From nobody Fri Nov 1 12:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516883290756793.8243864393934; Thu, 25 Jan 2018 04:28:10 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0DCE02234432F; Thu, 25 Jan 2018 04:22:33 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07E2522333776 for ; Thu, 25 Jan 2018 04:22:29 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id t74so14389804wme.3 for ; Thu, 25 Jan 2018 04:27:59 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:56 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KCdOyln+mQVUCOEz3XW4P5EGTBfcPZGrJS9xkHitAxk=; b=T1CUI2LrK/9UKGzX5rKIbC54Hw8v4ePIB1Vthi2qG/hv2YPUxp/LTHbDQNQSfuPDLX 6WlmF0epNTbCltIdYSvDdaU6e9tmpxGRdFwgt2tOEqj3yBquxe7erCz3rKf8Lzu6D8Ye 5F+FnYWqqgfQ4/qeFfBR4Mtjmu3Zs6tmzG+ZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KCdOyln+mQVUCOEz3XW4P5EGTBfcPZGrJS9xkHitAxk=; b=aaTbvg5RjaseWSW6Z6KSg9TmW52B7IZDu07bBZUJ2aP85Op0TGSQ0JP2C5Xttfj9sa 3SkrFNp41rhfzLVjFbVqk2O68qto8J/RQh5d7Tk9xJi6CgYTTeJ2k+P6iLJknVFCYERN qLrsjZyGl+Hdy1jL4SNSJ+5PPmcHJKLWELGSQtvuLM5+UglFqYvTaTaLWbpD3Hg9aA/X NYCR6rXzcLPHIKiCDDj6B3qk3Njm4Ivav1lHHI788b7vN1VFCC/ZmIJR9zyC6FjKzEiQ ygkAtO2sj0paPQwIJhMjoQpQSTbw6mUh8U6ayTVNt/1XjXtJlXTbR6m6/pYQPcj23HgZ ECtQ== X-Gm-Message-State: AKwxytdKA3ZU1rMmP72bERJj2DHALeAbxPgB317vllsEJ0Yc52lNKBKx mIogsNwWwEQljMEtVDqbhqWgFk56ZR8= X-Google-Smtp-Source: AH8x224LvaCa194n/9+qC3h8ggjZGM7BTwncp3OEynCP9+X3wmEHKF1gYj6tpkKnKjwbHpV1IJ4FTw== X-Received: by 10.28.51.12 with SMTP id z12mr7065374wmz.16.1516883277473; Thu, 25 Jan 2018 04:27:57 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:36 +0000 Message-Id: <20180125122736.5427-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 8/8] Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add menu options to the SynQuacer Platform menu screen to limit the maximum PCIe link speed for each RC individually. This may be useful to work around potential PCIe issues. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc = | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc = | 2 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c = | 4 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = | 107 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = | 12 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf = | 11 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni = | 28 +++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr = | 61 +++++++++++ Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h = | 23 +++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h = | 28 +++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLib.inf | 2 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 25 ++++- Silicon/Socionext/SynQuacer/SynQuacer.dec = | 5 + 13 files changed, 304 insertions(+), 6 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 86685d1dec3b..2d46b4515749 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -405,6 +405,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|30 =20 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings= "|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index b4b9239143bc..263b6454ff72 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -397,6 +397,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|30 =20 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings= "|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c b/Silico= n/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index 9af3dd942cdd..2a0fefbd423f 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -160,7 +160,9 @@ OnPciIoProtocolNotify ( // 2-port sibling of which samples were used in development) needs a // little nudge to get it to train the downstream links at Gen2 spee= d. // - RetrainAsm1184eDownstreamPort (PciIo); + if (mHiiSettings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1) { + RetrainAsm1184eDownstreamPort (PciIo); + } break; } } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 91c1b66ea1f8..b60607d05861 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -14,6 +14,36 @@ =20 #include "PlatformDxe.h" =20 +UINT64 mHiiSettingsVal; +SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +STATIC HII_VENDOR_DEVICE_PATH mPlatformDxeHiiVendorDevicePath =3D { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + SYNQUACER_PLATFORM_FORMSET_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + (UINT8) (END_DEVICE_PATH_LENGTH), + (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8) + } + } +}; + STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] =3D { { ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc @@ -144,6 +174,77 @@ SmmuEnableCoherentDma ( SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTE= R_WB); } =20 +STATIC +EFI_STATUS +InstallHiiPages ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HII_HANDLE HiiHandle; + EFI_HANDLE DriverHandle; + + DriverHandle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces (&DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + HiiHandle =3D HiiAddPackages (&gSynQuacerPlatformFormSetGuid, + DriverHandle, + PlatformDxeStrings, + PlatformDxeHiiBin, + NULL); + + if (HiiHandle =3D=3D NULL) { + gBS->UninstallMultipleProtocolInterfaces (DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + return EFI_OUT_OF_RESOURCES; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EnableSettingsForm ( + VOID + ) +{ + EFI_STATUS Status; + UINTN VarSize; + SYNQUACER_PLATFORM_VARSTORE_DATA Settings; + + VarSize =3D sizeof (Settings); + Status =3D gRT->GetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, NULL, &VarSize, &Setting= s); + if (Status =3D=3D EFI_NOT_FOUND) { + // + // Variable does not exist yet - create it + // + SetMem (&Settings, sizeof (Settings), 0); + Status =3D gRT->SetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_A= CCESS, + sizeof (Settings), &Settings); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiSetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiGetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + + return InstallHiiPages (); +} + EFI_STATUS EFIAPI PlatformDxeEntryPoint ( @@ -156,6 +257,9 @@ PlatformDxeEntryPoint ( UINTN DtbSize; EFI_HANDLE Handle; =20 + mHiiSettingsVal =3D PcdGet64 (PcdPlatformSettings); + mHiiSettings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; + Dtb =3D NULL; Status =3D DtPlatformLoadDtb (&Dtb, &DtbSize); if (!EFI_ERROR (Status)) { @@ -197,5 +301,8 @@ PlatformDxeEntryPoint ( Status =3D RegisterPcieNotifier (); ASSERT_EFI_ERROR (Status); =20 + Status =3D EnableSettingsForm (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index d1dad2a3eace..6fc4970cf472 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -16,18 +16,30 @@ #define __PLATFORM_DXE_H__ =20 #include +#include #include #include #include +#include #include +#include #include #include +#include #include #include +#include #include +#include #include #include =20 +extern UINT8 PlatformDxeHiiBin[]; +extern UINT8 PlatformDxeStrings[]; + +extern UINT64 mHiiSettingsVal; +extern SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + EFI_STATUS EFIAPI RegisterPcieNotifier ( diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index f075957d7456..de21ba33df75 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -25,6 +25,8 @@ [Defines] [Sources] Pci.c PlatformDxe.c + PlatformDxeHii.uni + PlatformDxeHii.vfr =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -37,18 +39,24 @@ [Packages] [LibraryClasses] BaseMemoryLib DebugLib + DevicePathLib DtPlatformDtbLoaderLib + HiiLib IoLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib UefiDriverEntryPoint UefiLib + UefiRuntimeServicesTableLib =20 [Guids] + gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid gSynQuacerNonDiscoverableI2cMasterGuid gSynQuacerNonDiscoverableRuntimeI2cMasterGuid + gSynQuacerPlatformFormSetGuid =20 [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES @@ -59,5 +67,8 @@ [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress =20 +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings + [Depex] TRUE diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni new file mode 100644 index 000000000000..0425d8e0d761 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -0,0 +1,28 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#langdef en-US "English" + +#string STR_FORM_SET_TITLE #language en-US "SynQuacer Platform= Settings" +#string STR_FORM_SET_TITLE_HELP #language en-US "Press to s= et platform specific options." + +#string STR_MAIN_FORM_TITLE #language en-US "SynQuacer Platform= Settings" +#string STR_NULL_STRING #language en-US "" + +#string STR_PCIE0_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #0 li= nk speed" +#string STR_PCIE1_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #1 li= nk speed" +#string STR_PCIE_MAX_SPEED_HELP #language en-US "The maximum speed = the PCIe root port is allowed to negotiate" + +#string STR_PCIE_MAX_SPEED_UNLIMITED #language en-US "Unlimited" +#string STR_PCIE_MAX_SPEED_GEN1 #language en-US "Gen1 (2.5 GT/s)" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr new file mode 100644 index 000000000000..0dd25c980b38 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include + +// +// EFI Variable attributes +// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_READ_ONLY 0x00000008 + +formset + guid =3D SYNQUACER_PLATFORM_FORMSET_GUID, + title =3D STRING_TOKEN(STR_FORM_SET_TITLE), + help =3D STRING_TOKEN(STR_FORM_SET_TITLE_HELP), + classguid =3D EFI_HII_PLATFORM_SETUP_FORMSET_GUID, + + efivarstore SYNQUACER_PLATFORM_VARSTORE_DATA, + attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLAT= ILE, // EFI variable attributes + name =3D SynQuacerPlatformSettings, + guid =3D SYNQUACER_PLATFORM_FORMSET_GUID; + + form formid =3D 0x1000, + title =3D STRING_TOKEN(STR_MAIN_FORM_TITLE); + + oneof varid =3D SynQuacerPlatformSettings.Pcie0MaxSpeed, + prompt =3D STRING_TOKEN(STR_PCIE0_MAX_SPEED_PROMPT), + help =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags =3D NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = =3D PCIE_MAX_SPEED_UNLIMITED, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value =3D P= CIE_MAX_SPEED_GEN1, flags =3D 0; + endoneof; + + oneof varid =3D SynQuacerPlatformSettings.Pcie1MaxSpeed, + prompt =3D STRING_TOKEN(STR_PCIE1_MAX_SPEED_PROMPT), + help =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags =3D NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = =3D PCIE_MAX_SPEED_UNLIMITED, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value =3D P= CIE_MAX_SPEED_GEN1, flags =3D 0; + endoneof; + + subtitle text =3D STRING_TOKEN(STR_NULL_STRING); + + endform; + +endformset; diff --git a/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformForm= Set.h b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h new file mode 100644 index 000000000000..9a70bb873056 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h @@ -0,0 +1,23 @@ +/** @file +* +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __SYNQUACER_PLATFORM_FORMSET_H__ +#define __SYNQUACER_PLATFORM_FORMSET_H__ + +#define SYNQUACER_PLATFORM_FORMSET_GUID \ + { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99= , 0x54 } } + +extern EFI_GUID gSynQuacerPlatformFormSetGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Sili= con/Socionext/SynQuacer/Include/Platform/VarStore.h new file mode 100644 index 000000000000..fb2db7479758 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -0,0 +1,28 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __VARSTORE_H__ +#define __VARSTORE_H__ + +#define SYNQUACER_PLATFORM_VARIABLE_NAME L"SynQuacerPlatformSettings" + +#define PCIE_MAX_SPEED_UNLIMITED 0x0 +#define PCIE_MAX_SPEED_GEN1 0x1 + +typedef struct { + UINT8 Pcie0MaxSpeed; + UINT8 Pcie1MaxSpeed; + UINT8 Reserved[6]; +} SYNQUACER_PLATFORM_VARSTORE_DATA; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuac= erPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 27fcba034418..e475529eaf58 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib =20 [FixedPcd] @@ -52,3 +53,4 @@ [FixedPcd] =20 [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask + gSynQuacerTokenSpaceGuid.PcdPlatformSettings diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index bea40e3dcfe8..1bdfd012b902 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -18,9 +18,11 @@ #include #include #include +#include #include #include #include +#include #include =20 #define IATU_VIEWPORT_OFF 0x900 @@ -268,7 +270,8 @@ PciInitControllerPost ( IN EFI_PHYSICAL_ADDRESS DbiBase, IN EFI_PHYSICAL_ADDRESS ConfigBase, IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge + IN CONST PCI_ROOT_BRIDGE *RootBridge, + IN BOOLEAN EnableGen2Speed ) { // 4: Set Bifurcation 1=3Ddisable 4=3Dable @@ -312,8 +315,10 @@ PciInitControllerPost ( EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); =20 - // Force link speed change to Gen2 at link up - MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + if (EnableGen2Speed) { + // Force link speed change to Gen2 at link up + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + } =20 // Region 0: MMIO32 range ConfigureWindow (DbiBase, 0, @@ -392,7 +397,16 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - UINTN Idx; + UINTN Idx; + UINT64 SettingsVal; + SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; + BOOLEAN EnableGen2Speed[2]; + + SettingsVal =3D PcdGet64 (PcdPlatformSettings); + Settings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; + + EnableGen2Speed[0] =3D (Settings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1= ); + EnableGen2Speed[1] =3D (Settings->Pcie1MaxSpeed !=3D PCIE_MAX_SPEED_GEN1= ); =20 for (Idx =3D 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { @@ -414,7 +428,8 @@ SynQuacerPciHostBridgeLibConstructor ( mBaseAddresses[Idx].DbiBase, mBaseAddresses[Idx].ConfigBase, mBaseAddresses[Idx].IoMemBase, - &mPciRootBridges[Idx]); + &mPciRootBridges[Idx], + EnableGen2Speed[Idx]); } } =20 diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index 76529e3c2164..eb4fc4ace2f7 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -27,6 +27,8 @@ [Guids] =20 gSynQuacerPlatformDxeFileGuid =3D { 0xac422cc1, 0xd916, 0x489a, { 0xb1, = 0x65, 0x53, 0x6f, 0xdf, 0xc6, 0x33, 0xc2 } } =20 + gSynQuacerPlatformFormSetGuid =3D { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, = 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99, 0x54 } } + [Ppis] gSynQuacerDramInfoPpiGuid =3D { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46= , 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } =20 @@ -45,3 +47,6 @@ [PcdsFixedAtBuild] [PcdsPatchableInModule, PcdsDynamic] # Enable both RC #0 and RC #1 by default gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 + +[PcdsDynamic] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|0x0|UINT64|0x00000008 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel