From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516883270169351.11526442172965; Thu, 25 Jan 2018 04:27:50 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4668F222A337A; Thu, 25 Jan 2018 04:22:19 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA458222A3348 for ; Thu, 25 Jan 2018 04:22:17 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id f71so14287234wmf.0 for ; Thu, 25 Jan 2018 04:27:47 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:44 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EdvE6GL7G1yfSByioV73p5dEQEERz0ddDEdPTQg9Nrk=; b=TC1ka7syAXhpBnAinwf70dL2VsajAGeh1Go66W6AqtuMHf3oXVyWMzG3OQr0UWkruB bdE98UhR9VuratyNQ9Xpr33m+bEFBw7mzuEHmVA7FbGLaumywJjD5RMuI3lbJZ3REG4o yYTZJaULXy30KouMSx8IcUoI/IF2lJghiU9MU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EdvE6GL7G1yfSByioV73p5dEQEERz0ddDEdPTQg9Nrk=; b=KoWnbM10SKt3bvM0epnRKjnumEAfsBErVCNM2qKP7IWjRAWKd1vmPQX1fvrkmZVY6u Esu5SOVzoBx4VsFpJPWzc6S2CzD5zqHJ2RJvjuS4RT7DLWYxuFYJwpf8oUUhagkqkqx6 iLyXtUT+t6Idg5gmGdXAeBZGhRa6pQyYVIuJQ5101oe7o1lVO4yOLGu+cTEbduRRxy7g UPTv/lSJWg3gQTv669gPYfmOnTwVBmvhQWhNhiXuEvZAPjMfelcpcKyQ0e52SH6yCIID O3GjBYE8Q0DwCzFxOsz6fV1dGsfcL476mRFhG+q6+RfllXuEVX87SBEk/rRvvaa7bmoT BQWw== X-Gm-Message-State: AKwxytc3Pnk3hUGHzJwR+a5j0WcmRCFBNozcDJh4945zF0Duc19KaWiM KmEsRmTMqJDVJTyQ5KlDHY7jj1vaP/U= X-Google-Smtp-Source: AH8x226sRxIEThw+C0/h816fnAZY/H+eErXtrDAq2YQNiacZXluFWpgfcyXq4GUr+ioxxo3Q2LGC1w== X-Received: by 10.28.154.67 with SMTP id c64mr7987002wme.125.1516883265610; Thu, 25 Jan 2018 04:27:45 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:29 +0000 Message-Id: <20180125122736.5427-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/8] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The ASM1061 SATA controller integrated into the DeveloperBox board emits too much electromagnetic radiation, so it needs spread spectrum mode enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c =3D> Pci.c}= | 83 +++++++++++++++----- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf |= 2 +- 2 files changed, 64 insertions(+), 21 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c similarity index 64% rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index 874e83a649b5..9af3dd942cdd 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -15,9 +15,12 @@ #include "PlatformDxe.h" =20 #define ASMEDIA_VID 0x1b21 +#define ASM1061_PID 0x0612 #define ASM1182E_PID 0x1182 #define ASM1184E_PID 0x1184 =20 +#define ASM1061_SSC_OFFSET 0xA10 + #define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 #define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSE= T + \ OFFSET_OF (PCI_CAPABILITY_PCI= EXP, \ @@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort ( IN EFI_PCI_IO_PROTOCOL *PciIo ) { - UINT16 PciVidPid[2]; EFI_STATUS Status; PCIE_CAP Cap; PCI_REG_PCIE_LINK_CONTROL LinkControl; =20 - Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OF= FSET, - ARRAY_SIZE (PciVidPid), &PciVidPid); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", - __FUNCTION__, Status)); - return; - } - - if (PciVidPid[0] !=3D ASMEDIA_VID || - (PciVidPid[1] !=3D ASM1182E_PID && PciVidPid[1] !=3D ASM1184E_PID)) { - return; - } - // // The upstream and downstream ports share the same PID/VID, so check // the port type. This assumes the PCIe Express capability block lives @@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort ( =20 STATIC VOID +EnableAsm1061SpreadSpectrum ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + EFI_STATUS Status; + UINT8 SscVal; + + DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n", + __FUNCTION__)); + + // SSC mode 0~-4000 ppm, 1:1 modulation + + SscVal =3D 0; + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFS= ET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); + + MemoryFence (); + gBS->Stall (1); // delay at least 100 ns between writes of the same regi= ster + + SscVal =3D 1; + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFS= ET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID EFIAPI OnPciIoProtocolNotify ( IN EFI_EVENT Event, @@ -101,6 +118,7 @@ OnPciIoProtocolNotify ( EFI_STATUS Status; EFI_HANDLE HandleBuffer; UINTN BufferSize; + UINT16 PciVidPid[2]; =20 while (TRUE) { BufferSize =3D sizeof (EFI_HANDLE); @@ -114,12 +132,37 @@ OnPciIoProtocolNotify ( (VOID **)&PciIo); ASSERT_EFI_ERROR (Status); =20 - // - // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its - // 2-port sibling of which samples were used in development) needs a - // little nudge to get it to train the downstream links at Gen2 speed. - // - RetrainAsm1184eDownstreamPort (PciIo); + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_= OFFSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n= ", + __FUNCTION__, Status)); + continue; + } + + if (PciVidPid[0] !=3D ASMEDIA_VID) { + continue; + } + + switch (PciVidPid[1]) { + case ASM1061_PID: + // + // The ASM1061 SATA controller as integrated into the DeveloperBox d= esign + // emits too much electromagnetic radiation. So enable spread spectr= um + // mode. + // + EnableAsm1061SpreadSpectrum (PciIo); + break; + case ASM1182E_PID: + case ASM1184E_PID: + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 spee= d. + // + RetrainAsm1184eDownstreamPort (PciIo); + break; + } } } =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 7d3b88a5b52e..766f4041c826 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,7 +23,7 @@ [Defines] ENTRY_POINT =3D PlatformDxeEntryPoint =20 [Sources] - Asmedia118x.c + Pci.c PlatformDxe.c =20 [Packages] --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516883272804152.4674174209963; Thu, 25 Jan 2018 04:27:52 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B14A0222A337C; Thu, 25 Jan 2018 04:22:21 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8D4B4222A337C for ; Thu, 25 Jan 2018 04:22:19 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id r78so14627049wme.0 for ; Thu, 25 Jan 2018 04:27:48 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:46 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X/xNVgMJvcVN5+bQMF7p4ydDnTMNg4KvabrvZNklBYs=; b=bsx3hm9IubmCHC2JXfOmrIjkPGqsapZ/db4jHc8zTLt9ZMqb/8x2MD1TTWUvgBBEmG CKi2wD6TTHkco3+6PddHeECBoN1Aq9PbafjnzsooVnQfQYLARj+CS+RNlOGKOWAYTyJj lleZ94FFdjQxAUk/XwMLYF0/rQ6hPrHlhF8Pw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X/xNVgMJvcVN5+bQMF7p4ydDnTMNg4KvabrvZNklBYs=; b=RDsFPJHeH3WyBHaLQxRi5Gw6V5QAmQpOMWuU7rFM53ACOgef35itBGn8TUqTWhciv3 Amj3L3reLhdCZftwhVGD5RV6yKPjNw/csAVVwAbo+4I72fylYjsIKRNr5KbeDsIcKFKn HiHB+MisGpnRUN4p+7N2ONj2UEVtLGDYQiv03dI3knUCmgr1iBKBTY8BUy1RzvJj6PWn FwWWewbKPT0o7Mov99KikN17eiR0wHz/w8yvn7z3D1qEbeRjPZqUE+2cw9V2NIGjNxO1 skSaHoPjUjmf1OAG0TdXPXtqXF5PWMa1hZtoT5BjBeWZ71JA1f0xLzaTxp2BJIjj8OEv Y1XA== X-Gm-Message-State: AKwxytemaWAXMs2vTwSnEbQgEkx/PNUm6Elt4vouEYLJUPJ/kv6cwq8k LrlIBHrYElFPIe/xTtROaQUqp4Ji4oE= X-Google-Smtp-Source: AH8x227sWnnlptfO8Loe7EOC68GFjxKk0KPL5UWlTzJxz/7xiK2avg43qoq4IeTH4wbjFmdiqv7Y8g== X-Received: by 10.28.38.133 with SMTP id m127mr7102109wmm.40.1516883267206; Thu, 25 Jan 2018 04:27:47 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:30 +0000 Message-Id: <20180125122736.5427-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/8] Silicon: fix typo in gPcf8563RealTimeClockLibI2cMasterProtocolGuid X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Do a global replace of gPcf8563RealTimeClockLibI2cMasterProtolGuid with gPcf8563RealTimeClockLibI2cMasterProtocolGuid. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | = 2 +- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | = 2 +- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | = 4 ++-- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | = 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | = 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClo= ckLib.c b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockL= ib.c index 67f8e7de4025..6bc4aef28849 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c @@ -373,7 +373,7 @@ LibRtcInitialize ( // BufferSize =3D sizeof (EFI_HANDLE); Status =3D gBS->LocateHandle (ByProtocol, - &gPcf8563RealTimeClockLibI2cMasterProtolGuid, NULL, + &gPcf8563RealTimeClockLibI2cMasterProtocolGuid, NULL, &BufferSize, &mI2cMasterHandle); ASSERT_EFI_ERROR (Status); =20 diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClo= ckLib.dec b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeCloc= kLib.dec index 3849056f164a..94c4a3f1ef4c 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.d= ec +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.d= ec @@ -22,7 +22,7 @@ [Guids] gPcf8563RealTimeClockLibTokenSpaceGuid =3D { 0xaaf5b169, 0x93a0, 0x4d60,= { 0xba, 0xe4, 0x06, 0x07, 0x92, 0x8e, 0x63, 0xdd }} =20 [Protocols] - gPcf8563RealTimeClockLibI2cMasterProtolGuid =3D { 0xa6af18ae, 0x3bd5, 0x= 4af9, { 0xbb, 0x6a, 0xdb, 0x85, 0x07, 0x62, 0x81, 0x38 }} + gPcf8563RealTimeClockLibI2cMasterProtocolGuid =3D { 0xa6af18ae, 0x3bd5, = 0x4af9, { 0xbb, 0x6a, 0xdb, 0x85, 0x07, 0x62, 0x81, 0x38 }} =20 [PcdsFixedAtBuild] gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51|UINT8|0x0= 0000001 diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClo= ckLib.inf b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeCloc= kLib.inf index 9907e343ba78..1a9a6f6c9cf3 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.i= nf +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.i= nf @@ -42,11 +42,11 @@ [Guids] [Protocols] gEfiDriverBindingProtocolGuid ## CONSUMES gEfiI2cMasterProtocolGuid ## CONSUMES - gPcf8563RealTimeClockLibI2cMasterProtolGuid ## CONSUMES + gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES =20 [FixedPcd] gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cBusFrequency =20 [Depex] - gPcf8563RealTimeClockLibI2cMasterProtolGuid + gPcf8563RealTimeClockLibI2cMasterProtocolGuid diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 098a4dbd324e..91c1b66ea1f8 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -183,7 +183,7 @@ PlatformDxeEntryPoint ( // through the I2C driver stack (which cannot be used at runtime) // Status =3D gBS->InstallProtocolInterface (&Handle, - &gPcf8563RealTimeClockLibI2cMasterProtolGuid, + &gPcf8563RealTimeClockLibI2cMasterProtocolGuid, EFI_NATIVE_INTERFACE, NULL); ASSERT_EFI_ERROR (Status); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 766f4041c826..4d6a1d637922 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -53,7 +53,7 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gEfiPciIoProtocolGuid ## CONSUMES - gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES + gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES =20 [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151688327519886.20698860536243; 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Thu, 25 Jan 2018 04:27:48 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:31 +0000 Message-Id: <20180125122736.5427-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/8] Silicon/NXP/Pcf8563RealTimeClockLib: avoid driver binding protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instead of registering a notification callback on the driver binding protocol, and attempting to connect our I2C master handle each time a new driver is registered, switch to the more obvious approach of registering a notification callback on the I2C master protocol directly. The original code was written under the assumption that it would make the RTC available at an earlier time, but given that all handles that are created during the execution of a driver entry point are connected by DXE core right away (i.e., before StartImage() returns), this is not really necessary, and in fact, may result in the driver already having been connected by the time we attempt to connect it. Note that it is now up to the platform to ensure that ConnectController() is called for the handle if DXE core does not call it by itself, or does call it but at a time when no I2C master protocol driver is available yet. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | = 31 ++++++++------------ Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | = 1 - 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClo= ckLib.c b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockL= ib.c index 6bc4aef28849..fb58e1feb424 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c @@ -41,7 +41,7 @@ #define EPOCH_BASE 2000 =20 STATIC EFI_HANDLE mI2cMasterHandle; -STATIC VOID *mDriverEventRegistration; +STATIC VOID *mI2cMasterEventRegistration; STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; =20 @@ -263,12 +263,12 @@ LibSetWakeupTime ( =20 STATIC VOID -DriverRegistrationEvent ( +I2cMasterRegistrationEvent ( IN EFI_EVENT Event, IN VOID *Context ) { - EFI_HANDLE Handle[2]; + EFI_HANDLE Handle; UINTN BufferSize; EFI_STATUS Status; EFI_I2C_MASTER_PROTOCOL *I2cMaster; @@ -280,10 +280,10 @@ DriverRegistrationEvent ( do { BufferSize =3D sizeof (EFI_HANDLE); Status =3D gBS->LocateHandle (ByRegisterNotify, - &gEfiDriverBindingProtocolGuid, - mDriverEventRegistration, + &gEfiI2cMasterProtocolGuid, + mI2cMasterEventRegistration, &BufferSize, - Handle); + &Handle); if (EFI_ERROR (Status)) { if (Status !=3D EFI_NOT_FOUND) { DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n", @@ -292,12 +292,7 @@ DriverRegistrationEvent ( break; } =20 - // - // Check if we can connect our handle to this driver. - // - Handle[1] =3D NULL; - Status =3D gBS->ConnectController (mI2cMasterHandle, Handle, NULL, FAL= SE); - if (EFI_ERROR (Status)) { + if (Handle !=3D mI2cMasterHandle) { continue; } =20 @@ -378,16 +373,16 @@ LibRtcInitialize ( ASSERT_EFI_ERROR (Status); =20 // - // Register a protocol registration notification callback on the driver - // binding protocol so we can attempt to connect our I2C master to it - // as soon as it appears. + // Register a protocol registration notification callback on the I2C mas= ter + // protocol. This will notify us even if the protocol instance we are lo= oking + // for has already been installed. // EfiCreateProtocolNotifyEvent ( - &gEfiDriverBindingProtocolGuid, + &gEfiI2cMasterProtocolGuid, TPL_CALLBACK, - DriverRegistrationEvent, + I2cMasterRegistrationEvent, NULL, - &mDriverEventRegistration); + &mI2cMasterEventRegistration); =20 // // Register for the virtual address change event diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClo= ckLib.inf b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeCloc= kLib.inf index 1a9a6f6c9cf3..e232902c6b5d 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.i= nf +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.i= nf @@ -40,7 +40,6 @@ [Guids] gEfiEventVirtualAddressChangeGuid =20 [Protocols] - gEfiDriverBindingProtocolGuid ## CONSUMES gEfiI2cMasterProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES =20 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Remove a %r without an associated parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 2 = +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI= 2cDxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cD= xe.c index c3703dfb6c33..46c512a20151 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c @@ -335,7 +335,7 @@ SynQuacerI2cStartRequest ( } =20 if (MmioRead8 (I2c->MmioBase + F_I2C_REG_BSR) & F_I2C_BSR_LRB) { - BOOTTIME_DEBUG ((DEBUG_WARN, "%a: No ack received - %r\n", __FUNCTIO= N__)); + BOOTTIME_DEBUG ((DEBUG_WARN, "%a: No ack received\n", __FUNCTION__)); Status =3D EFI_DEVICE_ERROR; break; } --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 25 Jan 2018 04:27:51 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+z4ovW6TIaaC4nkL3RLs3j5MTR8XeOuNge1td5JF4Pg=; b=TR3QqaHjQQChvN0RdhHVcipSbduR5qUXfCNTLYnQq8ZfHXyC4jV4KrbUyYGb2E1Pny wGhu9zZ7c5sT1qa2LBRY2cJ99DAJgrMcZef32k8t1bwR1oih5PEeeCwjMxwz2XQTQvXL 7bgnVScjWBxALDf+htgKszzCLZvODzw3YBbKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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charset="utf-8" To ensure that the I2C master protocol is installed immediately onto the handles created by PlatformDxe in its entry point, force the SynQuacerI2cDxe driver to be loaded before PlatformDxe. These handles are recursively connected by the DXE core as soon as they appear, and so ensuring that the I2C master protocol driver is available at this time will ensure that these handles will be connected to it right away. This is useful when implementations of architectural protocols such as RTC or the EFI variable store, which should become available long before the ordinary dispatch of UEFI driver model drivers is started at the end of DXE, are based on I2C. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | = 2 +- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | = 2 +- Silicon/Socionext/SynQuacer/SynQuacer.dec | = 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 4d6a1d637922..f075957d7456 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION =3D 0x0001001A BASE_NAME =3D PlatformDxe - FILE_GUID =3D ac422cc1-d916-489a-b165-536fdfc633c2 + FILE_GUID =3D ac422cc1-d916-489a-b165-536fdfc633c2 = # gSynQuacerPlatformDxeFileGuid MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D PlatformDxeEntryPoint diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI= 2cDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2= cDxe.inf index fa715366878c..325816ba0b88 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.i= nf +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.i= nf @@ -56,4 +56,4 @@ [FixedPcd] gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock =20 [Depex] - TRUE + BEFORE gSynQuacerPlatformDxeFileGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index a21f12b5bc32..76529e3c2164 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -25,6 +25,8 @@ [Guids] gSynQuacerNonDiscoverableI2cMasterGuid =3D { 0x364ee675, 0x9e44, 0x42b7,= { 0xa5, 0xe4, 0x92, 0x84, 0xdb, 0x85, 0xda, 0x09 } } gSynQuacerNonDiscoverableRuntimeI2cMasterGuid =3D { 0x5f35aa9b, 0x8c6f, = 0x4828, { 0xbd, 0x44, 0x7c, 0xc0, 0xeb, 0x2d, 0xfe, 0xb9 } } =20 + gSynQuacerPlatformDxeFileGuid =3D { 0xac422cc1, 0xd916, 0x489a, { 0xb1, = 0x65, 0x53, 0x6f, 0xdf, 0xc6, 0x33, 0xc2 } } + [Ppis] gSynQuacerDramInfoPpiGuid =3D { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46= , 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } =20 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Align the UART DT nodes: - use 'uart' not 'fuart' as node name for the second serial port - create an alias 'serial1' for the second serial port - use UART clock reference instead of hardcoded frequency - split 'clocks' property into 1 cell per phandle Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37a3981f0360..7c3518facb98 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -32,6 +32,7 @@ =20 aliases { serial0 =3D &soc_uart0; + serial1 =3D &fuart; }; =20 chosen { @@ -436,15 +437,16 @@ compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0x0 0x2a400000 0x0 0x1000>; interrupts =3D ; - clocks =3D <&clk_uart &clk_apb>; + clocks =3D <&clk_uart>, <&clk_apb>; clock-names =3D "uartclk", "apb_pclk"; }; =20 - fuart: fuart@51040000 { + fuart: uart@51040000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x0 0x51040000 0x0 0x1000>; interrupts =3D ; - clock-frequency =3D <62500000>; + clocks =3D <&clk_uart>, <&clk_apb>; + clock-names =3D "baudclk", "apb_pclk"; reg-io-width =3D <4>; reg-shift =3D <2>; }; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516883287634165.22015986672784; Thu, 25 Jan 2018 04:28:07 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B098E22344331; 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Thu, 25 Jan 2018 04:27:55 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:35 +0000 Message-Id: <20180125122736.5427-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 7/8] Silicon/SynQuacer/DeviceTree: update NETSEC DT node to latest binding X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The upstream version of the Linux NETSEC driver expects the PHY DT node to appear under a MDIO subnode, so fix this in the device tree. Fix the node name as well, this should be 'ethernet' not 'netsec', and add a clock-names property describing the single clock reference as 'phy_ref_clk'. Also, move the PHY subnode into the per-platform .dts file so we can set the unit address in the node name. This is necessary because recent versions of the DT compiler are more finicky about this. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++= ++----------- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Sili= con/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index d2cd7ef90e6f..488c51a0f793 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -44,3 +44,10 @@ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD2= 7", "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD3= 1"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + }; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 7c3518facb98..6ee7a0b7ccb4 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -457,25 +457,23 @@ #clock-cells =3D <0>; }; =20 - eth0: netsec@522D0000 { - compatible =3D "socionext,synquacer-netsec"; - reg =3D <0 0x522d0000 0x0 0x10000>, - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; - interrupts =3D ; - clocks =3D <&clk_netsec>; - phy-mode =3D "rgmii"; - max-speed =3D <1000>; - max-frame-size =3D <9000>; - phy-handle =3D <ðphy0>; - dma-coherent; + ethernet@522d0000 { + compatible =3D "socionext,synquacer-netsec"; + reg =3D <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&clk_netsec>; + clock-names =3D "phy_ref_clk"; + phy-mode =3D "rgmii"; + max-speed =3D <1000>; + max-frame-size =3D <9000>; + phy-handle =3D <&phy_netsec>; + dma-coherent; =20 + mdio_netsec: mdio { #address-cells =3D <1>; #size-cells =3D <0>; - - ethphy0: ethernet-phy { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D ; - }; + }; }; =20 smmu: iommu@582c0000 { diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts = b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index 132fd370a71b..97fddfedcb46 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -34,3 +34,10 @@ &sdhci { status =3D "okay"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Nov 1 10:35:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516883290756793.8243864393934; Thu, 25 Jan 2018 04:28:10 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0DCE02234432F; Thu, 25 Jan 2018 04:22:33 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07E2522333776 for ; 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Thu, 25 Jan 2018 04:27:57 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:36 +0000 Message-Id: <20180125122736.5427-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 8/8] Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add menu options to the SynQuacer Platform menu screen to limit the maximum PCIe link speed for each RC individually. This may be useful to work around potential PCIe issues. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc = | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc = | 2 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c = | 4 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = | 107 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = | 12 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf = | 11 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni = | 28 +++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr = | 61 +++++++++++ Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h = | 23 +++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h = | 28 +++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLib.inf | 2 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 25 ++++- Silicon/Socionext/SynQuacer/SynQuacer.dec = | 5 + 13 files changed, 304 insertions(+), 6 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 86685d1dec3b..2d46b4515749 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -405,6 +405,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|30 =20 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings= "|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index b4b9239143bc..263b6454ff72 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -397,6 +397,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|30 =20 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings= "|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c b/Silico= n/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index 9af3dd942cdd..2a0fefbd423f 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -160,7 +160,9 @@ OnPciIoProtocolNotify ( // 2-port sibling of which samples were used in development) needs a // little nudge to get it to train the downstream links at Gen2 spee= d. // - RetrainAsm1184eDownstreamPort (PciIo); + if (mHiiSettings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1) { + RetrainAsm1184eDownstreamPort (PciIo); + } break; } } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 91c1b66ea1f8..b60607d05861 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -14,6 +14,36 @@ =20 #include "PlatformDxe.h" =20 +UINT64 mHiiSettingsVal; +SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +STATIC HII_VENDOR_DEVICE_PATH mPlatformDxeHiiVendorDevicePath =3D { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + SYNQUACER_PLATFORM_FORMSET_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + (UINT8) (END_DEVICE_PATH_LENGTH), + (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8) + } + } +}; + STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] =3D { { ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc @@ -144,6 +174,77 @@ SmmuEnableCoherentDma ( SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTE= R_WB); } =20 +STATIC +EFI_STATUS +InstallHiiPages ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HII_HANDLE HiiHandle; + EFI_HANDLE DriverHandle; + + DriverHandle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces (&DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + HiiHandle =3D HiiAddPackages (&gSynQuacerPlatformFormSetGuid, + DriverHandle, + PlatformDxeStrings, + PlatformDxeHiiBin, + NULL); + + if (HiiHandle =3D=3D NULL) { + gBS->UninstallMultipleProtocolInterfaces (DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + return EFI_OUT_OF_RESOURCES; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EnableSettingsForm ( + VOID + ) +{ + EFI_STATUS Status; + UINTN VarSize; + SYNQUACER_PLATFORM_VARSTORE_DATA Settings; + + VarSize =3D sizeof (Settings); + Status =3D gRT->GetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, NULL, &VarSize, &Setting= s); + if (Status =3D=3D EFI_NOT_FOUND) { + // + // Variable does not exist yet - create it + // + SetMem (&Settings, sizeof (Settings), 0); + Status =3D gRT->SetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_A= CCESS, + sizeof (Settings), &Settings); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiSetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiGetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + + return InstallHiiPages (); +} + EFI_STATUS EFIAPI PlatformDxeEntryPoint ( @@ -156,6 +257,9 @@ PlatformDxeEntryPoint ( UINTN DtbSize; EFI_HANDLE Handle; =20 + mHiiSettingsVal =3D PcdGet64 (PcdPlatformSettings); + mHiiSettings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; + Dtb =3D NULL; Status =3D DtPlatformLoadDtb (&Dtb, &DtbSize); if (!EFI_ERROR (Status)) { @@ -197,5 +301,8 @@ PlatformDxeEntryPoint ( Status =3D RegisterPcieNotifier (); ASSERT_EFI_ERROR (Status); =20 + Status =3D EnableSettingsForm (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index d1dad2a3eace..6fc4970cf472 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -16,18 +16,30 @@ #define __PLATFORM_DXE_H__ =20 #include +#include #include #include #include +#include #include +#include #include #include +#include #include #include +#include #include +#include #include #include =20 +extern UINT8 PlatformDxeHiiBin[]; +extern UINT8 PlatformDxeStrings[]; + +extern UINT64 mHiiSettingsVal; +extern SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + EFI_STATUS EFIAPI RegisterPcieNotifier ( diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index f075957d7456..de21ba33df75 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -25,6 +25,8 @@ [Defines] [Sources] Pci.c PlatformDxe.c + PlatformDxeHii.uni + PlatformDxeHii.vfr =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -37,18 +39,24 @@ [Packages] [LibraryClasses] BaseMemoryLib DebugLib + DevicePathLib DtPlatformDtbLoaderLib + HiiLib IoLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib UefiDriverEntryPoint UefiLib + UefiRuntimeServicesTableLib =20 [Guids] + gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid gSynQuacerNonDiscoverableI2cMasterGuid gSynQuacerNonDiscoverableRuntimeI2cMasterGuid + gSynQuacerPlatformFormSetGuid =20 [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES @@ -59,5 +67,8 @@ [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress =20 +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings + [Depex] TRUE diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni new file mode 100644 index 000000000000..0425d8e0d761 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -0,0 +1,28 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#langdef en-US "English" + +#string STR_FORM_SET_TITLE #language en-US "SynQuacer Platform= Settings" +#string STR_FORM_SET_TITLE_HELP #language en-US "Press to s= et platform specific options." + +#string STR_MAIN_FORM_TITLE #language en-US "SynQuacer Platform= Settings" +#string STR_NULL_STRING #language en-US "" + +#string STR_PCIE0_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #0 li= nk speed" +#string STR_PCIE1_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #1 li= nk speed" +#string STR_PCIE_MAX_SPEED_HELP #language en-US "The maximum speed = the PCIe root port is allowed to negotiate" + +#string STR_PCIE_MAX_SPEED_UNLIMITED #language en-US "Unlimited" +#string STR_PCIE_MAX_SPEED_GEN1 #language en-US "Gen1 (2.5 GT/s)" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr new file mode 100644 index 000000000000..0dd25c980b38 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include + +// +// EFI Variable attributes +// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_READ_ONLY 0x00000008 + +formset + guid =3D SYNQUACER_PLATFORM_FORMSET_GUID, + title =3D STRING_TOKEN(STR_FORM_SET_TITLE), + help =3D STRING_TOKEN(STR_FORM_SET_TITLE_HELP), + classguid =3D EFI_HII_PLATFORM_SETUP_FORMSET_GUID, + + efivarstore SYNQUACER_PLATFORM_VARSTORE_DATA, + attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLAT= ILE, // EFI variable attributes + name =3D SynQuacerPlatformSettings, + guid =3D SYNQUACER_PLATFORM_FORMSET_GUID; + + form formid =3D 0x1000, + title =3D STRING_TOKEN(STR_MAIN_FORM_TITLE); + + oneof varid =3D SynQuacerPlatformSettings.Pcie0MaxSpeed, + prompt =3D STRING_TOKEN(STR_PCIE0_MAX_SPEED_PROMPT), + help =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags =3D NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = =3D PCIE_MAX_SPEED_UNLIMITED, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value =3D P= CIE_MAX_SPEED_GEN1, flags =3D 0; + endoneof; + + oneof varid =3D SynQuacerPlatformSettings.Pcie1MaxSpeed, + prompt =3D STRING_TOKEN(STR_PCIE1_MAX_SPEED_PROMPT), + help =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags =3D NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = =3D PCIE_MAX_SPEED_UNLIMITED, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value =3D P= CIE_MAX_SPEED_GEN1, flags =3D 0; + endoneof; + + subtitle text =3D STRING_TOKEN(STR_NULL_STRING); + + endform; + +endformset; diff --git a/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformForm= Set.h b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h new file mode 100644 index 000000000000..9a70bb873056 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h @@ -0,0 +1,23 @@ +/** @file +* +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __SYNQUACER_PLATFORM_FORMSET_H__ +#define __SYNQUACER_PLATFORM_FORMSET_H__ + +#define SYNQUACER_PLATFORM_FORMSET_GUID \ + { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99= , 0x54 } } + +extern EFI_GUID gSynQuacerPlatformFormSetGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Sili= con/Socionext/SynQuacer/Include/Platform/VarStore.h new file mode 100644 index 000000000000..fb2db7479758 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -0,0 +1,28 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __VARSTORE_H__ +#define __VARSTORE_H__ + +#define SYNQUACER_PLATFORM_VARIABLE_NAME L"SynQuacerPlatformSettings" + +#define PCIE_MAX_SPEED_UNLIMITED 0x0 +#define PCIE_MAX_SPEED_GEN1 0x1 + +typedef struct { + UINT8 Pcie0MaxSpeed; + UINT8 Pcie1MaxSpeed; + UINT8 Reserved[6]; +} SYNQUACER_PLATFORM_VARSTORE_DATA; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuac= erPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 27fcba034418..e475529eaf58 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib =20 [FixedPcd] @@ -52,3 +53,4 @@ [FixedPcd] =20 [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask + gSynQuacerTokenSpaceGuid.PcdPlatformSettings diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index bea40e3dcfe8..1bdfd012b902 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -18,9 +18,11 @@ #include #include #include +#include #include #include #include +#include #include =20 #define IATU_VIEWPORT_OFF 0x900 @@ -268,7 +270,8 @@ PciInitControllerPost ( IN EFI_PHYSICAL_ADDRESS DbiBase, IN EFI_PHYSICAL_ADDRESS ConfigBase, IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge + IN CONST PCI_ROOT_BRIDGE *RootBridge, + IN BOOLEAN EnableGen2Speed ) { // 4: Set Bifurcation 1=3Ddisable 4=3Dable @@ -312,8 +315,10 @@ PciInitControllerPost ( EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); =20 - // Force link speed change to Gen2 at link up - MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + if (EnableGen2Speed) { + // Force link speed change to Gen2 at link up + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + } =20 // Region 0: MMIO32 range ConfigureWindow (DbiBase, 0, @@ -392,7 +397,16 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - UINTN Idx; + UINTN Idx; + UINT64 SettingsVal; + SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; + BOOLEAN EnableGen2Speed[2]; + + SettingsVal =3D PcdGet64 (PcdPlatformSettings); + Settings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; + + EnableGen2Speed[0] =3D (Settings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1= ); + EnableGen2Speed[1] =3D (Settings->Pcie1MaxSpeed !=3D PCIE_MAX_SPEED_GEN1= ); =20 for (Idx =3D 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { @@ -414,7 +428,8 @@ SynQuacerPciHostBridgeLibConstructor ( mBaseAddresses[Idx].DbiBase, mBaseAddresses[Idx].ConfigBase, mBaseAddresses[Idx].IoMemBase, - &mPciRootBridges[Idx]); + &mPciRootBridges[Idx], + EnableGen2Speed[Idx]); } } =20 diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index 76529e3c2164..eb4fc4ace2f7 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -27,6 +27,8 @@ [Guids] =20 gSynQuacerPlatformDxeFileGuid =3D { 0xac422cc1, 0xd916, 0x489a, { 0xb1, = 0x65, 0x53, 0x6f, 0xdf, 0xc6, 0x33, 0xc2 } } =20 + gSynQuacerPlatformFormSetGuid =3D { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, = 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99, 0x54 } } + [Ppis] gSynQuacerDramInfoPpiGuid =3D { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46= , 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } =20 @@ -45,3 +47,6 @@ [PcdsFixedAtBuild] [PcdsPatchableInModule, PcdsDynamic] # Enable both RC #0 and RC #1 by default gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 + +[PcdsDynamic] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|0x0|UINT64|0x00000008 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel