From nobody Fri Nov 1 10:29:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1516795047686517.722324103651; Wed, 24 Jan 2018 03:57:27 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E21AE21E48F2B; Wed, 24 Jan 2018 03:51:53 -0800 (PST) Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D2DF222A337C for ; Wed, 24 Jan 2018 03:51:51 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id g38so3760022wrd.2 for ; Wed, 24 Jan 2018 03:57:20 -0800 (PST) Received: from localhost.localdomain ([160.163.176.196]) by smtp.gmail.com with ESMTPSA id 204sm253297wmx.0.2018.01.24.03.57.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2018 03:57:17 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ne8KS6UnBZjtarelcKQeQ9K2KLQc4xcOFss3DT4CwJA=; b=ZfHSF6TmFZ8N6LG4dUksX+ebR9z09s7l5DrEahGVRE8eCOUFY/eiBbzJImhVuuY9y+ HPYLjIwyylTB4R8Tshg72KqDXy2zO7saiG4B7un28Wwtq5ryOqu5Zv26SQjLzIGa1qL3 NTcb+lUjgvVt7dD8rK4J+ZREzW2LzGT8lgGIo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ne8KS6UnBZjtarelcKQeQ9K2KLQc4xcOFss3DT4CwJA=; b=lZeDok+a1tyCy2sEJR613UtwO1BH3T3dZ5FX2025FfpTB3F/8aMYGIRzHGMQOVGB4d o1cZLQdFWhiFUkPZRd2u9kORE5CfeIR9izegEdKbttrbOPQXQ5d1WxIi0Naeip/YyKDm P0SVGFf53QZo5DrMLBm2NcvON+YlipBdqXbTZ8Rf38uwIEAydQRc1K3m9P4UgNE9xi9w Shx3ei/1/KL7iGdpkfJIHb8Pf3mKzkPeD/IzEs+XUwvxkZ8ZDsO23l3nIkv5yiulhKtT X9Cdr69YDVviNy4En/r2B1Isj0P3XOT0rCgfAN5ZEMnznHFXd0EVlaGhHAtBCv/Bm+mY 9LVg== X-Gm-Message-State: AKwxytf7zHtm5E6eYklY3WRbK9niguAlV+JTf5wwQKwLiUnXU1bNrtie fO7wesduxE5ibPb+44HoH6Y6EmN9ffU= X-Google-Smtp-Source: AH8x227YWEn3bExT0KJ0nUJY8HVLiq4KYWHXEtizPMpFJbP3tAlLiTluKzXi+5vEl3mPaAj2Jqpxgw== X-Received: by 10.223.136.24 with SMTP id d24mr5617939wrd.203.1516795038548; Wed, 24 Jan 2018 03:57:18 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 24 Jan 2018 11:57:11 +0000 Message-Id: <20180124115711.18797-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH v2] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The ASM1061 SATA controller integrated into the DeveloperBox board emits too much electromagnetic radiation, so it needs spread spectrum mode enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- v2: - rename AsmediaXXX.c to Pci.c - rename RegisterAsm1184Notifier() to RegisterPciIoNotifier() and make its invocation unconditional (rather than only if PCI domain #0 is not limited to Gen1 speed) - use switch() rather than if() in PID/VID check Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c =3D> Pci.c}= | 87 +++++++++++++++----- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c |= 18 ++-- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h |= 5 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf |= 2 +- 4 files changed, 80 insertions(+), 32 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c similarity index 63% rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index c4cbacd3dff9..7ac96ab22b7a 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -15,9 +15,12 @@ #include "PlatformDxe.h" =20 #define ASMEDIA_VID 0x1b21 +#define ASM1061_PID 0x0612 #define ASM1182E_PID 0x1182 #define ASM1184E_PID 0x1184 =20 +#define ASM1061_SSC_OFFSET 0xA10 + #define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 #define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSE= T + \ OFFSET_OF (PCI_CAPABILITY_PCI= EXP, \ @@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort ( IN EFI_PCI_IO_PROTOCOL *PciIo ) { - UINT16 PciVidPid[2]; EFI_STATUS Status; PCIE_CAP Cap; PCI_REG_PCIE_LINK_CONTROL LinkControl; =20 - Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OF= FSET, - ARRAY_SIZE (PciVidPid), &PciVidPid); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", - __FUNCTION__, Status)); - return; - } - - if (PciVidPid[0] !=3D ASMEDIA_VID || - (PciVidPid[1] !=3D ASM1182E_PID && PciVidPid[1] !=3D ASM1184E_PID)) { - return; - } - // // The upstream and downstream ports share the same PID/VID, so check // the port type. This assumes the PCIe Express capability block lives @@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort ( =20 STATIC VOID +EnableAsm1061SpreadSpectrum ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + EFI_STATUS Status; + UINT8 SscVal; + + DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n", + __FUNCTION__)); + + // SSC mode 0~-4000 ppm, 1:1 modulation + + SscVal =3D 0; + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFS= ET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); + + MemoryFence (); + gBS->Stall (1); // delay at least 100 ns between writes of the same regi= ster + + SscVal =3D 1; + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFS= ET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID EFIAPI OnPciIoProtocolNotify ( IN EFI_EVENT Event, @@ -101,6 +118,7 @@ OnPciIoProtocolNotify ( EFI_STATUS Status; EFI_HANDLE HandleBuffer; UINTN BufferSize; + UINT16 PciVidPid[2]; =20 while (TRUE) { BufferSize =3D sizeof (EFI_HANDLE); @@ -114,18 +132,45 @@ OnPciIoProtocolNotify ( (VOID **)&PciIo); ASSERT_EFI_ERROR (Status); =20 - // - // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its - // 2-port sibling of which samples were used in development) needs a - // little nudge to get it to train the downstream links at Gen2 speed. - // - RetrainAsm1184eDownstreamPort (PciIo); + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_= OFFSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n= ", + __FUNCTION__, Status)); + continue; + } + + if (PciVidPid[0] !=3D ASMEDIA_VID) { + continue; + } + + switch (PciVidPid[1]) { + case ASM1061_PID: + // + // The ASM1061 SATA controller as integrated into the DeveloperBox d= esign + // emits too much electromagnetic radiation. So enable spread spectr= um + // mode. + // + EnableAsm1061SpreadSpectrum (PciIo); + break; + case ASM1182E_PID: + case ASM1184E_PID: + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 spee= d. + // + if (mHiiSettings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1) { + RetrainAsm1184eDownstreamPort (PciIo); + } + break; + } } } =20 EFI_STATUS EFIAPI -RegisterAsm1184Notifier ( +RegisterPciIoNotifier ( VOID ) { diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 11b31e77bd3f..f3b05fc973ed 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -14,6 +14,9 @@ =20 #include "PlatformDxe.h" =20 +UINT64 mHiiSettingsVal; +SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + typedef struct { VENDOR_DEVICE_PATH VendorDevicePath; EFI_DEVICE_PATH_PROTOCOL End; @@ -253,8 +256,9 @@ PlatformDxeEntryPoint ( VOID *Dtb; UINTN DtbSize; EFI_HANDLE Handle; - UINT64 SettingsVal; - SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; + + mHiiSettingsVal =3D PcdGet64 (PcdPlatformSettings); + mHiiSettings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; =20 Dtb =3D NULL; Status =3D DtPlatformLoadDtb (&Dtb, &DtbSize); @@ -294,17 +298,13 @@ PlatformDxeEntryPoint ( =20 SmmuEnableCoherentDma (); =20 - SettingsVal =3D PcdGet64 (PcdPlatformSettings); - Settings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->Pcie0MaxSpeed !=3D PCIE_MAX_SPEED_GEN1) { - Status =3D RegisterAsm1184Notifier (); - ASSERT_EFI_ERROR (Status); - } + Status =3D RegisterPciIoNotifier (); + ASSERT_EFI_ERROR (Status); =20 Status =3D EnableSettingsForm (); ASSERT_EFI_ERROR (Status); =20 - if (Settings->EnableEmmc =3D=3D EMMC_ENABLED) { + if (mHiiSettings->EnableEmmc =3D=3D EMMC_ENABLED) { Status =3D RegisterEmmc (); ASSERT_EFI_ERROR (Status); } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index de7de12cec97..b634e8be99ad 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -40,9 +40,12 @@ extern UINT8 PlatformDxeHiiBin[]; extern UINT8 PlatformDxeStrings[]; =20 +extern UINT64 mHiiSettingsVal; +extern SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + EFI_STATUS EFIAPI -RegisterAsm1184Notifier ( +RegisterPciIoNotifier ( VOID ); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 16412b999a40..e13e16f3da6b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,8 +23,8 @@ [Defines] ENTRY_POINT =3D PlatformDxeEntryPoint =20 [Sources] - Asmedia118x.c Emmc.c + Pci.c PlatformDxe.c PlatformDxeHii.uni PlatformDxeHii.vfr --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel