From nobody Sun Apr 28 22:02:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128013821399.1615895138227; Fri, 1 Dec 2017 03:33:33 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 820B320352AA4; Fri, 1 Dec 2017 03:29:06 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 594B420352A8A for ; Fri, 1 Dec 2017 03:29:05 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id i11so2817442wmf.4 for ; Fri, 01 Dec 2017 03:33:31 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id n12sm8150716wrn.76.2017.12.01.03.33.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:29 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/8thc3ISCxTyVq3WuXjn8w71t+kmJolI5J7oMHVwNoM=; b=ZGr+sUZbOhWCFbLTk1hEQbcoP2bSBgI5t7KnO6us0F/T0WBAqrHQVADOpBBbb0h5TV EDlQ9DRgp/bo904yaKdgAajLn4E+uCpRNurIGcGVdJWMe+E/8Ssie0S++N8Zb3Ah11sn LMDZfEWNYciAoUK+j0ixLJBwcUy99PGf5nvZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/8thc3ISCxTyVq3WuXjn8w71t+kmJolI5J7oMHVwNoM=; b=Ds8rmXrRvxiU2i8XZtYi43xI83AhLx61VGVwnfBgaqQXk3aTUHyt+wC1LzLKjaXJ0H 8aHM4677A2O3m3lOprdDICHlq0uEPjW1wNOBHFFk17dy5OnJKz+f/aoaKPRBdd0h8NJz bAec9cq2Mi3aY9TeAopjL6YAB8NAg9KUU/lEpHTlNGF9q7p+YQ4ZSWIXMnEpq7cNtkSL 24xZpl3K4Ozpi8B6RcFaK5sHsyCj9dxre0SPSx2hgmSVDS/oODd9omDVIyuwdeK384IU gpWipLvEqjqRIRXvOgcYIxAu6FMZR9G79xMQYJU5S2tt2FkH4VwYRLeL+nKrCg/wq5qN cNDg== X-Gm-Message-State: AKGB3mJjYElOPhszI9+aPnI4g97xGTUZP4kGezYT2nj7lAjPswzMKFEm HTm+6wyuO2oEk59yfLYIULb8RgPHChw= X-Google-Smtp-Source: AGs4zMYLFBIcCoQBAMLszNMtOYIH/tPXA83xzC0LpRTM1GVcVPuMvMa4rzvgJ0+apPkZGmgKgCYMFw== X-Received: by 10.28.126.201 with SMTP id z192mr1016655wmc.121.1512128010043; Fri, 01 Dec 2017 03:33:30 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:33:17 +0000 Message-Id: <20171201113321.23642-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113321.23642-1-ard.biesheuvel@linaro.org> References: <20171201113321.23642-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/5] Platform/ARM: add VExpressPkg .dec file base on EDK2's ArmPlatformPkg.dec X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In preparation of moving the VExpress specific LCD glue libraries into edk2-platforms, create a new package file for VExpress and clone some of the LCD related PCDs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | 34 ++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec b/Platform/ARM/VEx= pressPkg/ArmVExpressPkg.dec new file mode 100644 index 000000000000..e0826befd36b --- /dev/null +++ b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec @@ -0,0 +1,34 @@ +#/** @file +# Arm Versatile Express package. +# +# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x0001001B + PACKAGE_NAME =3D VExpressPkg + PACKAGE_GUID =3D 75e9d922-0e01-411c-8182-92c52fd79402 + PACKAGE_VERSION =3D 0.1 + +[Guids.common] + gVExpressTokenSpaceGuid =3D { 0xc0778830, 0x8999, 0x4eee, { 0x84, 0x= df, 0x93, 0x93, 0x6f, 0xbc, 0x0a, 0xad } } + +[PcdsFixedAtBuild.common] + # + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # + # For a list of mode numbers look in LcdArmVExpress.c + # + gVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000001 + gVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000002 + gVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000003 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 22:02:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128017027812.5707063772121; Fri, 1 Dec 2017 03:33:37 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BB77D20352AA3; Fri, 1 Dec 2017 03:29:09 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0476020352A8A for ; Fri, 1 Dec 2017 03:29:07 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id r78so2947006wme.5 for ; Fri, 01 Dec 2017 03:33:34 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id n12sm8150716wrn.76.2017.12.01.03.33.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:31 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oYh/zfjnXYSUyUsBblGWfeNPYRzKybBNZV+evu9MOeI=; b=j3A+WWQK2XU6ivW5liT9RgTBEnKfxeqO78kYo+5ZDM0UikhF986gQ6awqaP5hIdBac dgZK6VlYbZ0yKG5fyR2sywtANNGKHPiBH02D2VWgnv7x8QQp+V9WFPvu/MIGqRU6oCx2 1RZ023FxGQTi8MkKh8daOA7OSQs8qEI2ZTORk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oYh/zfjnXYSUyUsBblGWfeNPYRzKybBNZV+evu9MOeI=; b=YmU7hi20rN6y7AkRfxD7yglMC/H01qV9RcRp7OqK5gh9oE29c3GsXZmLRWsUHz0prb vWokm1IZvvrfoR59ms0Xty4sHX7q4vUulJwUyx9YpGrfhHQa3YE+fJpC+SbSQRxLW27Q IvsdW7pK+IrGstOESoazq8LtiWcxWkFH60wd/692lqc7jCgLqcGIg94qD4dHyL+aQApJ bIHII/jC57Apxls9pbRJXfIP7OV/sLeYdLNkG/mK7MkXBUaCj5LFIak4rMq7nHkvKyMX CL6GvM3szb8yd+9M82z/BloAbBIVpu0mX8jY8nKAG7QeftmecbobUrehJgwGa/z6EuBr HoGQ== X-Gm-Message-State: AKGB3mL703ozOGH/esC+P+OyWZqKZDL2FBXPRDQpRaR0C3IUsghxscsM xI4XWRhAOihxyW8vGr6ECpt9fK07Oro= X-Google-Smtp-Source: AGs4zMZTksUpGVqXjoQFN2NWSgpT3odyeoG4gKFpYxQ6hmAnPcuNhTdacbwY+bO3chgFjOesw9k5qA== X-Received: by 10.28.214.145 with SMTP id n139mr1067153wmg.59.1512128012549; Fri, 01 Dec 2017 03:33:32 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:33:18 +0000 Message-Id: <20171201113321.23642-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113321.23642-1-ard.biesheuvel@linaro.org> References: <20171201113321.23642-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/5] Platform/ARM: import PL111 glue library for VExpress X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Create a new LcdPlatformLib implementation for PL111 on VExpress, based on the existing code that lives in ArmPlatformPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c = | 370 ++++++++++++++++++++ Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf= | 44 +++ 2 files changed, 414 insertions(+) diff --git a/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVEx= press.c b/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVExpre= ss.c new file mode 100644 index 000000000000..3f3ceb3d2fa8 --- /dev/null +++ b/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -0,0 +1,370 @@ +/** @file + + Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +typedef struct { + UINT32 Mode; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + LCD_BPP Bpp; + UINT32 OscFreq; + + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; +} LCD_RESOLUTION; + + +LCD_RESOLUTION mResolutions[] =3D { + { // Mode 0 : VGA : 640 x 480 x 24 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 1 : SVGA : 800 x 600 x 24 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 2 : XGA : 1024 x 768 x 24 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + }, + { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + }, + { // Mode 5 : HD : 1920 x 1080 x 24 bpp + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + }, + { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 9 : VGA : 640 x 480 x 15 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 10 : SVGA : 800 x 600 x 15 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 11 : XGA : 1024 x 768 x 15 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + } +}; + +EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { + 0, + NULL +}; + +EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { + 0, + NULL +}; + + +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); + if (!EFI_ERROR(Status)) { + // Install the EDID Protocols + Status =3D gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, &mEdidActive, + NULL + ); + } + + return Status; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // Is it on the motherboard or on the daughterboard? + switch(PL111_CLCD_SITE) { + + case ARM_VE_MOTHERBOARD_SITE: + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; + *VramSize =3D LCD_VRAM_SIZE; + break; + + case ARM_VE_DAUGHTERBOARD_1_SITE: + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; + *VramSize =3D LCD_VRAM_SIZE; + + // Allocate the VRAM from the DRAM so that nobody else uses it. + Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. + Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); + return Status; + } + break; + + default: + // Unsupported site + Status =3D EFI_UNSUPPORTED; + break; + } + + return Status; +} + +UINT32 +LcdPlatformGetMaxMode ( + VOID + ) +{ + // The following line will report correctly the total number of graphics= modes + // supported by the PL111CLCD. + //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + + // However, on some platforms it is desirable to ignore some graphics mo= des. + // This could be because the specific implementation of PL111 has certai= n limitations. + + // Set the maximum mode allowed + return (PcdGet32(PcdPL111LcdMaxMode)); +} + +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 LcdSite; + UINT32 OscillatorId; + SYS_CONFIG_FUNCTION Function; + UINT32 SysId; + + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + LcdSite =3D PL111_CLCD_SITE; + + switch(LcdSite) { + case ARM_VE_MOTHERBOARD_SITE: + Function =3D SYS_CFG_OSC; + OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; + break; + case ARM_VE_DAUGHTERBOARD_1_SITE: + Function =3D SYS_CFG_OSC_SITE1; + OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); + break; + default: + return EFI_UNSUPPORTED; + } + + // Set the video mode oscillator + Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // The FVP foundation model does not have an LCD. + // On the FVP models the GIC variant in encoded in bits [15:12]. + // Note: The DVI Mode is not modelled by RTSM or FVP models. + SysId =3D MmioRead32 (ARM_VE_SYS_ID_REG); + if (SysId !=3D ARM_RTSM_SYS_ID) { + // Take out the FVP GIC variant to reduce the permutations. + SysId &=3D ~ARM_FVP_SYS_ID_VARIANT_MASK; + if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { + // Set the DVI into the new mode + Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + } + } + + // Set the multiplexer + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} + +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + Info->Version =3D 0; + Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; + Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; + Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + + switch (mResolutions[ModeNumber].Bpp) { + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; + + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT(FALSE); + break; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT UINT32* HRes, + OUT UINT32* HSync, + OUT UINT32* HBackPorch, + OUT UINT32* HFrontPorch, + OUT UINT32* VRes, + OUT UINT32* VSync, + OUT UINT32* VBackPorch, + OUT UINT32* VFrontPorch + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *HRes =3D mResolutions[ModeNumber].HorizontalResolution; + *HSync =3D mResolutions[ModeNumber].HSync; + *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; + *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; + *VRes =3D mResolutions[ModeNumber].VerticalResolution; + *VSync =3D mResolutions[ModeNumber].VSync; + *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; + *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D mResolutions[ModeNumber].Bpp; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVEx= pressLib.inf b/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmV= ExpressLib.inf new file mode 100644 index 000000000000..14b63d3c2cc3 --- /dev/null +++ b/Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdArmVExpressLi= b.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Component description file for ArmVeGraphicsDxe module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PL111LcdArmVExpressLib + FILE_GUID =3D 5c60eef8-3c2a-45c0-823a-e0e06ca3c537 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + PL111LcdArmVExpress.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib + +[Protocols] + gEfiEdidDiscoveredProtocolGuid # PRODUCES + gEfiEdidActiveProtocolGuid # PRODUCES + +[Pcd] + gVExpressTokenSpaceGuid.PcdPL111LcdMaxMode + gVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 22:02:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128019480307.8399299679277; Fri, 1 Dec 2017 03:33:39 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 02CA820352AA2; Fri, 1 Dec 2017 03:29:12 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4B8E820352A8A for ; Fri, 1 Dec 2017 03:29:10 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id n138so2956051wmg.2 for ; Fri, 01 Dec 2017 03:33:36 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id n12sm8150716wrn.76.2017.12.01.03.33.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:34 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DPfAA6a+RtBFsvYkDzq5f4wUxFHcb4/YWS+XjcTht1c=; b=VFF9e8kDaHDvwaaOBpRCTQZKia1dRmYrIqq+CEwPTFXJLn4at6yxPmoRBZ/oNY9eK8 iYNJGaVZu5vKNr0HsymP9qMW6ftHYQpWWj7rGdsJ6tqOn3x+ACUydZZsZY1NVOcDJHGq jbNjD+b+ElfPS8J6e8QlpWWKKA9iFxL5WYntk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DPfAA6a+RtBFsvYkDzq5f4wUxFHcb4/YWS+XjcTht1c=; b=qy1WDfXuBkenvVyYOy2/QkB1bBzOxoxPvVIh2lOrit3/Ts6U2718XEljI1lpl7zJUn LVCVVQLTULvYpM8uyHX+t+rUb2AC2HIqrc5Edw9ZdPU2ITYLJdH5Fu5dy4jLBcSafbWk /6isc7+NK7udPo0sm0Psg/I56ofNCKH4EzbNz1rvc94649Mkq5Wr0RHO90k0kFOKTeaA J6ot4lBrtyw33nMYv3HcbW5iChrBpZ4HtDCuvY4v4CF5m9PaYmypKRLSoC9zac9Ds/JX MZKnJ8yWzf6hR7Ss4l5uu8OpPKYVYWBaDIMQMjSAwWg6/beX4wzZZv10DgCTwmfVElSu hMwg== X-Gm-Message-State: AKGB3mK0crMgLMGdGx7zsbaSAfDpehee14QE4kIzJi1nNy3m+IY/e4JO WWp1lDPzkNCqS0g2ewTOW5ASTDz/Pp4= X-Google-Smtp-Source: AGs4zMb7fkiPCMht2elVe+Lr3DrNmX3n/sWXSD3wYJbr5FFnAPPtyLk7EdjRbIAuBRGQgr6PLdOqsw== X-Received: by 10.28.127.197 with SMTP id a188mr955630wmd.138.1512128014929; Fri, 01 Dec 2017 03:33:34 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:33:19 +0000 Message-Id: <20171201113321.23642-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113321.23642-1-ard.biesheuvel@linaro.org> References: <20171201113321.23642-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/5] Platform/ARM: import HcdLcd glue library for VExpress X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Create a new LcdPlatformLib implementation for HdLcd on VExpress, based on the existing code that lives in ArmPlatformPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 285 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 43 +++ 2 files changed, 328 insertions(+) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c new file mode 100644 index 000000000000..b1106ee19b98 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -0,0 +1,285 @@ +/** + + Copyright (c) 2012, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +typedef struct { + UINT32 Mode; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + LCD_BPP Bpp; + UINT32 OscFreq; + + // These are used by HDLCD + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; +} LCD_RESOLUTION; + + +LCD_RESOLUTION mResolutions[] =3D { + { // Mode 0 : VGA : 640 x 480 x 24 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 1 : SVGA : 800 x 600 x 24 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 2 : XGA : 1024 x 768 x 24 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + }, + { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + }, + { // Mode 5 : HD : 1920 x 1080 x 24 bpp + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + } +}; + +EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { + 0, + NULL +}; + +EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { + 0, + NULL +}; + +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); + if (EFI_ERROR(Status)) { + return Status; + } + + // Install the EDID Protocols + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, &mEdidActive, + NULL + ); + + return Status; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + EFI_ALLOCATE_TYPE AllocationType; + + // Set the vram size + *VramSize =3D LCD_VRAM_SIZE; + + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; + + // Allocate the VRAM from the DRAM so that nobody else uses it. + if (*VramBaseAddress =3D=3D 0) { + AllocationType =3D AllocateAnyPages; + } else { + AllocationType =3D AllocateAddress; + } + Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. + Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + return Status; + } + + return EFI_SUCCESS; +} + +UINT32 +LcdPlatformGetMaxMode ( + VOID + ) +{ + // + // The following line will report correctly the total number of graphics= modes + // that could be supported by the graphics driver: + // + return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); +} + +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + // Set the video mode oscillator + do { + Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); + } while (Status =3D=3D EFI_TIMEOUT); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Set the DVI into the new mode + do { + Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); + } while (Status =3D=3D EFI_TIMEOUT); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Set the multiplexer + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} + +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + Info->Version =3D 0; + Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; + Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; + Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + + switch (mResolutions[ModeNumber].Bpp) { + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; + + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT(FALSE); + break; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT UINT32* HRes, + OUT UINT32* HSync, + OUT UINT32* HBackPorch, + OUT UINT32* HFrontPorch, + OUT UINT32* VRes, + OUT UINT32* VSync, + OUT UINT32* VBackPorch, + OUT UINT32* VFrontPorch + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *HRes =3D mResolutions[ModeNumber].HorizontalResolution; + *HSync =3D mResolutions[ModeNumber].HSync; + *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; + *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; + *VRes =3D mResolutions[ModeNumber].VerticalResolution; + *VSync =3D mResolutions[ModeNumber].VSync; + *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; + *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D mResolutions[ModeNumber].Bpp; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf new file mode 100644 index 000000000000..c4c5adda896c --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -0,0 +1,43 @@ +#/** @file +# +# Component description file for HdLcdArmVExpress library +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D HdLcdArmVExpress + FILE_GUID =3D 56875b13-d4fc-4f20-8fe9-fc53762e299d + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + HdLcdArmVExpress.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib + +[Protocols] + gEfiEdidDiscoveredProtocolGuid # PRODUCES + gEfiEdidActiveProtocolGuid # PRODUCES + +[Pcd] + gVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 22:02:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128022647221.4964983755799; Fri, 1 Dec 2017 03:33:42 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3E47C20352AAC; Fri, 1 Dec 2017 03:29:13 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F5DE20352A8A for ; Fri, 1 Dec 2017 03:29:12 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id f9so2867463wmh.0 for ; Fri, 01 Dec 2017 03:33:38 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id n12sm8150716wrn.76.2017.12.01.03.33.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:36 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zs7n96PBv671TjVdR4m7qog/qLDDDhuyoNUWBKW0YqA=; b=PWyVe9e4xrV2eYjks2PFVpKe7SzRttnCOez8GMsq1Y/WsS+oVvvyBApbnAghmUMlPY lO6taQiBTVZraPST3jXp0nU2z35XFZ+LGwpV8i0bPr/Vvcd3nVrv1t+mFq4wucH0KwdK jazNBiVM3x9ITUuV9R1Vke9fe41sTm4NJdlbM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zs7n96PBv671TjVdR4m7qog/qLDDDhuyoNUWBKW0YqA=; b=B2dQreYNcegIhcxhXhRtt1Qw3p3dqVQ4+jA23NJsWnT9sRQJKDQNvCz9EjWEfU7DKc 6DB0cRxDrpuH5x3Yign8OUY8N8Bwt1RcOM7M9WHFyavStCzaLw3WKZ4g5ovmZSt26G+d kL8n9crMBWyxwxTWISNWMUO8r90DcxQ3/CS4sypSJkXYU9zREb+y2lyYY3jvbBytJLC8 3lnnb1gZZcjXMR5Z3AqoF2D8v4YyJc8Q67TB4TGevCLHdsLSndq0JMV5rrsx6mkaFtyV scIa+ogZqk+SfN8hHlXfHxwuo0hsBHeouO5KkbRy9WHey8KPDP04xL1uOmLsggXhABLe 2rzg== X-Gm-Message-State: AKGB3mK1ulshRIzi1lBfjRTatogHGbuFjw+yfLt8PU68QDrpGvFqvZQX o2ThmhGovg0rCA86Bv+VNsvMldWO51w= X-Google-Smtp-Source: AGs4zMb2sohKt5RJCiWbOVLazYLFqATM8VRdMCCwMm3QevacjYKk5eVzNQdgKHes6jh/ZUiNrl1nSg== X-Received: by 10.28.13.145 with SMTP id 139mr1005862wmn.24.1512128017162; Fri, 01 Dec 2017 03:33:37 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:33:20 +0000 Message-Id: <20171201113321.23642-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113321.23642-1-ard.biesheuvel@linaro.org> References: <20171201113321.23642-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/5] Platform/ARM: move FVP to the new LcdGraphicsOutputDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Update the FVP .dsc and .fdf files to switch over to the refactored LCD graphics output driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 5 +++-- Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 2 +- Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 5 +---- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platfor= m/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc index a04159bb9741..8b20371e1e15 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc +++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -47,7 +47,8 @@ [LibraryClasses.common] ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVEx= pressLib/NorFlashArmVExpressLib.inf !ifdef EDK2_ENABLE_PL111 - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf + LcdHwLib|ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf + LcdPlatformLib|Platform/ARM/VExpressPkg/PL111LcdArmVExpressLib/PL111LcdA= rmVExpressLib.inf !endif =20 # Virtio Support @@ -273,7 +274,7 @@ [Components.common] ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf !ifdef EDK2_ENABLE_PL111 - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf !endif ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf =20 diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf b/Platfor= m/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf index 1084eda3d367..d95b66073978 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf +++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -114,7 +114,7 @@ [FV.FvMain] INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf !ifdef EDK2_ENABLE_PL111 - INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDx= e.inf + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf !endif INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf =20 diff --git a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc b/Platform/ARM/VE= xpressPkg/ArmVExpress.dsc.inc index 1d6cd79333ef..93a2451dafd6 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +++ b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc @@ -82,10 +82,7 @@ [LibraryClasses.common] ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVEx= pressLib/NorFlashArmVExpressLib.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf -!ifdef EDK2_ENABLE_PL111 - # ARM PL111 Lcd Driver - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf -!endif + # ARM PL031 RTC Driver RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealT= imeClockLib.inf TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 22:02:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128025102749.5110846627138; Fri, 1 Dec 2017 03:33:45 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7755220352AAF; Fri, 1 Dec 2017 03:29:15 -0800 (PST) Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 590C520352A8A for ; Fri, 1 Dec 2017 03:29:14 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id z34so9755382wrz.10 for ; Fri, 01 Dec 2017 03:33:40 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id n12sm8150716wrn.76.2017.12.01.03.33.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:38 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KL8QPuN7gdRl0EH0FeTbv7YCzruSiP5yaM36AavI9qA=; b=cjua8+3Q8X5OLFfUPcjkgXbe4HvL4dVbH1fUysSkHSjB/WgEnyRGup9jh1oQtYKhf7 oknQEIJPbFJhm3uOxe8XmpLX9HzsOz3bCaY+QzBwnD09gSAoQsVyecgZ910j4mOcZ87S j7HIVQ1KHUF5aPfQZi+0kU0KHtTlFD1wOWDFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KL8QPuN7gdRl0EH0FeTbv7YCzruSiP5yaM36AavI9qA=; b=IYIqlu/JowLupXXz/tNXdLj1BqaplXlZIVt7hSSCRHwfE1Ve6Daq863XHM/5P5g1gq 6vIwa2rJ4H3Oq+qGI1pEbDWCqaUCuTN3M+cuLht1e9fo8qHdk3jKxDQ+ezyZs04DmHLZ z3RA8Zy1AcND31mMPeqprmksgqg93Vje/rZ8jeS279xnq8cVv4vBuBIqIFddDhIBcVus UERIeTUIZIE1nCJjc3YU9NzDNoJE6mNEVhqJ4UKsh0m7v/qJ8HXH/wVvY0XzFeBavgXh B6HqJ0O5XkFs65CO09PwvE5FivinFMBSIYYu3p3o3EIo/GkTgYc2s+klDClr4HAGXQW2 B0Kw== X-Gm-Message-State: AJaThX61DIroWKOlqwt21oW4uEOmpKtgBBn588Yul3K2RAcFOzQEN9ym eOnwmPALyAx4nYJrAa29s6PQEjL8w3M= X-Google-Smtp-Source: AGs4zMbtqN0IllA60KVqP3OGvQHl7+qi6X3jTY5+L3MBuE00rDGChq9gQ7+N34i+WAkwzIsI3MBpaA== X-Received: by 10.223.188.141 with SMTP id g13mr5149353wrh.169.1512128019086; Fri, 01 Dec 2017 03:33:39 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:33:21 +0000 Message-Id: <20171201113321.23642-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113321.23642-1-ard.biesheuvel@linaro.org> References: <20171201113321.23642-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/5] Platform/ARM: move TC2 to the new LcdGraphicsOutputDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Update the TC2 .dsc and .fdf files to switch over to the refactored LCD graphics output driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 8 ++++---- Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc b/Platform/A= RM/VExpressPkg/ArmVExpress-CTA15-A7.dsc index 98513b282fa7..c7307c741b64 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc +++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc @@ -50,7 +50,8 @@ [LibraryClasses.common] # ARM General Interrupt Driver in Secure and Non-secure ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf =20 - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib= /HdLcdArmVExpressLib.inf + LcdHwLib|ArmPlatformPkg/Library/HdLcd/HdLcd.inf + LcdPlatformLib|Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf =20 ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf =20 @@ -158,7 +159,7 @@ [PcdsFixedAtBuild.common] ## PL111 Lcd & HdLcd gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000 - gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5 + gVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5 !endif =20 # @@ -245,8 +246,7 @@ [Components.common] =20 ArmPkg/Drivers/ArmGic/ArmGicDxe.inf ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf - #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.i= nf - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf =20 diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf b/Platform/A= RM/VExpressPkg/ArmVExpress-CTA15-A7.fdf index 3c75a51570b8..32d04e7c86fe 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf +++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf @@ -97,8 +97,7 @@ [FV.FvMain] INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf - #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputD= xe.inf - INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.i= nf + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf =20 # --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel