From nobody Thu May 2 04:59:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509005266429514.3802951951747; Thu, 26 Oct 2017 01:07:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EBFA02034CF93; Thu, 26 Oct 2017 01:03:58 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F3A52034CF8C for ; Thu, 26 Oct 2017 01:03:58 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2017 01:07:43 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by orsmga005.jf.intel.com with ESMTP; 26 Oct 2017 01:07:42 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,434,1503385200"; d="scan'208";a="165180379" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 26 Oct 2017 16:07:41 +0800 Message-Id: <20171026080741.225120-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 Subject: [edk2] [PATCH] MdePkg/PciExpress21.h: Fix typo in PCI_REG_PCIE_SLOT_CONTROL X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liming Gao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PCI_REG_PCIE_SLOT_CONTROL contains a typo. It is defined as: typedef union { struct { UINT32 AttentionButtonPressed : 1; UINT32 ... ... } Bits; UINT16 Uint16; } PCI_REG_PCIE_SLOT_CONTROL; The bit field data type should be UINT16 instead of UINT32, results sizeof (PCI_REG_PCIE_SLOT_CONTROL) equals to 4 instead of 2. Because this structure is used in PCI_CAPABILITY_PCIEXP as below: typedef struct { ... PCI_REG_PCIE_SLOT_CONTROL SlotControl; PCI_REG_PCIE_SLOT_STATUS SlotStatus; } PCI_CAPABILITY_PCIEXP; It cause the OFFSET_OF (PCI_CAPABILITY_PCIEXP, SlotStatus) equal to a wrong value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Liming Gao Reviewed-by: Liming Gao --- MdePkg/Include/IndustryStandard/PciExpress21.h | 24 ++++++++++++----------= -- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Includ= e/IndustryStandard/PciExpress21.h index ce9c06a7c6..d90b5975ba 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -182,18 +182,18 @@ typedef union { =20 typedef union { struct { - UINT32 AttentionButtonPressed : 1; - UINT32 PowerFaultDetected : 1; - UINT32 MrlSensorChanged : 1; - UINT32 PresenceDetectChanged : 1; - UINT32 CommandCompletedInterrupt : 1; - UINT32 HotPlugInterrupt : 1; - UINT32 AttentionIndicator : 2; - UINT32 PowerIndicator : 2; - UINT32 PowerController : 1; - UINT32 ElectromechanicalInterlock : 1; - UINT32 DataLinkLayerStateChanged : 1; - UINT32 Reserved : 3; + UINT16 AttentionButtonPressed : 1; + UINT16 PowerFaultDetected : 1; + UINT16 MrlSensorChanged : 1; + UINT16 PresenceDetectChanged : 1; + UINT16 CommandCompletedInterrupt : 1; + UINT16 HotPlugInterrupt : 1; + UINT16 AttentionIndicator : 2; + UINT16 PowerIndicator : 2; + UINT16 PowerController : 1; + UINT16 ElectromechanicalInterlock : 1; + UINT16 DataLinkLayerStateChanged : 1; + UINT16 Reserved : 3; } Bits; UINT16 Uint16; } PCI_REG_PCIE_SLOT_CONTROL; --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel