From nobody Sat May 4 22:10:52 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1503647010710592.9624554128593; Fri, 25 Aug 2017 00:43:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 376EF21D1E2C9; Fri, 25 Aug 2017 00:40:53 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 752F921D1E2C6 for ; Fri, 25 Aug 2017 00:40:51 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Aug 2017 00:43:27 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.2]) by fmsmga002.fm.intel.com with ESMTP; 25 Aug 2017 00:43:25 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,424,1498546800"; d="scan'208";a="1210289588" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Fri, 25 Aug 2017 15:43:23 +0800 Message-Id: <20170825074323.390468-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 Subject: [edk2] [PATCH] MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Michael D Kinney , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ruiyu Ni The patch dynamically enables Bus Master on P2P bridges only when requested by a device driver through PciIo.Attribute() to enable the Bus Master. Signed-off-by: Sean Brogan Signed-off-by: Ruiyu Ni Cc: Jiewen Yao Cc: Michael D Kinney Reviewed-by: Jiewen.yao@intel.com --- MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 16 +++++++++++++--- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 18 +++++++++++++++= --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++---- 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index c0227fa2b6..359b9ded6d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -1,7 +1,7 @@ /** @file Supporting functions implementaion for PCI devices management. =20 -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -711,7 +711,12 @@ StartPciDevicesOnBridge ( 0, &Supports ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; + // + // By default every bridge's IO and MMIO spaces are enabled. + // Bridge's Bus Master will be enabled when any device behind it r= equests + // to enable Bus Master. + // + Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRI= BUTE_MEMORY); PciIoDevice->PciIo.Attributes ( &(PciIoDevice->PciIo), EfiPciIoAttributeOperationEnable, @@ -763,7 +768,12 @@ StartPciDevicesOnBridge ( 0, &Supports ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; + // + // By default every bridge's IO and MMIO spaces are enabled. + // Bridge's Bus Master will be enabled when any device behind it r= equests + // to enable Bus Master. + // + Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRI= BUTE_MEMORY); PciIoDevice->PciIo.Attributes ( &(PciIoDevice->PciIo), EfiPciIoAttributeOperationEnable, diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 81171c82d9..f73756a31e 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1218,11 +1218,12 @@ DetermineDeviceAttribute ( return Status; } // - // Assume the PCI Root Bridge supports DAC + // Assume the PCI Root Bridge supports DAC and Bus Master. // PciIoDevice->Supports |=3D (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVI= CE | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | + EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); =20 } else { =20 @@ -1233,9 +1234,16 @@ DetermineDeviceAttribute ( // Command =3D EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_MEMORY_SPACE | - EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP; =20 + // + // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus M= aster capable. + // So only test the Bus Master capability for PCI devices. + // + if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) { + Command |=3D EFI_PCI_COMMAND_BUS_MASTER; + } + BridgeControl =3D EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_= VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16; =20 // @@ -1245,7 +1253,11 @@ DetermineDeviceAttribute ( =20 // // Set the supported attributes for specified PCI device + // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus M= aster capable. // + if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) { + Command |=3D EFI_PCI_COMMAND_BUS_MASTER; + } PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SU= PPORTS); =20 // diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/= PciBusDxe/PciIo.c index cc7125e4fc..659f480d71 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1348,7 +1348,8 @@ ModifyRootBridgeAttributes ( // Attributes &=3D ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | + EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); =20 // // Record the new attribute of the Root Bridge @@ -1726,12 +1727,11 @@ PciIoAttributes ( } // // The upstream bridge should be also set to revelant attribute - // expect for IO, Mem and BusMaster + // expect for IO and Mem // UpStreamAttributes =3D Attributes & (~(EFI_PCI_IO_ATTRIBUTE_IO | - EFI_PCI_IO_ATTRIBUTE_MEMORY | - EFI_PCI_IO_ATTRIBUTE_BUS_MASTER + EFI_PCI_IO_ATTRIBUTE_MEMORY ) ); UpStreamBridge =3D PciIoDevice->Parent; --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel