From nobody Fri May 3 05:24:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1494322455942985.8526691105235; Tue, 9 May 2017 02:34:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0884421A0BABF; Tue, 9 May 2017 02:34:14 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9262921A13493 for ; Tue, 9 May 2017 02:34:12 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP; 09 May 2017 02:34:12 -0700 Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.198.95]) by orsmga005.jf.intel.com with ESMTP; 09 May 2017 02:34:11 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,313,1491289200"; d="scan'208";a="97503552" From: zwei4 To: edk2-devel@lists.01.org Date: Tue, 9 May 2017 17:34:06 +0800 Message-Id: <20170509093406.22780-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] Extend IBB region. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- Platform/BroxtonPlatformPkg/BuildBios.bat | 4 ++-- Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc | 2 +- Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 6 +++--- .../ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 1556 -> 1556 b= ytes .../Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPl= atformPkg/BuildBios.bat index b57188d34..80de2f47b 100644 --- a/Platform/BroxtonPlatformPkg/BuildBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBios.bat @@ -410,9 +410,9 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv %Storage_Folder% >= nul =20 if /i "%FSP_WRAPPER%" =3D=3D "TRUE" ( if %Stepping%=3D=3DB ( -:: 0xFEF63000 =3D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase =3D $= (CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EM= P_DATA_SIZE) + $(BLD_IBBM_SIZE) +:: 0xFEF7A000 =3D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase =3D $= (CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EM= P_DATA_SIZE) + $(BLD_IBBM_SIZE) pushd %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPk= g\FspBin - python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f Ap= olloLakeFsp.fd -c m -b 0xFEF63000 -o .\ -n FSP.fd + python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f Ap= olloLakeFsp.fd -c m -b 0xFEF7A000 -o .\ -n FSP.fd python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f FSP= .fd -o .\ -n FSP.Fv popd copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBi= nPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc b/Platform= /BroxtonPlatformPkg/PlatformDsc/Defines.dsc index ff751c164..842acf308 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc @@ -153,7 +153,7 @@ DEFINE FSP_IBBL_SIZE =3D 0x2000 DEFINE BLD_IBBL_SIZE =3D 0x6000 DEFINE FSP_IBBM_SIZE =3D 0x58000 - DEFINE BLD_IBBM_SIZE =3D 0x1E000 + DEFINE BLD_IBBM_SIZE =3D 0x35000 =20 DEFINE CAR_BASE_ADDRESS =3D 0xFEF00000 # @PcdTemporary= RamBase DEFINE BLD_RAM_DATA_SIZE =3D 0x16000 # BOOTLOADER te= mp memory size diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/Broxton= PlatformPkg/PlatformPkg.fdf index 3b4d9e780..7522153a3 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -19,10 +19,10 @@ #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D # 3MB BIOS Layout Definition #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - DEFINE FLASH_BASE =3D 0xFFD00000 #The base address of the 3MB= FLASH Device. - DEFINE FLASH_SIZE =3D 0x00300000 #The flash size in bytes of = the 3MB FLASH Device + DEFINE FLASH_BASE =3D 0xFFCE9000 #The base address of the 3MB= FLASH Device. + DEFINE FLASH_SIZE =3D 0x00317000 #The flash size in bytes of = the 3MB FLASH Device DEFINE FLASH_BLOCK_SIZE =3D 0x1000 #The block size in bytes of = the 3MB FLASH Device. - DEFINE FLASH_NUM_BLOCKS =3D 0x300 #The number of blocks in 3MB= FLASH Device. + DEFINE FLASH_NUM_BLOCKS =3D 0x317 #The number of blocks in 3MB= FLASH Device. !else #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D # 5MB BIOS Layout Definition diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/Reset= Vector.ia32.port80.raw b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vt= f0/Bin/ResetVector.ia32.port80.raw index f1fc0417a921dee98833ff797ea1ea0c4de1e2f5..2cb2466ed5e4b31b371e2f93f47= 2d04ca217933f 100644 GIT binary patch delta 13 UcmbQjGlge@B+~_sjnY3^0UqxJjsO4v delta 13 UcmbQjGlge@BvS(WM(Lld031pL9RL6T diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/Init= NEM.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM= .asm index 28560ab89..12d274676 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm @@ -183,7 +183,7 @@ istruc HobStruc dd 0x00100000 ; .CarSize dd 0xFFF00000 ; .IBBSource =3D Not used dd 0xFEF45000 ; .IBBBase =3D .CarBase - dd 0x00076000 ; .IBBSize =3D size of (FVIBBM.fv+FSP_M.fv) =3D BLD= _IBBM_SIZE + FSP_IBBM_SIZE =3D 0x76000 + dd 0x0008D000 ; .IBBSize =3D size of (FVIBBM.fv+FSP_M.fv) =3D BLD= _IBBM_SIZE + FSP_IBBM_SIZE =3D 0x8D000 dd 0xFFFFF000 ; .IBBLSource =3D 0x100000000 - .IBBLSize =3D PcdFlash= FvIBBLBase dd 0xFEF40000 ; .IBBLBase =3D .IBBBase + .IBBSize dd 0x00001000 ; .IBBLSize =3D PcdFlashFvIBBLSize =3D FLASH_REGION_= FV_IBBL_SIZE in .fdf --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel