From nobody Fri May 3 20:21:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1493187011360377.2200130932398; Tue, 25 Apr 2017 23:10:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 21A0021951C8F; Tue, 25 Apr 2017 23:10:09 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9399121951C86 for ; Tue, 25 Apr 2017 23:10:07 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2017 23:10:07 -0700 Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.198.54]) by FMSMGA003.fm.intel.com with ESMTP; 25 Apr 2017 23:10:06 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,253,1488873600"; d="scan'208";a="849897246" From: zwei4 To: edk2-devel@lists.01.org Date: Wed, 26 Apr 2017 14:09:49 +0800 Message-Id: <20170426060949.29840-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] Add script to build ResetVector. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- Platform/BroxtonPlatformPkg/BuildBios.bat | 6 ++= ++++ Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc | 2 +- .../BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm | 4 ++= -- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPl= atformPkg/BuildBios.bat index a326d3c64..0ebc5705a 100644 --- a/Platform/BroxtonPlatformPkg/BuildBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBios.bat @@ -317,6 +317,12 @@ if ErrorLevel 1 goto BldFail echo Building ResetVector... =20 set ResetVectorPath=3D%WORKSPACE%\%PLATFORM_RC_PACKAGE%\Cpu\ResetVector + +pushd %ResetVectorPath%\Vtf0 + nasm.exe %Nasm_Flags% -o Bin\ResetVector.ia32.port80.raw ResetVectorCode= .asm + python %CORE_PATH%\UefiCpuPkg\ResetVector\Vtf0\Tools\FixupForRawSection.= py Bin\ResetVector.ia32.port80.raw +popd + pushd %ResetVectorPath%\Vtf1 nasm.exe %Nasm_Flags% -o Bin\ResetVector.ia32.port80.raw ResetVectorCode= .asm python %CORE_PATH%\UefiCpuPkg\ResetVector\Vtf0\Tools\FixupForRawSection.= py Bin\ResetVector.ia32.port80.raw diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc b/Platform= /BroxtonPlatformPkg/PlatformDsc/Defines.dsc index e8866a0dc..ff751c164 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc @@ -152,7 +152,7 @@ =20 DEFINE FSP_IBBL_SIZE =3D 0x2000 DEFINE BLD_IBBL_SIZE =3D 0x6000 - DEFINE FSP_IBBM_SIZE =3D 0x56000 + DEFINE FSP_IBBM_SIZE =3D 0x58000 DEFINE BLD_IBBM_SIZE =3D 0x1E000 =20 DEFINE CAR_BASE_ADDRESS =3D 0xFEF00000 # @PcdTemporary= RamBase diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/Init= NEM.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM= .asm index 9fa43fcc3..28560ab89 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm @@ -1,7 +1,7 @@ ;; @file ; Search for the Boot Firmware Volume (BFV) base address. ; -; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
; ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the B= SD License @@ -183,7 +183,7 @@ istruc HobStruc dd 0x00100000 ; .CarSize dd 0xFFF00000 ; .IBBSource =3D Not used dd 0xFEF45000 ; .IBBBase =3D .CarBase - dd 0x00078000 ; .IBBSize =3D PcdFlashFvIBBMSize =3D FLASH_REGION_= FV_IBBM_SIZE in .fdf + dd 0x00076000 ; .IBBSize =3D size of (FVIBBM.fv+FSP_M.fv) =3D BLD= _IBBM_SIZE + FSP_IBBM_SIZE =3D 0x76000 dd 0xFFFFF000 ; .IBBLSource =3D 0x100000000 - .IBBLSize =3D PcdFlash= FvIBBLBase dd 0xFEF40000 ; .IBBLBase =3D .IBBBase + .IBBSize dd 0x00001000 ; .IBBLSize =3D PcdFlashFvIBBLSize =3D FLASH_REGION_= FV_IBBL_SIZE in .fdf --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel