From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491400702285574.4068024882678; Wed, 5 Apr 2017 06:58:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 29BED20080934; Wed, 5 Apr 2017 06:58:21 -0700 (PDT) Received: from mail-wr0-x22d.google.com (mail-wr0-x22d.google.com [IPv6:2a00:1450:400c:c0c::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D8F0620080926 for ; Wed, 5 Apr 2017 06:58:19 -0700 (PDT) Received: by mail-wr0-x22d.google.com with SMTP id w11so14977782wrc.3 for ; Wed, 05 Apr 2017 06:58:19 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id 127sm22522793wmt.20.2017.04.05.06.58.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Apr 2017 06:58:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q6wvd6Aa2TbbfgZ/OnRlLJ39WL+Rm4dG2OFw1b55AZI=; b=MEMX1p036caOo6CzG3qW9uEfxDjZlMeLdLltMxcO4lJ7MbB01GWIHmqZ4tFXFbJrjj 4ddsVS+qmPZCE9C6sNf/d/G/DLcjUybR4oUt+wnXg3kg/spTBK9qzNhVTaJARzUaJ0CH N6hQhYKNHEWorQ1wrZN61PSFL2EolgeAXWrYY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q6wvd6Aa2TbbfgZ/OnRlLJ39WL+Rm4dG2OFw1b55AZI=; b=qPX8Ci2QDrx5oy4der9lmWNCzWyrlLcOiHUVFXb7N0M5gqLOCWxconmQMlUNrkKUip /fnF5FEbMLOJkBVbkF8e/Zf2cbkrWXc7i9x19ZNQHxMpzViXWMYhpgecfkHY+YoCCKvs 7TlpRMQTr+vjN4Lv4lodtIpc7hoG/x6KI74OA0oZo2YVOpmSrBJGsgGDayhovZzMZ+r2 FtCnUMj3VXkU0ms7/7x/+YStPnXDCkAQe+jWOLoXeLNiBeSCrRD/zG2wYHYAvYFaLmUM PLEj0/FbJH1MnyNjTaP7swWgQ6HFRIAR7+K7OOtGIy9zxsH2b4vkFB4q9euRO3H1IBdW NiSA== X-Gm-Message-State: AFeK/H0qVGyki7ROwjjz9GB/lhoIHXNhruqv/0U8ik9PkDCRUCuLO0EAXbOgLghcIvijVqLr X-Received: by 10.223.183.6 with SMTP id l6mr26475883wre.192.1491400697276; Wed, 05 Apr 2017 06:58:17 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Apr 2017 14:58:02 +0100 Message-Id: <20170405135807.28425-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170405135807.28425-1-ard.biesheuvel@linaro.org> References: <20170405135807.28425-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 resend v4 1/6] ArmPlatformPkg/ArmShellCmdRunAxf: remove BdsLib dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Remove ArmShellCmdRunAxf's dependency on the deprecated BdsLib by cloning the ShutdownUefiBootServices() routine into a local source file; this is the only BdsLib feature 'runaxf' depends on. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf | 1 - ArmPlatformPkg/Library/ArmShellCmdRunAxf/RunAxf.c | 58 ++++++= +++++++++++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf= b/ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf index 9a34f666612a..7d15f6934608 100644 --- a/ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf +++ b/ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf @@ -43,7 +43,6 @@ [Packages] [LibraryClasses] ArmLib BaseLib - BdsLib DebugLib HiiLib ShellLib diff --git a/ArmPlatformPkg/Library/ArmShellCmdRunAxf/RunAxf.c b/ArmPlatfor= mPkg/Library/ArmShellCmdRunAxf/RunAxf.c index 2abfb6cc1053..9f4fc780307d 100644 --- a/ArmPlatformPkg/Library/ArmShellCmdRunAxf/RunAxf.c +++ b/ArmPlatformPkg/Library/ArmShellCmdRunAxf/RunAxf.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include =20 @@ -35,6 +34,63 @@ typedef VOID (*ELF_ENTRYPOINT)(UINTN arg0, UINTN arg1, UINTN arg2, UINTN arg3); =20 +STATIC +EFI_STATUS +ShutdownUefiBootServices ( + VOID + ) +{ + EFI_STATUS Status; + UINTN MemoryMapSize; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN MapKey; + UINTN DescriptorSize; + UINT32 DescriptorVersion; + UINTN Pages; + + MemoryMap =3D NULL; + MemoryMapSize =3D 0; + Pages =3D 0; + + do { + Status =3D gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + + Pages =3D EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; + MemoryMap =3D AllocatePages (Pages); + + // + // Get System MemoryMap + // + Status =3D gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + } + + // Don't do anything between the GetMemoryMap() and ExitBootServices() + if (!EFI_ERROR(Status)) { + Status =3D gBS->ExitBootServices (gImageHandle, MapKey); + if (EFI_ERROR(Status)) { + FreePages (MemoryMap, Pages); + MemoryMap =3D NULL; + MemoryMapSize =3D 0; + } + } + } while (EFI_ERROR(Status)); + + return Status; +} + =20 STATIC EFI_STATUS --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491400704592263.83213356184046; Wed, 5 Apr 2017 06:58:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 704452008093A; Wed, 5 Apr 2017 06:58:23 -0700 (PDT) Received: from mail-wr0-x232.google.com (mail-wr0-x232.google.com [IPv6:2a00:1450:400c:c0c::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 934F420080926 for ; Wed, 5 Apr 2017 06:58:21 -0700 (PDT) Received: by mail-wr0-x232.google.com with SMTP id w11so14978968wrc.3 for ; Wed, 05 Apr 2017 06:58:21 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id 127sm22522793wmt.20.2017.04.05.06.58.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Apr 2017 06:58:18 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EsFR66HOdFbrm5OzjHcDYsQFJOU/so6RG++IgEAk2pg=; b=NeQ0ukhbxgXnC2PDPu50P8Ulvgeld5BxK5uPqN7rv00wV6V32LdvzZIPnk8V6cTIy2 pyk9o3xF62j1+F6F0CrCGzvPt/UHFAy4wybmj8+87i4QyFdfuorRi4+tlyv1fEoYaFeC 4L3TdZfYqDhMbUvSY6PhAiElbZVgsPjbJ43/o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EsFR66HOdFbrm5OzjHcDYsQFJOU/so6RG++IgEAk2pg=; b=YcsnuArQ8UhwSS+TEc904c5FuDCV33bySbSIi0w05WVf791frsJqaJnXxrTr1Vj7fS MMNe22xAf59rYMFJvBKAqqwPUgGeYMWBXIcowqpWtvH2uDI0lI/JWm4mF3jrIbAZE+yf vMbIrldL3h53RAptkWBsy5TbbK1SmZRa1OgKasYqypAf6rMD9idXnfUTZku7xskTfNYD aKYM4nZwn0DXr7MnnzlZvyumKpHf6Cspfss0CaU2c6Arzsuub0n7DEyw8IJ3qwQMzwTt eNHrCSRm2B13HBmAr8fxI1YUPxPiVdLVPuclAq623Uk0XSFme6L5XoZ9zhnCmd/w0roQ 84MA== X-Gm-Message-State: AFeK/H0KVmZDsgMH3xktxYThloFG4ZhsQwUgA3OvgRaoSFSbtaUxDwu1DAMM1GJXIyzqyekj X-Received: by 10.223.172.133 with SMTP id o5mr21634025wrc.23.1491400699254; Wed, 05 Apr 2017 06:58:19 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Apr 2017 14:58:03 +0100 Message-Id: <20170405135807.28425-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170405135807.28425-1-ard.biesheuvel@linaro.org> References: <20170405135807.28425-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 resend v4 2/6] ArmPlatformPkg/ArmJunoDxe: remove BdsLib dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The ArmJunoDxe driver does not actually depend on the deprecated BdsLib so remove the dependency declaration from the INF file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf | 1 - 1 file changed, 1 deletion(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/= ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf index a2617982b259..168070c6add4 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf @@ -38,7 +38,6 @@ [LibraryClasses] ArmLib ArmShellCmdRunAxfLib BaseMemoryLib - BdsLib DebugLib DmaLib DxeServicesTableLib --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491400706859124.44405644258393; Wed, 5 Apr 2017 06:58:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AB5B62041FBC3; Wed, 5 Apr 2017 06:58:25 -0700 (PDT) Received: from mail-wr0-x231.google.com (mail-wr0-x231.google.com [IPv6:2a00:1450:400c:c0c::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9571E203BF032 for ; Wed, 5 Apr 2017 06:58:24 -0700 (PDT) Received: by mail-wr0-x231.google.com with SMTP id t20so16191851wra.1 for ; Wed, 05 Apr 2017 06:58:24 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id 127sm22522793wmt.20.2017.04.05.06.58.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Apr 2017 06:58:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2edUcYjeYx2FVRifF8i/zIY4Zx3i8rxps0f4IfcyAiU=; b=UuyZl4N4GyGrWEGmugWYnsgyroBeOcEAfkHht0BO1cmgLQl8L6kk7sBBI/MJstifIw 8j9za6fb8hIslmnBua2EW0BT6Ov1r5nJAoj7mAjJUnUy95u/BC6r8Y24Pa5ZXQezHoCf kvW3AZj9HjYI9P+I4J2AOOumm9AGIz769VfLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2edUcYjeYx2FVRifF8i/zIY4Zx3i8rxps0f4IfcyAiU=; b=HxAqZ7lOuQl0sUGsJj3gocXd/KnyOmwYliIXPQ7sc3o7vF0lR/t7ykvuwSihS4K3H+ ETwMZolg26EI+p4+0NhrCs4s9bHrAzsh6QL37mTBd52ZJgQ1pJKCaX5qnK6n+dIFWuZm m4Vm6Rd+wRxuRC6Q+/NGG5bRIAWeo3TaBeljLHoikocCS80PShvnRhP/FP3dJ/Xl8az1 L+o0xgx9PTSre7wbNSnkwzJV2ItcEfNj1GM8tus0PcYp/ISPO6AzjMWEic7hhmI3JHnN WCXudBj2v4QweQdIe/qX4uzTel7I4oMXPYdxoLAi3GMU4wNm867xmRuNV/G4vJQpoffy Xizw== X-Gm-Message-State: AN3rC/7bzF8oqFb8ofsFuplS/v2rmRGs8+rpSZK6wtJGkgTQsL4qpR+47+jZQv4tiebL3oz9 X-Received: by 10.223.136.165 with SMTP id f34mr1440236wrf.145.1491400702288; Wed, 05 Apr 2017 06:58:22 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Apr 2017 14:58:04 +0100 Message-Id: <20170405135807.28425-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170405135807.28425-1-ard.biesheuvel@linaro.org> References: <20170405135807.28425-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 resend v4 3/6] ArmPlatformPkg/ArmJunoDxe: use the generic non-discoverable device support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Replace the open coded reimplementation of 'PCI emulation' with a pair of calls into NonDiscoverableDeviceRegistrationLib to register the OHCI and EHCI controllers. These will be picked up by the generic driver instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 30 +- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf | 3 +- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h | 5 - ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c | 596 --= ------------------ ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h | 284 --= -------- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c | 299 --= -------- 6 files changed, 27 insertions(+), 1190 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/Ar= mPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c index f13c49559bb4..14ff189a3078 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -447,10 +448,31 @@ ArmJunoEntryPoint ( UINT32 JunoRevision; EFI_EVENT EndOfDxeEvent; =20 - Status =3D PciEmulationEntryPoint (); - if (EFI_ERROR (Status)) { - return Status; - } + // + // Register the OHCI and EHCI controllers as non-coherent + // non-discoverable devices. + // + Status =3D RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeOhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress), + SIZE_64KB + ); + ASSERT_EFI_ERROR (Status); + + Status =3D RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeEhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress), + SIZE_64KB + ); + ASSERT_EFI_ERROR (Status); =20 // // If a hypervisor has been declared then we need to make sure its regio= n is protected at runtime diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/= ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf index 168070c6add4..6719d0adcc87 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf @@ -21,8 +21,6 @@ [Defines] [Sources.common] AcpiTables.c ArmJunoDxe.c - PciEmulation.c - PciRootBridgeIo.c =20 [Packages] ArmPkg/ArmPkg.dec @@ -42,6 +40,7 @@ [LibraryClasses] DmaLib DxeServicesTableLib IoLib + NonDiscoverableDeviceRegistrationLib PcdLib PrintLib SerialPortLib diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInterna= l.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h index df0277067e34..5d2b68fabd12 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h @@ -42,11 +42,6 @@ #define R_TST_CTRL_1 0x0158 /* Test Control Register = 1 */ =20 =20 -EFI_STATUS -PciEmulationEntryPoint ( - VOID - ); - /** * Callback called when ACPI Protocol is installed */ diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c b/= ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c deleted file mode 100644 index 2ddebf606e3d..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c +++ /dev/null @@ -1,596 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include "PciEmulation.h" - -#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44 - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - PCI_DEVICE_PATH PciDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_IO_DEVICE_PATH; - -typedef struct { - UINT32 Signature; - EFI_PCI_IO_DEVICE_PATH DevicePath; - EFI_PCI_IO_PROTOCOL PciIoProtocol; - PCI_TYPE00 *ConfigSpace; - PCI_ROOT_BRIDGE RootBridge; - UINTN Segment; -} EFI_PCI_IO_PRIVATE_DATA; - -#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', = 'o') -#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DA= TA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) - -EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =3D -{ - { - { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } }, - EISA_PNP_ID(0x0A03), // HID - 0 // UID - }, - { - { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } }, - 0, - 0 - }, - { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DE= VICE_PATH_PROTOCOL), 0} } -}; - -STATIC -VOID -ConfigureUSBHost ( - VOID - ) -{ -} - - -EFI_STATUS -PciIoPollMem ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoPollIo ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoMemRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (= This); - - return PciRootBridgeIoMemRead (&Private->RootBridge.Io, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Wi= dth, - Private->ConfigSpace->Device.Bar[BarIndex]= + Offset, //Fix me ConfigSpace - Count, - Buffer - ); -} - -EFI_STATUS -PciIoMemWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (= This); - - return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) W= idth, - Private->ConfigSpace->Device.Bar[BarIndex= ] + Offset, //Fix me ConfigSpace - Count, - Buffer - ); -} - -EFI_STATUS -PciIoIoRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoIoWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -/** - Enable a PCI driver to read PCI controller registers in PCI configuratio= n space. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] Offset The offset within the PCI configuration space for - the PCI controller. - @param[in] Count The number of PCI configuration operations to - perform. Bytes moved is Width size * Count, - starting at Offset. - - @param[in out] Buffer The destination buffer to store the results. - - @retval EFI_SUCCESS The data was read from the PCI controlle= r. - @retval EFI_INVALID_PARAMETER "Width" is invalid. - @retval EFI_INVALID_PARAMETER "Buffer" is NULL. - -**/ -EFI_STATUS -PciIoPciRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (= This); - EFI_STATUS Status; - - if ((Width < 0) || (Width >=3D EfiPciIoWidthMaximum) || (Buffer =3D=3D N= ULL)) { - return EFI_INVALID_PARAMETER; - } - - Status =3D PciRootBridgeIoMemRW ( - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, - Count, - TRUE, - (PTR)(UINTN)Buffer, - TRUE, - (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix= me ConfigSpace - ); - - return Status; -} - -/** - Enable a PCI driver to write PCI controller registers in PCI configurati= on space. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] Offset The offset within the PCI configuration space for - the PCI controller. - @param[in] Count The number of PCI configuration operations to - perform. Bytes moved is Width size * Count, - starting at Offset. - - @param[in out] Buffer The source buffer to write data from. - - @retval EFI_SUCCESS The data was read from the PCI controlle= r. - @retval EFI_INVALID_PARAMETER "Width" is invalid. - @retval EFI_INVALID_PARAMETER "Buffer" is NULL. - -**/ -EFI_STATUS -PciIoPciWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (= This); - - if ((Width < 0) || (Width >=3D EfiPciIoWidthMaximum) || (Buffer =3D=3D N= ULL)) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Wid= th, - Count, - TRUE, - (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace= ) + Offset), //Fix me ConfigSpace - TRUE, - (PTR)(UINTN)Buffer - ); -} - -EFI_STATUS -PciIoCopyMem ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 DestBarIndex, - IN UINT64 DestOffset, - IN UINT8 SrcBarIndex, - IN UINT64 SrcOffset, - IN UINTN Count - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoMap ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ) -{ - DMA_MAP_OPERATION DmaOperation; - - if (Operation =3D=3D EfiPciIoOperationBusMasterRead) { - DmaOperation =3D MapOperationBusMasterRead; - } else if (Operation =3D=3D EfiPciIoOperationBusMasterWrite) { - DmaOperation =3D MapOperationBusMasterWrite; - } else if (Operation =3D=3D EfiPciIoOperationBusMasterCommonBuffer) { - DmaOperation =3D MapOperationBusMasterCommonBuffer; - } else { - return EFI_INVALID_PARAMETER; - } - return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, = Mapping); -} - -EFI_STATUS -PciIoUnmap ( - IN EFI_PCI_IO_PROTOCOL *This, - IN VOID *Mapping - ) -{ - return DmaUnmap (Mapping); -} - -/** - Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommon= Buffer - mapping. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Type This parameter is not used and must be ignored. - @param[in] MemoryType The type of memory to allocate, EfiBootService= sData or - EfiRuntimeServicesData. - @param[in] Pages The number of pages to allocate. - @param[out] HostAddress A pointer to store the base system memory addr= ess of - the allocated range. - @param[in] Attributes The requested bit mask of attributes for the a= llocated - range. Only the attributes, - EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and - EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used wi= th this - function. If any other bits are set, then EFI_= UNSUPPORTED - is returned. This function ignores this bit ma= sk. - - @retval EFI_SUCCESS The requested memory pages were allocate= d. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_INVALID_PARAMETER MemoryType is invalid. - @retval EFI_UNSUPPORTED Attributes is unsupported. - @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. - -**/ -EFI_STATUS -PciIoAllocateBuffer ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ) -{ - if (Attributes & - (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | - EFI_PCI_ATTRIBUTE_MEMORY_CACHED ))) { - return EFI_UNSUPPORTED; - } - - return DmaAllocateBuffer (MemoryType, Pages, HostAddress); -} - - -EFI_STATUS -PciIoFreeBuffer ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ) -{ - return DmaFreeBuffer (Pages, HostAddress); -} - - -EFI_STATUS -PciIoFlush ( - IN EFI_PCI_IO_PROTOCOL *This - ) -{ - return EFI_SUCCESS; -} - -/** - Retrieves this PCI controller's current PCI bus number, device number, a= nd function number. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instan= ce. - @param[out] SegmentNumber The PCI controller's current PCI segment nu= mber. - @param[out] BusNumber The PCI controller's current PCI bus number. - @param[out] DeviceNumber The PCI controller's current PCI device num= ber. - @param[out] FunctionNumber The PCI controller's current PCI function n= umber. - - @retval EFI_SUCCESS The PCI controller location was returned. - @retval EFI_INVALID_PARAMETER At least one out of the four output para= meters is - a NULL pointer. -**/ -EFI_STATUS -PciIoGetLocation ( - IN EFI_PCI_IO_PROTOCOL *This, - OUT UINTN *SegmentNumber, - OUT UINTN *BusNumber, - OUT UINTN *DeviceNumber, - OUT UINTN *FunctionNumber - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (= This); - - if ((SegmentNumber =3D=3D NULL) || (BusNumber =3D=3D NULL) || - (DeviceNumber =3D=3D NULL) || (FunctionNumber =3D=3D NULL) ) { - return EFI_INVALID_PARAMETER; - } - - *SegmentNumber =3D Private->Segment; - *BusNumber =3D 0xff; - *DeviceNumber =3D 0; - *FunctionNumber =3D 0; - - return EFI_SUCCESS; -} - -/** - Performs an operation on the attributes that this PCI controller support= s. - - The operations include getting the set of supported attributes, retrievi= ng - the current attributes, setting the current attributes, enabling attribu= tes, - and disabling attributes. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Operation The operation to perform on the attributes for = this - PCI controller. - @param[in] Attributes The mask of attributes that are used for Set, - Enable and Disable operations. - @param[out] Result A pointer to the result mask of attributes that= are - returned for the Get and Supported operations. = This - is an optional parameter that may be NULL for t= he - Set, Enable, and Disable operations. - - @retval EFI_SUCCESS The operation on the PCI controller's - attributes was completed. If the operati= on - was Get or Supported, then the attribute= mask - is returned in Result. - @retval EFI_INVALID_PARAMETER Operation is greater than or equal to - EfiPciIoAttributeOperationMaximum. - @retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL. - @retval EFI_INVALID_PARAMETER Operation is Supported and Result is NUL= L. - -**/ -EFI_STATUS -PciIoAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, - IN UINT64 Attributes, - OUT UINT64 *Result OPTIONAL - ) -{ - switch (Operation) { - case EfiPciIoAttributeOperationGet: - case EfiPciIoAttributeOperationSupported: - if (Result =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - // - // We are not a real PCI device so just say things we kind of do - // - *Result =3D EFI_PCI_DEVICE_ENABLE; - break; - - case EfiPciIoAttributeOperationSet: - case EfiPciIoAttributeOperationEnable: - case EfiPciIoAttributeOperationDisable: - if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) { - return EFI_UNSUPPORTED; - } - // Since we are not a real PCI device no enable/set or disable operati= ons exist. - return EFI_SUCCESS; - - default: - return EFI_INVALID_PARAMETER; - }; - return EFI_SUCCESS; -} - -EFI_STATUS -PciIoGetBarAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT8 BarIndex, - OUT UINT64 *Supports, OPTIONAL - OUT VOID **Resources OPTIONAL - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoSetBarAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN UINT8 BarIndex, - IN OUT UINT64 *Offset, - IN OUT UINT64 *Length - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_PCI_IO_PROTOCOL PciIoTemplate =3D -{ - PciIoPollMem, - PciIoPollIo, - { PciIoMemRead, PciIoMemWrite }, - { PciIoIoRead, PciIoIoWrite }, - { PciIoPciRead, PciIoPciWrite }, - PciIoCopyMem, - PciIoMap, - PciIoUnmap, - PciIoAllocateBuffer, - PciIoFreeBuffer, - PciIoFlush, - PciIoGetLocation, - PciIoAttributes, - PciIoGetBarAttributes, - PciIoSetBarAttributes, - 0, - 0 -}; - -EFI_STATUS -PciInstallDevice ( - IN UINTN DeviceId, - IN PHYSICAL_ADDRESS MemoryStart, - IN UINT64 MemorySize, - IN UINTN ClassCode1, - IN UINTN ClassCode2, - IN UINTN ClassCode3 - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - EFI_PCI_IO_PRIVATE_DATA *Private; - - // Configure USB host - ConfigureUSBHost (); - - // Create a private structure - Private =3D AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA)); - if (Private =3D=3D NULL) { - Status =3D EFI_OUT_OF_RESOURCES; - return Status; - } - - Private->Signature =3D EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; = // Fill in signature - Private->RootBridge.Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; = // Fake Root Bridge structure needs a signature too - Private->RootBridge.MemoryStart =3D MemoryStart; // Get the USB capabili= ty register base - Private->Segment =3D 0; = // Default to segment zero - - // Calculate the total size of the USB controller (OHCI + EHCI). - Private->RootBridge.MemorySize =3D MemorySize; //CapabilityLength + (HOS= T_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1)); - - // Create fake PCI config space: OHCI + EHCI - Private->ConfigSpace =3D AllocateZeroPool (sizeof (PCI_TYPE00)); - if (Private->ConfigSpace =3D=3D NULL) { - Status =3D EFI_OUT_OF_RESOURCES; - FreePool (Private); - return Status; - } - - // - // Configure PCI config space: OHCI + EHCI - // - Private->ConfigSpace->Hdr.VendorId =3D 0xFFFF; // Invalid vendor Id as i= t is not an actual device. - Private->ConfigSpace->Hdr.DeviceId =3D 0x0000; // Not relevant as the ve= ndor id is not valid. - Private->ConfigSpace->Hdr.ClassCode[0] =3D ClassCode1; - Private->ConfigSpace->Hdr.ClassCode[1] =3D ClassCode2; - Private->ConfigSpace->Hdr.ClassCode[2] =3D ClassCode3; - Private->ConfigSpace->Device.Bar[0] =3D MemoryStart; - - Handle =3D NULL; - - // Unique device path. - CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDe= vicePathTemplate)); - Private->DevicePath.AcpiDevicePath.UID =3D 1; // Use '1' to differentiat= e from PLDA root complex - Private->DevicePath.PciDevicePath.Device =3D DeviceId; - - // Copy protocol structure - CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate)= ); - - Status =3D gBS->InstallMultipleProtocolInterfaces (&Handle, - &gEfiPciIoProtocolGuid, = &Private->PciIoProtocol, - &gEfiDevicePathProtocolG= uid, &Private->DevicePath, - NULL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolIn= terfaces () failed.\n")); - } - - return Status; -} - -EFI_STATUS -PciEmulationEntryPoint ( - VOID - ) -{ - EFI_STATUS Status; - - Status =3D PciInstallDevice (0, FixedPcdGet32 (PcdSynopsysUsbOhciBaseAdd= ress), SIZE_64KB, PCI_IF_OHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install OHCI device.\n")= ); - } - - Status =3D PciInstallDevice (1, FixedPcdGet32 (PcdSynopsysUsbEhciBaseAdd= ress), SIZE_64KB, PCI_IF_EHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install EHCI device.\n")= ); - } - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h b/= ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h deleted file mode 100644 index de2855d01d6b..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h +++ /dev/null @@ -1,284 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#ifndef _PCI_ROOT_BRIDGE_H_ -#define _PCI_ROOT_BRIDGE_H_ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "ArmJunoDxeInternal.h" - -#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL -#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL -#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL - - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - - -#define ACPI_CONFIG_IO 0 -#define ACPI_CONFIG_MMIO 1 -#define ACPI_CONFIG_BUS 2 - -typedef struct { - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; - EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; -} ACPI_CONFIG_INFO; - - -#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F') - -typedef struct { - UINT32 Signature; - EFI_HANDLE Handle; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; - EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; - - UINT8 StartBus; - UINT8 EndBus; - UINT16 Type; - UINT32 MemoryStart; - UINT32 MemorySize; - UINTN IoOffset; - UINT32 IoStart; - UINT32 IoSize; - UINT64 PciAttributes; - - ACPI_CONFIG_INFO *Config; - -} PCI_ROOT_BRIDGE; - - -#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, I= o, PCI_ROOT_BRIDGE_SIGNATURE) - - -typedef union { - UINT8 volatile *Buffer; - UINT8 volatile *Ui8; - UINT16 volatile *Ui16; - UINT32 volatile *Ui32; - UINT64 volatile *Ui64; - UINTN volatile Ui; -} PTR; - - - -EFI_STATUS -EFIAPI -PciRootBridgeIoPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoUnmap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - OUT VOID *HostAddress - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ); - -// -// Private Function Prototypes -// -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINTN Count, - IN BOOLEAN InStrideFlag, - IN PTR In, - IN BOOLEAN OutStrideFlag, - OUT PTR Out - ); - -BOOLEAN -PciIoMemAddressValid ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT64 Address - ); - -EFI_STATUS -EmulatePciIoForEhci ( - INTN MvPciIfMaxIf - ); - -#endif diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c= b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c deleted file mode 100644 index f1eaceff28d8..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c +++ /dev/null @@ -1,299 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include "PciEmulation.h" - -BOOLEAN -PciRootBridgeMemAddressValid ( - IN PCI_ROOT_BRIDGE *Private, - IN UINT64 Address - ) -{ - if ((Address >=3D Private->MemoryStart) && (Address < (Private->MemorySt= art + Private->MemorySize))) { - return TRUE; - } - - return FALSE; -} - - -EFI_STATUS -PciRootBridgeIoMemRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINTN Count, - IN BOOLEAN InStrideFlag, - IN PTR In, - IN BOOLEAN OutStrideFlag, - OUT PTR Out - ) -{ - UINTN Stride; - UINTN InStride; - UINTN OutStride; - - Width =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); - Stride =3D (UINTN)1 << Width; - InStride =3D InStrideFlag ? Stride : 0; - OutStride =3D OutStrideFlag ? Stride : 0; - - // - // Loop for each iteration and move the data - // - switch (Width) { - case EfiPciWidthUint8: - for (;Count > 0; Count--, In.Buffer +=3D InStride, Out.Buffer +=3D Out= Stride) { - *In.Ui8 =3D *Out.Ui8; - } - break; - case EfiPciWidthUint16: - for (;Count > 0; Count--, In.Buffer +=3D InStride, Out.Buffer +=3D Out= Stride) { - *In.Ui16 =3D *Out.Ui16; - } - break; - case EfiPciWidthUint32: - for (;Count > 0; Count--, In.Buffer +=3D InStride, Out.Buffer +=3D Out= Stride) { - *In.Ui32 =3D *Out.Ui32; - } - break; - default: - return EFI_INVALID_PARAMETER; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRootBridgeIoPciRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ) -{ - return EFI_SUCCESS; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PR= OTOCOL. - @param Width Signifies the width of the memory operatio= ns. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffe= r to store the results. For write - operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the P= CI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE *Private; - UINTN AlignMask; - PTR In; - PTR Out; - - if ( Buffer =3D=3D NULL ) { - return EFI_INVALID_PARAMETER; - } - - Private =3D INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - - if (!PciRootBridgeMemAddressValid (Private, Address)) { - return EFI_INVALID_PARAMETER; - } - - AlignMask =3D (1 << (Width & 0x03)) - 1; - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - In.Buffer =3D Buffer; - Out.Buffer =3D (VOID *)(UINTN) Address; - - switch (Width) { - case EfiPciWidthUint8: - case EfiPciWidthUint16: - case EfiPciWidthUint32: - case EfiPciWidthUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); - - case EfiPciWidthFifoUint8: - case EfiPciWidthFifoUint16: - case EfiPciWidthFifoUint32: - case EfiPciWidthFifoUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); - - case EfiPciWidthFillUint8: - case EfiPciWidthFillUint16: - case EfiPciWidthFillUint32: - case EfiPciWidthFillUint64: - return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); - - default: - break; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PR= OTOCOL. - @param Width Signifies the width of the memory operatio= ns. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffe= r to store the results. For write - operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the P= CI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE *Private; - UINTN AlignMask; - PTR In; - PTR Out; - - if ( Buffer =3D=3D NULL ) { - return EFI_INVALID_PARAMETER; - } - - Private =3D INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - - if (!PciRootBridgeMemAddressValid (Private, Address)) { - return EFI_INVALID_PARAMETER; - } - - AlignMask =3D (1 << (Width & 0x03)) - 1; - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - In.Buffer =3D (VOID *)(UINTN) Address; - Out.Buffer =3D Buffer; - - switch (Width) { - case EfiPciWidthUint8: - case EfiPciWidthUint16: - case EfiPciWidthUint32: - case EfiPciWidthUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); - - case EfiPciWidthFifoUint8: - case EfiPciWidthFifoUint16: - case EfiPciWidthFifoUint32: - case EfiPciWidthFifoUint64: - return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); - - case EfiPciWidthFillUint8: - case EfiPciWidthFillUint16: - case EfiPciWidthFillUint32: - case EfiPciWidthFillUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); - - default: - break; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PR= OTOCOL. - @param Width Signifies the width of the memory operatio= ns. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffe= r to store the results. For write - operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the P= CI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PR= OTOCOL. - @param Width Signifies the width of the memory operatio= ns. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffe= r to store the results. For write - operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the P= CI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); -} --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 149140071017813.832238438833997; Wed, 5 Apr 2017 06:58:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E448C20D77DA4; Wed, 5 Apr 2017 06:58:27 -0700 (PDT) Received: from mail-wr0-x233.google.com (mail-wr0-x233.google.com [IPv6:2a00:1450:400c:c0c::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A9D96203BF032 for ; Wed, 5 Apr 2017 06:58:25 -0700 (PDT) Received: by mail-wr0-x233.google.com with SMTP id k6so15865120wre.2 for ; Wed, 05 Apr 2017 06:58:25 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id 127sm22522793wmt.20.2017.04.05.06.58.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Apr 2017 06:58:23 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PSg1GnRpY/Gn12yShxInZ5eDuwa6zFfmpQd+mXlLa8Y=; b=VWtRJS6jTClUwMRYnKvX5KfQg3xgYNF7GleS1Kn2VPHygfqmTE8N4wgTP6waJH2t7a JnuPO6wJm+00J2v2fxO7K1sopiWN2lHxXqGLd7ZOdeGI+E81GFYvSldq7J/PHg+W8/zB +2un58+W31eM9rNliK1YGwGtWkyh2RFML7pMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PSg1GnRpY/Gn12yShxInZ5eDuwa6zFfmpQd+mXlLa8Y=; b=fxVJOC6oS3ThbbPDa2/Qi6hmatgJ14ikMtnEsst1qhrY+NAiQ3GsaOq74iP+wDb3Bz ZF9tspJ5/CbmgAyZ/Qdbd6A5h9ajr+EgC5VqqqOiyefCQ5/Gk95cy4B5pT0n7YX6Zmr8 +hF8jwGklQZproHf3dhqjL9uC7cyntlyLkQfwihTrQmZJOqGAhbgA7sQwuH3j4IdDOzn rg/CJ/SmnZ1lVWzUjCIzjKw/Rncc4ncE63XOoxupRByojz0k/hk1240X+EgjzQuWRYWc Pi2O84yXTq+8bA+cwfyEAjbIo4EGe3EmyH8lwUZqCRW7ui5JQtBmXzCJ3DVC1+V65a6+ 8MaA== X-Gm-Message-State: AFeK/H0GJoByF+0gOelLFgmnaoo6rVzZq/kHpipv8p4ZuvsVRK54K3pX103EA9K6JY20ZSUb X-Received: by 10.223.146.164 with SMTP id 33mr25211598wrn.17.1491400704185; Wed, 05 Apr 2017 06:58:24 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Apr 2017 14:58:05 +0100 Message-Id: <20170405135807.28425-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170405135807.28425-1-ard.biesheuvel@linaro.org> References: <20170405135807.28425-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 resend v4 4/6] ArmPlatformPkg/ArmJunoDxe: don't register OnEndOfDxe event on rev R0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The ArmJunoDxe driver code registers a callback for the EndOfDxe event, at which time it does some manipulation of the PCI peripherals on the board. Given that R0 has no working PCIe, instead of conditionally performing these operations, omit the registration of the callback altogether on that platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 43 +++++++++--= --------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/Ar= mPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c index 14ff189a3078..f7e33961b4e7 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -379,7 +379,6 @@ OnEndOfDxe ( EFI_DEVICE_PATH_PROTOCOL* PciRootComplexDevicePath; EFI_HANDLE Handle; EFI_STATUS Status; - UINT32 JunoRevision; =20 // // PCI Root Complex initialization @@ -395,13 +394,9 @@ OnEndOfDxe ( Status =3D gBS->ConnectController (Handle, NULL, PciRootComplexDevicePat= h, FALSE); ASSERT_EFI_ERROR (Status); =20 - GetJunoRevision (JunoRevision); - - if (JunoRevision !=3D JUNO_REVISION_R0) { - Status =3D ArmJunoSetNicMacAddress (); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "ArmJunoDxe: Failed to set Marvell Yukon NIC MA= C address\n")); - } + Status =3D ArmJunoSetNicMacAddress (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ArmJunoDxe: Failed to set Marvell Yukon NIC MAC = address\n")); } } =20 @@ -511,22 +506,6 @@ ArmJunoEntryPoint ( } } =20 - // - // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. - // The "OnEndOfDxe()" function is declared as the call back function. - // It will be called at the end of the DXE phase when an event of the - // same group is signalled to inform about the end of the DXE phase. - // Install the INSTALL_FDT_PROTOCOL protocol. - // - Status =3D gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - OnEndOfDxe, - NULL, - &gEfiEndOfDxeEventGroupGuid, - &EndOfDxeEvent - ); - // Install dynamic Shell command to run baremetal binaries. Status =3D ShellDynCmdRunAxfInstall (ImageHandle); if (EFI_ERROR (Status)) { @@ -555,6 +534,22 @@ ArmJunoEntryPoint ( // Enable PCI enumeration PcdSetBool (PcdPciDisableBusEnumeration, FALSE); =20 + // + // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. + // The "OnEndOfDxe()" function is declared as the call back function. + // It will be called at the end of the DXE phase when an event of the + // same group is signalled to inform about the end of the DXE phase. + // Install the INSTALL_FDT_PROTOCOL protocol. + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + // Declare the related ACPI Tables EfiCreateProtocolNotifyEvent ( &gEfiAcpiTableProtocolGuid, --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491400713366163.60981701172216; Wed, 5 Apr 2017 06:58:33 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3288F20D77DAA; Wed, 5 Apr 2017 06:58:32 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3A14621A04811 for ; Wed, 5 Apr 2017 06:58:30 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id j90so9010001lfk.2 for ; Wed, 05 Apr 2017 06:58:30 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id 127sm22522793wmt.20.2017.04.05.06.58.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Apr 2017 06:58:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ym/dMY5tPDu9r6oo3Zf4op1cF9hJhYrH7z5j+vwmBDA=; b=i9oLXLDkRlxSB+Xx3zt+ZRRuacgawJ5VF6Yj1YvU5JRg2d6fp8oLeoTZwwq5SLlHTo HXv5gxnN9jonclEpEfLuK+bL0gXqrMJK2Qxl2VZ16H4ao5oWtokEP3C3kL3IYPYsnJlT Q6wjSG2Yua/bIjWpHE1KrIym9ESKekWdEjbJk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ym/dMY5tPDu9r6oo3Zf4op1cF9hJhYrH7z5j+vwmBDA=; b=ltxqSEIYQ3SePnDFm41dBTO4sAAtwG9eX5r6gKPV9RNSWZCRVVt4N3h5g5HmnSehoF 0KOUUn77PMDET5F/vVg4y2zCvIELVXo4dnV1RyfQjCwdBg4k9r5OGezezRzkke3GuRMJ Gwkc6hV/AYA3xfpBBferVIrLfFKPgWhYrROCq/3YlET+P2GcDS5SeLr5wZR5eF58q7hR stvqT6wZLOAQipFZb6nKTRgbeKXH/A9DFLh3DULaG4Fp+mBL9m94pmDtZ8Ylyan4dbNE 1h8+GsPmps1bnyorXC0yGoofcaSfWlcg8JCB4T8lGbyJEQm1UVV2G+qhrQwWe/NrX10q L7cA== X-Gm-Message-State: AFeK/H2MoWCI78B8es+RhCUhy0ePq/aruCR7l/iULIwnbNKTUc9r9+Va EweW8/5/xDmaLroF X-Received: by 10.28.13.69 with SMTP id 66mr18857132wmn.137.1491400707280; Wed, 05 Apr 2017 06:58:27 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Apr 2017 14:58:06 +0100 Message-Id: <20170405135807.28425-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170405135807.28425-1-ard.biesheuvel@linaro.org> References: <20170405135807.28425-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v4 resend v4 5/6] ArmPlatformPkg/ArmJunoPkg: remove PCI host bridge driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We are switching the Juno platform to the generic host bridge driver, which involves implementing PciHostBridgeLib for this platform, and plugging it into MdeModulePkg's PciHostBridgeDxe.inf. Since the platform descriptions no longer live in upstream EDK2, the PciHostBridgeLib implementation (which reuses some of the code removed here) will live there as well. But this PciHostBridgeDxe driver is no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c = | 199 ------ ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h = | 324 --------- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf = | 76 -- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResourceAl= location.c | 642 ----------------- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c = | 748 -------------------- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c = | 170 ----- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h = | 111 --- 7 files changed, 2270 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBrid= ge.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c deleted file mode 100644 index e1a6b749e4e6..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ /dev/null @@ -1,199 +0,0 @@ -/** @file -* Pci Host Bridge support for the Xpress-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#include "PciHostBridge.h" - -#include - -/** - * PCI Root Bridge Description - */ -typedef struct { - UINT32 AcpiUid; - UINT64 MemAllocAttributes; -} PCI_ROOT_BRIDGE_DESC; - -PCI_ROOT_BRIDGE_DESC PciRbDescriptions =3D { - 0, // AcpiUid - PCI_MEMORY_ALLOCATION_ATTRIBUTES // MemAllocAttributes -}; - -/** - * Template for PCI Host Bridge Instance - **/ -STATIC CONST PCI_HOST_BRIDGE_INSTANCE -gPciHostBridgeInstanceTemplate =3D { - PCI_HOST_BRIDGE_SIGNATURE, //Signature - NULL, // Handle - NULL, // ImageHandle - NULL, // RootBridge - TRUE, // CanRestarted - NULL, // CpuIo - NULL, // Metronome - { // ResAlloc - PciHbRaNotifyPhase, // ResAlloc.NotifyPhase - PciHbRaGetNextRootBridge, // ResAlloc.GetNextRootBridge - PciHbRaGetAllocAttributes, // ResAlloc.GetAllocAttributes - PciHbRaStartBusEnumeration, // ResAlloc.StartBusEnumeration - PciHbRaSetBusNumbers, // ResAlloc.SetBusNumbers - PciHbRaSubmitResources, // ResAlloc.SubmitResources - PciHbRaGetProposedResources, // ResAlloc.GetProposedResources - PciHbRaPreprocessController // ResAlloc.PreprocessController - } -}; -PCI_HOST_BRIDGE_INSTANCE* gpPciHostBridgeInstance; - -EFI_STATUS -HostBridgeConstructor ( - IN OUT PCI_HOST_BRIDGE_INSTANCE** Instance, - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - PCI_HOST_BRIDGE_INSTANCE* HostBridge; - - PCI_TRACE ("HostBridgeConstructor()"); - - if (Instance =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - HostBridge =3D AllocateCopyPool (sizeof (PCI_HOST_BRIDGE_INSTANCE), &gPc= iHostBridgeInstanceTemplate); - if (HostBridge =3D=3D NULL) { - PCI_TRACE ("HostBridgeConstructor(): FAIL to allocate resources"); - return EFI_OUT_OF_RESOURCES; - } - - // It will also create a device handle for the PCI Host Bridge (as HostB= ridge->Handle =3D=3D NULL) - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &HostBridge->Handle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &Hos= tBridge->ResAlloc, - NULL - ); - if (EFI_ERROR (Status)) { - PCI_TRACE ("HostBridgeConstructor(): FAIL to install resource allocato= r"); - FreePool (HostBridge); - return EFI_DEVICE_ERROR; - } else { - PCI_TRACE ("HostBridgeConstructor(): SUCCEED to install resource alloc= ator"); - } - - Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)= (&(HostBridge->CpuIo))); - ASSERT_EFI_ERROR (Status); - - Status =3D gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (V= OID **)(&(HostBridge->Metronome))); - ASSERT_EFI_ERROR (Status); - - HostBridge->ImageHandle =3D ImageHandle; - - *Instance =3D HostBridge; - return EFI_SUCCESS; -} - -EFI_STATUS -HostBridgeDestructor ( - IN PCI_HOST_BRIDGE_INSTANCE* HostBridge - ) -{ - EFI_STATUS Status; - - Status =3D gBS->UninstallMultipleProtocolInterfaces ( - HostBridge->Handle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &H= ostBridge->ResAlloc, - NULL - ); - - if (HostBridge->RootBridge) { - PciRbDestructor (HostBridge->RootBridge); - } - - FreePool (HostBridge); - - return Status; -} - -/** - Entry point of this driver - - @param ImageHandle Handle of driver image - @param SystemTable Point to EFI_SYSTEM_TABLE - - @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource - @retval EFI_DEVICE_ERROR Can not install the protocol instance - @retval EFI_SUCCESS Success to initialize the Pci host bridge. -**/ -EFI_STATUS -EFIAPI -PciHostBridgeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - PCI_TRACE ("PciHostBridgeEntryPoint()"); - - // Creation of the PCI Host Bridge Instance - Status =3D HostBridgeConstructor (&gpPciHostBridgeInstance, ImageHandle); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciHostBridgeEntryPoint(): ERROR: Fail to construct PCI Ho= st Bridge."); - return Status; - } - - // Creation of the PCIe Root Bridge - Status =3D PciRbConstructor (gpPciHostBridgeInstance, PciRbDescriptions.= AcpiUid, PciRbDescriptions.MemAllocAttributes); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciHostBridgeEntryPoint(): ERROR: Fail to construct PCI Ro= ot Bridge."); - return Status; - } - ASSERT (gpPciHostBridgeInstance->RootBridge->Signature =3D=3D PCI_ROOT_B= RIDGE_SIGNATURE); - - // PCI 32bit Memory Space - Status =3D gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - PCI_MEM32_BASE, - PCI_MEM32_SIZE, - 0 - ); - - // PCI 64bit Memory Space - Status =3D gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - PCI_MEM64_BASE, - PCI_MEM64_SIZE, - 0 - ); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -PciHostBridgeUnload ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - - // Free Reserved memory space in GCD - gDS->RemoveMemorySpace (PCI_MEM32_BASE, PCI_MEM32_SIZE); - gDS->RemoveMemorySpace (PCI_MEM64_BASE, PCI_MEM64_SIZE); - - // Free the allocated memory - Status =3D HostBridgeDestructor (gpPciHostBridgeInstance); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBrid= ge.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h deleted file mode 100644 index e53f4fa3a8d8..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ /dev/null @@ -1,324 +0,0 @@ -/** @file -* Header containing the structure specific to the Xpress-RICH3 PCIe Root = Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#ifndef __PCIHOSTBRIDGE_H -#define __PCIHOSTBRIDGE_H - -#include - -#include "XPressRich3.h" - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) - -#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value =3D (UINT32)(Val); = CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootP= ortBaseAddress)+(Add)),1,&Value); } -#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWi= dthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } - -#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value =3D (UINT32)(Val); C= puIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieContro= lBaseAddress)+(Add)),1,&Value); } -#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWid= thUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } - -/** - * PCI Root Bridge Device Path (ACPI Device Node + End Node) - */ -typedef struct { - ACPI_HID_DEVICE_PATH Acpi; - EFI_DEVICE_PATH_PROTOCOL End; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - -typedef enum { - ResTypeIo =3D 0, - ResTypeMem32, - ResTypePMem32, - ResTypeMem64, - ResTypePMem64, - ResTypeMax -} PCI_RESOURCE_TYPE; - -#define ACPI_SPECFLAG_PREFETCHABLE 0x06 -#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL -#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL - -typedef struct { - UINT64 Base; - UINT64 Length; - UINT64 Alignment; -} PCI_RESOURCE_ALLOC; - -typedef struct _PCI_HOST_BRIDGE_INSTANCE PCI_HOST_BRIDGE_INSTANCE; - -/** - * PCI Root Bridge Instance structure - **/ -typedef struct { - UINTN Signature; - EFI_HANDLE Handle; - PCI_HOST_BRIDGE_INSTANCE *HostBridge; - // - // Set Type of memory allocation (could be EFI_PCI_HOST_BRIDGE_COMBINE_M= EM_PMEM - // and EFI_PCI_HOST_BRIDGE_MEM64_DECODE). - // - UINT64 MemAllocAttributes; - PCI_RESOURCE_ALLOC ResAlloc[ResTypeMax]; - UINTN BusStart; - UINTN BusLength; - UINT64 Supports; - UINT64 Attributes; - EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; -} PCI_ROOT_BRIDGE_INSTANCE; - -/** - * PCI Host Bridge Instance structure - **/ -struct _PCI_HOST_BRIDGE_INSTANCE { - UINTN Signature; - EFI_HANDLE Handle; - EFI_HANDLE ImageHandle; - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; - // - // The enumeration cannot be restarted after the process goes into the n= on initial - // enumeration phase. - // - BOOLEAN CanRestarted; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; -}; - -#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h'= , 's', 't') -#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2'= , 'p', 'b') -#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE= _INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) -#define INSTANCE_FROM_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE= _INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) - -/** - * PCI Host Bridge Resource Allocator Functions - **/ -EFI_STATUS PciHbRaNotifyPhase ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ); - -EFI_STATUS PciHbRaGetNextRootBridge ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHandle - ); - -EFI_STATUS PciHbRaGetAllocAttributes ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ); - -EFI_STATUS PciHbRaStartBusEnumeration ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -EFI_STATUS PciHbRaSetBusNumbers ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -EFI_STATUS PciHbRaSubmitResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -EFI_STATUS PciHbRaGetProposedResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -EFI_STATUS PciHbRaPreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ); - - -/** - * PCI Root Bridge - **/ -EFI_STATUS PciRbPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS PciRbPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS PciRbMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ); - -EFI_STATUS PciRbMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ); - -EFI_STATUS PciRbUnMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ); - -EFI_STATUS PciRbAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - IN OUT VOID **HostAddress, - IN UINT64 Attributes - ); - -EFI_STATUS PciRbFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ); - -EFI_STATUS PciRbFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ); - -EFI_STATUS PciRbSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ); - -EFI_STATUS PciRbGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supports, - OUT UINT64 *Attributes - ); - -EFI_STATUS PciRbConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ); - -/** - * PCI Root Bridge Functions - **/ -EFI_STATUS -PciRbConstructor ( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridge, - IN UINT32 PciAcpiUid, - IN UINT64 MemAllocAttributes - ); - -EFI_STATUS -PciRbDestructor ( - IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge - ); - -EFI_STATUS -HWPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ); - -#endif diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBrid= geDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridg= eDxe.inf deleted file mode 100644 index de28c805ae6e..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.i= nf +++ /dev/null @@ -1,76 +0,0 @@ -#/** @file -# INF file for the Xpress-RICH3 PCIe Root Complex -# -# Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -#**/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PciHostBridge - FILE_GUID =3D C62F4B20-681E-11DF-8F0D-0002A5D5C51B - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - - ENTRY_POINT =3D PciHostBridgeEntryPoint - UNLOAD_IMAGE =3D PciHostBridgeUnload - -[Packages] - MdePkg/MdePkg.dec - ArmPkg/ArmPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - MemoryAllocationLib - DxeServicesTableLib - CacheMaintenanceLib - DmaLib - -[Sources] - PciHostBridge.c - PciHostBridgeResourceAllocation.c - PciRootBridge.c - XPressRich3.c - -[Protocols] - gEfiPciHostBridgeResourceAllocationProtocolGuid # Produced - gEfiPciRootBridgeIoProtocolGuid # Produced - gEfiDevicePathProtocolGuid # Produced - gEfiCpuIo2ProtocolGuid # Consumed - gEfiMetronomeArchProtocolGuid # Consumed - -[FeaturePcd] - gArmJunoTokenSpaceGuid.PcdPciMaxPayloadFixup - -[Pcd.common] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - - gArmTokenSpaceGuid.PcdPciBusMin - gArmTokenSpaceGuid.PcdPciBusMax - gArmTokenSpaceGuid.PcdPciIoBase - gArmTokenSpaceGuid.PcdPciIoSize - gArmTokenSpaceGuid.PcdPciMmio32Base - gArmTokenSpaceGuid.PcdPciMmio32Size - gArmTokenSpaceGuid.PcdPciMmio64Base - gArmTokenSpaceGuid.PcdPciMmio64Size - - gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress - gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress - gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress - gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize - -[Depex] - gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBrid= geResourceAllocation.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe= /PciHostBridgeResourceAllocation.c deleted file mode 100644 index de60db718408..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResou= rceAllocation.c +++ /dev/null @@ -1,642 +0,0 @@ -/** @file -* Implementation of the Pci Host Bridge Resource Allocation for the Xpres= s-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#include "PciHostBridge.h" - -EFI_STATUS -PciHbRaNotifyPhase ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 AddrLen; - UINTN BitsOfAlignment; - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - PCI_TRACE ("PciHbRaNotifyPhase()"); - - // Check RootBridge Signature - ASSERT (HostBridgeInstance->RootBridge->Signature =3D=3D PCI_ROOT_BRIDGE= _SIGNATURE); - - // The enumeration cannot be restarted after the process has been furthe= r than the first phase - if (Phase =3D=3D EfiPciHostBridgeBeginEnumeration) { - if (!HostBridgeInstance->CanRestarted) { - return EFI_NOT_READY; - } - } else { - HostBridgeInstance->CanRestarted =3D FALSE; - } - - switch (Phase) { - case EfiPciHostBridgeBeginEnumeration: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginEnumeration)"); - // Resets the host bridge PCI apertures and internal data structures - Status =3D HWPciRbInit (HostBridgeInstance->CpuIo); - if (EFI_ERROR (Status)) { - return Status; - } - break; - - case EfiPciHostBridgeBeginBusAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginBusAllocation)"); - // The bus allocation phase is about to begin - break; - - case EfiPciHostBridgeEndBusAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndBusAllocation)"); - // The bus allocation and bus programming phase is complete. All the P= CI-to-PCI bridges have been given and written back - // a bus number range into their configuration - break; - - case EfiPciHostBridgeBeginResourceAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginResourceAllocation= )"); - // The resource allocation phase is about to begin. - break; - - case EfiPciHostBridgeAllocateResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeAllocateResources)"); - // Allocates resources per previously submitted requests for all the P= CI root bridges. The resources have been submitted to - // PciHbRaSubmitResources() before. - - RootBridgeInstance =3D HostBridgeInstance->RootBridge; - if (RootBridgeInstance->ResAlloc[ResTypeIo].Length !=3D 0) { - BitsOfAlignment =3D HighBitSet64 (RootBridgeInstance->ResAlloc[ResTy= peIo].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen =3D RootBridgeInstance->ResAlloc[ResTypeIo].Length; - - Status =3D gDS->AllocateIoSpace ( - EfiGcdAllocateAnySearchBottomUp, - EfiGcdIoTypeIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - // If error then ResAlloc[n].Base =3D=3D0 - if (!EFI_ERROR (Status)) { - RootBridgeInstance->ResAlloc[ResTypeIo].Base =3D (UINTN)BaseAddr= ess; - } - } - - if (RootBridgeInstance->ResAlloc[ResTypeMem32].Length !=3D 0) { - BitsOfAlignment =3D HighBitSet64 (RootBridgeInstance->ResAlloc[ResTy= peMem32].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen =3D RootBridgeInstance->ResAlloc[ResTypeMem32].Length; - - // Top of the 32bit PCI Memory space - BaseAddress =3D FixedPcdGet64 (PcdPciMmio32Base) + FixedPcdGet64 (Pc= dPciMmio32Size); - - Status =3D gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 32bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >=3D FixedPcdGet64 (PcdPciMm= io32Base))) { - RootBridgeInstance->ResAlloc[ResTypeMem32].Base =3D (UINTN)BaseA= ddress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypePMem32].Length !=3D 0) { - BitsOfAlignment =3D HighBitSet64 (RootBridgeInstance->ResAlloc[ResTy= pePMem32].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen =3D RootBridgeInstance->ResAlloc[ResTypePMem32].Length; - - // Top of the 32bit PCI Memory space - BaseAddress =3D FixedPcdGet64 (PcdPciMmio32Base) + FixedPcdGet64 (Pc= dPciMmio32Size); - - Status =3D gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 32bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >=3D FixedPcdGet64 (PcdPciMm= io32Base))) { - RootBridgeInstance->ResAlloc[ResTypePMem32].Base =3D (UINTN)BaseAd= dress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypeMem64].Length !=3D 0) { - BitsOfAlignment =3D HighBitSet64 (RootBridgeInstance->ResAlloc[ResTy= peMem64].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen =3D RootBridgeInstance->ResAlloc[ResTypeMem64].Length; - - // Top of the 64bit PCI Memory space - BaseAddress =3D FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (Pc= dPciMmio64Size); - - Status =3D gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 64bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >=3D FixedPcdGet64 (PcdPciMm= io64Base))) { - RootBridgeInstance->ResAlloc[ResTypeMem64].Base =3D (UINTN)BaseA= ddress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypePMem64].Length !=3D 0) { - BitsOfAlignment =3D HighBitSet64 (RootBridgeInstance->ResAlloc[ResTy= pePMem64].Alignment) + 1; //Get the number of '1' in Alignment - AddrLen =3D RootBridgeInstance->ResAlloc[ResTypePMem64].Length; - - // Top of the 64bit PCI Memory space - BaseAddress =3D FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (Pc= dPciMmio64Size); - - Status =3D gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 64bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >=3D FixedPcdGet64 (PcdPciMm= io64Base))) { - RootBridgeInstance->ResAlloc[ResTypePMem64].Base =3D (UINTN)Base= Address; - } - } - - break; - - case EfiPciHostBridgeSetResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeSetResources)"); - // Programs the host bridge hardware to decode previously allocated re= sources (proposed resources) - // for all the PCI root bridges. The PCI bus driver will now program t= he resources - break; - - case EfiPciHostBridgeFreeResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeFreeResources)"); - // Deallocates resources that were previously allocated for all the PC= I root bridges and resets the - // I/O and memory apertures to their initial state.*/ - break; - - case EfiPciHostBridgeEndResourceAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndResourceAllocation)"= ); - break; - - case EfiPciHostBridgeEndEnumeration: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndEnumeration)"); - break; - - default: - DEBUG ((EFI_D_INFO, "PciHbRaNotifyPhase(Phase:%d)\n", Phase)); - ASSERT (0); - } - - return EFI_SUCCESS; -} - -/** - * PciHbRaGetNextRootBridge() returns the next root bridge attached to the= 'This' PCI Host Bridge. - * As we have only got one PCI Root Bridge in this PCI interface, we retur= n either this root bridge - * if it the first time we call this function (*RootBridgeHandle =3D=3D NU= LL) or we return EFI_NOT_FOUND - **/ -EFI_STATUS -PciHbRaGetNextRootBridge ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHandle - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - PCI_TRACE ("PciHbRaGetNextRootBridge()"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - ASSERT (HostBridgeInstance->RootBridge !=3D NULL); - - //Check RootBridge Signature - ASSERT (HostBridgeInstance->RootBridge->Signature =3D=3D PCI_ROOT_BRIDGE= _SIGNATURE); - - if (*RootBridgeHandle =3D=3D NULL) { - *RootBridgeHandle =3D HostBridgeInstance->RootBridge->Handle; - return EFI_SUCCESS; - } else if (*RootBridgeHandle =3D=3D HostBridgeInstance->RootBridge->Hand= le) { - return EFI_NOT_FOUND; - } else { - return EFI_INVALID_PARAMETER; - } -} - -/** PciHbRaGetAllocAttributes() returns the resource allocation attributes= supported by this PCI Root Bridge. - * A PCI Root bridge could support these types : - * - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM : does not support separate= windows for nonprefetchable and prefetchable memory. - * - EFI_PCI_HOST_BRIDGE_MEM64_DECODE : supports 64-bit memory windows - **/ -EFI_STATUS -PciHbRaGetAllocAttributes ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - PCI_TRACE ("PciHbRaGetAllocAttributes()"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - // Check if the RootBridgeHandle is the one managed by this PCI Host Bri= dge - ASSERT (HostBridgeInstance->RootBridge !=3D NULL); - if (HostBridgeInstance->RootBridge->Handle !=3D RootBridgeHandle) { - return EFI_INVALID_PARAMETER; - } - - *Attributes =3D HostBridgeInstance->RootBridge->MemAllocAttributes; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaStartBusEnumeration ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - VOID *Buffer; - UINT8 *Ptr; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - // Fill an ACPI descriptor table with the Bus Number Range. This informa= tion will be used by the PCI Bus driver - // to set bus numbers to PCI-to-PCI bridge. - PCI_TRACE ("PciHbRaStartBusEnumeration()"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - Buffer =3D AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) = + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Ptr =3D (UINT8 *)Buffer; - - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->Desc =3D ACPI_ADDRESS_SPACE_= DESCRIPTOR; // QWORD Address space Descriptor - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->Len =3D 0x2B; // Length = of this descriptor in bytes not including the first two fields - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType =3D ACPI_ADDRESS_SPA= CE_TYPE_BUS; // Resource Type Bus Number Range - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->GenFlag =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->SpecificFlag =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrSpaceGranularity =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin =3D HostBridgeI= nstance->RootBridge->BusStart; // Bus Start - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMax =3D 0; // Bu= s Max - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrTranslationOffset =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen =3D FixedPcdGet32 (P= cdPciBusMax) - FixedPcdGet32 (PcdPciBusMin) + 1; - - Ptr =3D Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc =3D ACPI_END_TAG_DESCRIPTOR; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Checksum =3D 0x0; - - *Configuration =3D Buffer; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaSetBusNumbers ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - UINT8 *Ptr; - UINTN BusStart; - UINTN BusEnd; - UINTN BusLen; - - PCI_TRACE ("PciHbRaSetBusNumbers()"); - - Ptr =3D Configuration; - if (*Ptr !=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - // Check if the passed ACPI descriptor table define a Bus Number Range - if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType !=3D ACPI_ADDRES= S_SPACE_TYPE_BUS) { - return EFI_INVALID_PARAMETER; - } - - // Check if the Configuration only passed one ACPI Descriptor (+ End Des= criptor) - if (*((UINT8*)(Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR))) !=3D A= CPI_END_TAG_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - ASSERT (HostBridgeInstance->RootBridge !=3D NULL); - if (HostBridgeInstance->RootBridge->Handle !=3D RootBridgeHandle) { - return EFI_INVALID_PARAMETER; - } - - BusStart =3D (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRang= eMin; - BusLen =3D (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen; - BusEnd =3D BusStart + BusLen - 1; - - ASSERT (BusStart <=3D BusEnd); // We should at least have PCI_BUS_ROOT a= nd PCI_SWITCH_BUS - ASSERT ((BusStart >=3D HostBridgeInstance->RootBridge->BusStart) && (Bus= Len <=3D HostBridgeInstance->RootBridge->BusLength)); - - HostBridgeInstance->RootBridge->BusStart =3D BusStart; - HostBridgeInstance->RootBridge->BusLength =3D BusLen; - - return EFI_SUCCESS; -} - -/** - * This function is used to submit all the I/O and memory resources that a= re required by the specified - * PCI root bridge. - **/ -EFI_STATUS -PciHbRaSubmitResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT8 *Ptr; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; - PCI_RESOURCE_TYPE ResType; - - PCI_TRACE ("PciHbRaSubmitResources()"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - if (Configuration =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // Check if the ACPI Descriptor tables is conformed - Ptr =3D (UINT8 *)Configuration; - while (*Ptr =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { // QWORD Address Spa= ce descriptor - Ptr +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; - } - if (*Ptr !=3D ACPI_END_TAG_DESCRIPTOR) { // End tag - return EFI_INVALID_PARAMETER; - } - - // Check the RootBridgeHandle - RootBridgeInstance =3D HostBridgeInstance->RootBridge; - ASSERT (RootBridgeInstance !=3D NULL); - if (RootBridgeHandle !=3D HostBridgeInstance->RootBridge->Handle) { - return EFI_INVALID_PARAMETER; - } - - Ptr =3D (UINT8 *)Configuration; - while ( *Ptr =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { // While the entry = is an ACPI Descriptor Table - Desc =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr; - - // Check if the description is valid - if (Desc->AddrLen > 0xffffffff) { - return EFI_INVALID_PARAMETER; - } - - if ((Desc->AddrRangeMax >=3D 0xffffffff) || (Desc->AddrRangeMax !=3D (= GetPowerOfTwo64 (Desc->AddrRangeMax + 1) - 1))) { - return EFI_INVALID_PARAMETER; - } - - switch (Desc->ResType) { - case ACPI_ADDRESS_SPACE_TYPE_MEM: - // Check invalid Address Space Granularity - if ((Desc->AddrSpaceGranularity !=3D 32) && (Desc->AddrSpaceGranular= ity !=3D 64)) { - return EFI_INVALID_PARAMETER; - } - - // check the memory resource request is supported by PCI root bridge - if (RootBridgeInstance->MemAllocAttributes =3D=3D EFI_PCI_HOST_BRIDG= E_COMBINE_MEM_PMEM && Desc->SpecificFlag =3D=3D 0x06) { - return EFI_INVALID_PARAMETER; - } - - if (Desc->AddrSpaceGranularity =3D=3D 32) { - if (Desc->SpecificFlag =3D=3D ACPI_SPECFLAG_PREFETCHABLE) { - ResType =3D ResTypePMem32; - } else { - ResType =3D ResTypeMem32; - } - } else { - if (Desc->SpecificFlag =3D=3D ACPI_SPECFLAG_PREFETCHABLE) { - ResType =3D ResTypePMem64; - } else { - ResType =3D ResTypeMem64; - } - } - RootBridgeInstance->ResAlloc[ResType].Length =3D Desc->AddrLen; - RootBridgeInstance->ResAlloc[ResType].Alignment =3D Desc->AddrRangeM= ax; - RootBridgeInstance->ResAlloc[ResType].Base =3D Desc->AddrRangeMin; - break; - case ACPI_ADDRESS_SPACE_TYPE_IO: - RootBridgeInstance->ResAlloc[ResTypeIo].Length =3D Desc->AddrLen; - RootBridgeInstance->ResAlloc[ResTypeIo].Alignment =3D Desc->AddrRang= eMax; - RootBridgeInstance->ResAlloc[ResTypeIo].Base =3D 0; - break; - default: - ASSERT (0); // Could be the case Desc->ResType =3D=3D ACPI_ADDRESS_S= PACE_TYPE_BUS - break; - } - Ptr +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - } - - return EFI_SUCCESS; -} - -/** Returns the proposed resource settings for the specified PCI root brid= ge. The resources have been submitted by - * PciHbRaSubmitResources() before - **/ -EFI_STATUS -PciHbRaGetProposedResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT32 i; - UINT32 ResAllocCount; - VOID *Buffer; - UINT8 *Ptr; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; - - PCI_TRACE ("PciHbRaGetProposedResources()"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - // Check the RootBridgeHandle - RootBridgeInstance =3D HostBridgeInstance->RootBridge; - ASSERT (RootBridgeInstance !=3D NULL); - if (RootBridgeHandle !=3D HostBridgeInstance->RootBridge->Handle) { - return EFI_INVALID_PARAMETER; - } - - // Count the number of Resource Allocated for this Root Bridge - ResAllocCount =3D 0; - for (i =3D 0; i < ResTypeMax; i++) { - if (RootBridgeInstance->ResAlloc[i].Length !=3D 0) ResAllocCount++; - } - - if (ResAllocCount =3D=3D 0) { - return EFI_INVALID_PARAMETER; - } - - Buffer =3D AllocateZeroPool (ResAllocCount * sizeof (EFI_ACPI_ADDRESS_SP= ACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Ptr =3D Buffer; - for (i =3D 0; i < ResTypeMax; i++) { - if (RootBridgeInstance->ResAlloc[i].Length !=3D 0) { // Base !=3D 0= if the resource has been allocated - Desc =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr; - - Desc->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; - Desc->Len =3D 0x2B; - Desc->GenFlag =3D 0; - Desc->AddrRangeMax =3D 0; - - switch (i) { - case ResTypeIo: - Desc->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; - Desc->SpecificFlag =3D 0; - Desc->AddrSpaceGranularity =3D 0; - break; - case ResTypeMem32: - Desc->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag =3D 0; - Desc->AddrSpaceGranularity =3D 32; - break; - case ResTypePMem32: - Desc->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag =3D ACPI_SPECFLAG_PREFETCHABLE; - Desc->AddrSpaceGranularity =3D 32; - break; - case ResTypeMem64: - Desc->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag =3D 0; - Desc->AddrSpaceGranularity =3D 64; - break; - case ResTypePMem64: - Desc->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag =3D ACPI_SPECFLAG_PREFETCHABLE; - Desc->AddrSpaceGranularity =3D 64; - break; - } - Desc->AddrRangeMin =3D RootBridgeInstance->ResAlloc[i].Base; - Desc->AddrTranslationOffset =3D (RootBridgeInstance->ResAlloc[i].Bas= e !=3D 0) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; - Desc->AddrLen =3D RootBridgeInstance->ResAlloc[i].Length; - Ptr +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - } - } - - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc =3D ACPI_END_TAG_DESCRIPTOR; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Checksum =3D 0x0; - - *Configuration =3D Buffer; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaPreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE* HostBridge; - PCI_ROOT_BRIDGE_INSTANCE* RootBridge; - UINT32 CapabilityPtr; - UINT32 CapabilityEntry; - UINT16 CapabilityID; - UINT32 DeviceCapability; - - PCI_TRACE ("PciHbRaPreprocessController()"); - - if (FeaturePcdGet (PcdPciMaxPayloadFixup)) { - // Do Max payload fixup for every devices - if (Phase =3D=3D EfiPciBeforeResourceCollection) { - // Get RootBridge Instance from Host Bridge Instance - HostBridge =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - RootBridge =3D HostBridge->RootBridge; - - // Get the first PCI Capability - CapabilityPtr =3D PCI_CAPBILITY_POINTER_OFFSET; - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint8, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress.F= unction, CapabilityPtr), - 1, - &CapabilityPtr - ); - CapabilityPtr &=3D 0x1FF; - - // Get Pci Express Capability - while (CapabilityPtr !=3D 0) { - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint16, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress= .Function, CapabilityPtr), - 1, - &CapabilityEntry - ); - - CapabilityID =3D (UINT8)CapabilityEntry; - - // Is PCIe capability ? - if (CapabilityID =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP) { - // Get PCIe Device Capabilities - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint32, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddre= ss.Function, CapabilityPtr + 0x8), - 1, - &DeviceCapability - ); - - // Force the Max Payload to 128 Bytes (128 Bytes Max Payload Siz= e =3D 0) - DeviceCapability &=3D ~ ((UINT32)(0x7 << 5 )); - // Max Read Request Size to 128 Bytes (128 Bytes Max Read Reques= t Size =3D 0) - DeviceCapability &=3D ~ ((UINT32)(0x7 << 12)); - // Enable all error reporting - DeviceCapability |=3D 0xF; - - RootBridge->Io.Pci.Write ( - &RootBridge->Io, - EfiPciWidthUint32, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddre= ss.Function, CapabilityPtr + 0x8), - 1, - &DeviceCapability - ); - - return EFI_SUCCESS; - } - CapabilityPtr =3D (CapabilityEntry >> 8) & 0xFF; - } - } - } - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBrid= ge.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c deleted file mode 100644 index 72d09156c066..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c +++ /dev/null @@ -1,748 +0,0 @@ -/** @file -* Implementation of the PCI Root Bridge Protocol for XPress-RICH3 PCIe Ro= ot Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#include "PciHostBridge.h" - -#include -#include - -#define CPUIO_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridge->C= puIo) -#define METRONOME_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridg= e->Metronome) - -/** - * PCI Root Bridge Instance Templates - */ -STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH gDevicePathTemplate =3D { - { - { ACPI_DEVICE_PATH, - ACPI_DP, - { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } - }, - EISA_PNP_ID (0x0A03), - 0 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { END_DEVICE_PATH_LENGTH, 0 } - } -}; - -STATIC CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL gIoTemplate =3D { - 0, - PciRbPollMem, - PciRbPollIo, - { - PciRbMemRead, - PciRbMemWrite - }, - { - PciRbIoRead, - PciRbIoWrite - }, - { - PciRbPciRead, - PciRbPciWrite - }, - PciRbCopyMem, - PciRbMap, - PciRbUnMap, - PciRbAllocateBuffer, - PciRbFreeBuffer, - PciRbFlush, - PciRbGetAttributes, - PciRbSetAttributes, - PciRbConfiguration, - 0 - }; - -typedef struct { - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[ResTypeMax+1]; - EFI_ACPI_END_TAG_DESCRIPTOR EndDesp; -} RESOURCE_CONFIGURATION; - - -RESOURCE_CONFIGURATION Configuration =3D { - {{ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_IO , 0, = 0, 0, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, = 0, 32, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, = 6, 32, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, = 0, 64, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, = 6, 64, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_BUS, 0, = 0, 0, 0, 255, 0, 255}}, - {ACPI_END_TAG_DESCRIPTOR, 0} -}; - - -EFI_STATUS -PciRbPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - - PCI_TRACE ("PciRbPollMem()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - Metronome =3D METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Result =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - // No matter what, always do a single poll. - Status =3D This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - if (Delay =3D=3D 0) { - return EFI_SUCCESS; - } - - NumberOfTicks =3D DivU64x32Remainder (Delay, (UINT32) Metronome->TickPer= iod, &Remainder); - if (Remainder !=3D 0) { - NumberOfTicks +=3D 1; - } - NumberOfTicks +=3D 1; - - while (NumberOfTicks) { - Metronome->WaitForTick (Metronome, 1); - - Status =3D This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -=3D 1; - } - - return EFI_TIMEOUT; -} - -EFI_STATUS -PciRbPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - - PCI_TRACE ("PciRbPollIo()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - Metronome =3D METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Result =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - // No matter what, always do a single poll. - Status =3D This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - if (Delay =3D=3D 0) { - return EFI_SUCCESS; - } - - NumberOfTicks =3D DivU64x32Remainder (Delay, (UINT32) Metronome->TickPer= iod, &Remainder); - if (Remainder !=3D 0) { - NumberOfTicks +=3D 1; - } - NumberOfTicks +=3D 1; - - while (NumberOfTicks) { - Metronome->WaitForTick (Metronome, 1); - - Status =3D This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -=3D 1; - } - - return EFI_TIMEOUT; -} - -EFI_STATUS -PciRbMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - - PCI_TRACE ("PciRbMemRead()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo =3D CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM3= 2_SIZE))) && - ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM6= 4_SIZE)))) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address= , Count, Buffer); -} - -EFI_STATUS -PciRbMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - - PCI_TRACE ("PciRbMemWrite()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo =3D CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM3= 2_SIZE))) && - ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM6= 4_SIZE)))) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Addres= s, Count, Buffer); -} - -EFI_STATUS -PciRbIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_TRACE ("PciRbIoRead()"); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // IO currently unsupported - return EFI_INVALID_PARAMETER; -} - -EFI_STATUS -PciRbIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_TRACE ("PciRbIoWrite()"); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // IO currently unsupported - return EFI_INVALID_PARAMETER; -} - -EFI_STATUS -PciRbPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - UINT32 Offset; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - - EfiPciAddress =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAd= dress; - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo =3D CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) { - Offset =3D EfiPciAddress->ExtendedRegister; - } else { - Offset =3D EfiPciAddress->Register; - } - - // The UEFI PCI enumerator scans for devices at all possible addresses, - // and ignores some PCI rules - this results in some hardware being - // detected multiple times. We work around this by faking absent - // devices - if ((EfiPciAddress->Bus =3D=3D 0) && ((EfiPciAddress->Device !=3D 0) || = (EfiPciAddress->Function !=3D 0))) { - *((UINT32 *)Buffer) =3D 0xffffffff; - return EFI_SUCCESS; - } - if ((EfiPciAddress->Bus =3D=3D 1) && ((EfiPciAddress->Device !=3D 0) || = (EfiPciAddress->Function !=3D 0))) { - *((UINT32 *)Buffer) =3D 0xffffffff; - return EFI_SUCCESS; - } - - // Work around incorrect class ID in the root bridge - if ((EfiPciAddress->Bus =3D=3D 0) && (EfiPciAddress->Device =3D=3D 0) &&= (EfiPciAddress->Function =3D=3D 0) && (Offset =3D=3D 8)) { - *((UINT32 *)Buffer) =3D 0x06040001; - return EFI_SUCCESS; - } - - Address =3D PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) | - (EfiPciAddress->Device << 15) | - (EfiPciAddress->Function << 12) | Offset); - - if ((Address < PCI_ECAM_BASE) || (Address > PCI_ECAM_BASE + PCI_ECAM_SIZ= E)) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address= , Count, Buffer); -} - -EFI_STATUS -PciRbPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - UINT32 Offset; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - - EfiPciAddress =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAd= dress; - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo =3D CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) - Offset =3D EfiPciAddress->ExtendedRegister; - else - Offset =3D EfiPciAddress->Register; - - Address =3D PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) | - (EfiPciAddress->Device << 15) | - (EfiPciAddress->Function << 12) | Offset); - - if (Address < PCI_ECAM_BASE || Address > PCI_ECAM_BASE + PCI_ECAM_SIZE) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Addres= s, Count, Buffer); -} - -EFI_STATUS -PciRbCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ) -{ - EFI_STATUS Status; - BOOLEAN Direction; - UINTN Stride; - UINTN Index; - UINT64 Result; - - PCI_TRACE ("PciRbCopyMem()"); - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - if (DestAddress =3D=3D SrcAddress) { - return EFI_SUCCESS; - } - - Stride =3D (UINTN)(1 << Width); - - Direction =3D TRUE; - if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * S= tride))) { - Direction =3D FALSE; - SrcAddress =3D SrcAddress + (Count-1) * Stride; - DestAddress =3D DestAddress + (Count-1) * Stride; - } - - for (Index =3D 0; Index < Count; Index++) { - Status =3D PciRbMemRead ( - This, - Width, - SrcAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - Status =3D PciRbMemWrite ( - This, - Width, - DestAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - if (Direction) { - SrcAddress +=3D Stride; - DestAddress +=3D Stride; - } else { - SrcAddress -=3D Stride; - DestAddress -=3D Stride; - } - } - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ) -{ - DMA_MAP_OPERATION DmaOperation; - - PCI_TRACE ("PciRbMap()"); - - if (Operation =3D=3D EfiPciOperationBusMasterRead || - Operation =3D=3D EfiPciOperationBusMasterRead64) { - DmaOperation =3D MapOperationBusMasterRead; - } else if (Operation =3D=3D EfiPciOperationBusMasterWrite || - Operation =3D=3D EfiPciOperationBusMasterWrite64) { - DmaOperation =3D MapOperationBusMasterWrite; - } else if (Operation =3D=3D EfiPciOperationBusMasterCommonBuffer || - Operation =3D=3D EfiPciOperationBusMasterCommonBuffer64) { - DmaOperation =3D MapOperationBusMasterCommonBuffer; - } else { - return EFI_INVALID_PARAMETER; - } - return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, = Mapping); -} - -EFI_STATUS -PciRbUnMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ) -{ - PCI_TRACE ("PciRbUnMap()"); - return DmaUnmap (Mapping); -} - -EFI_STATUS -PciRbAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - IN OUT VOID **HostAddress, - IN UINT64 Attributes - ) -{ - PCI_TRACE ("PciRbAllocateBuffer()"); - - if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { - return EFI_UNSUPPORTED; - } - - return DmaAllocateBuffer (MemoryType, Pages, HostAddress); -} - -EFI_STATUS -PciRbFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ) -{ - PCI_TRACE ("PciRbFreeBuffer()"); - return DmaFreeBuffer (Pages, HostAddress); -} - -EFI_STATUS -PciRbFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ) -{ - PCI_TRACE ("PciRbFlush()"); - - //TODO: Not supported yet - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCI_TRACE ("PciRbSetAttributes()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - if (Attributes) { - if ((Attributes & (~(RootBridgeInstance->Supports))) !=3D 0) { - return EFI_UNSUPPORTED; - } - } - - //TODO: Cannot allowed to change attributes - if (Attributes & ~RootBridgeInstance->Attributes) { - return EFI_UNSUPPORTED; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCI_TRACE ("PciRbGetAttributes()"); - - RootBridgeInstance =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - if (Attributes =3D=3D NULL && Supported =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // Set the return value for Supported and Attributes - if (Supported) { - *Supported =3D RootBridgeInstance->Supports; - } - - if (Attributes) { - *Attributes =3D RootBridgeInstance->Attributes; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; - UINTN Index; - - PCI_TRACE ("PciRbConfiguration()"); - - RootBridge =3D INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - for (Index =3D 0; Index < ResTypeMax; Index++) { - //if (ResAlloc[Index].Length !=3D 0) =3D> Resource allocated - if (RootBridge->ResAlloc[Index].Length !=3D 0) { - Configuration.SpaceDesp[Index].AddrRangeMin =3D RootBridge->ResAlloc= [Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax =3D RootBridge->ResAlloc= [Index].Base + RootBridge->ResAlloc[Index].Length - 1; - Configuration.SpaceDesp[Index].AddrLen =3D RootBridge->ResAlloc= [Index].Length; - } - } - - // Set up Configuration for the bus - Configuration.SpaceDesp[Index].AddrRangeMin =3D RootBridge->BusStart; - Configuration.SpaceDesp[Index].AddrLen =3D RootBridge->BusLength; - - *Resources =3D &Configuration; - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbConstructor ( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridge, - IN UINT32 PciAcpiUid, - IN UINT64 MemAllocAttributes - ) -{ - PCI_ROOT_BRIDGE_INSTANCE* RootBridge; - EFI_STATUS Status; - - PCI_TRACE ("PciRbConstructor()"); - - // Allocate Memory for the Instance from a Template - RootBridge =3D AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE)); - if (RootBridge =3D=3D NULL) { - PCI_TRACE ("PciRbConstructor(): ERROR: Out of Resources"); - return EFI_OUT_OF_RESOURCES; - } - RootBridge->Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; - CopyMem (&(RootBridge->DevicePath), &gDevicePathTemplate, sizeof (EFI_PC= I_ROOT_BRIDGE_DEVICE_PATH)); - CopyMem (&(RootBridge->Io), &gIoTemplate, sizeof (EFI_PCI_ROOT_BRIDGE_IO= _PROTOCOL)); - - // Set Parent Handle - RootBridge->Io.ParentHandle =3D HostBridge->Handle; - - // Attach the Root Bridge to the PCI Host Bridge Instance - RootBridge->HostBridge =3D HostBridge; - - // Set Device Path for this Root Bridge - RootBridge->DevicePath.Acpi.UID =3D PciAcpiUid; - - RootBridge->BusStart =3D FixedPcdGet32 (PcdPciBusMin); - RootBridge->BusLength =3D FixedPcdGet32 (PcdPciBusMax) - FixedPcdGet32 (= PcdPciBusMin) + 1; - - // PCI Attributes - RootBridge->Supports =3D 0; - RootBridge->Attributes =3D 0; - - // Install Protocol Instances. It will also generate a device handle for= the PCI Root Bridge - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &RootBridge->Handle, - &gEfiDevicePathProtocolGuid, &RootBridge->DevicePath, - &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io, - NULL - ); - ASSERT (RootBridge->Signature =3D=3D PCI_ROOT_BRIDGE_SIGNATURE); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciRbConstructor(): ERROR: Fail to install Protocol Interf= aces"); - FreePool (RootBridge); - return EFI_DEVICE_ERROR; - } - - HostBridge->RootBridge =3D RootBridge; - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbDestructor ( - IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge - ) -{ - EFI_STATUS Status; - - Status =3D gBS->UninstallMultipleProtocolInterfaces ( - RootBridge->Handle, - &gEfiDevicePathProtocolGuid, &RootBridge->DevicePa= th, - &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io, - NULL - ); - - FreePool (RootBridge); - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3= .c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c deleted file mode 100644 index 57e9e9df54a9..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ /dev/null @@ -1,170 +0,0 @@ -/** @file -* Initialize the XPress-RICH3 PCIe Root complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#include "PciHostBridge.h" - -#include - -#include "ArmPlatform.h" - -EFI_CPU_ARCH_PROTOCOL *mCpu; - -#define PCI_BRIDGE_REVISION_ID 1 -#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf) ((Class << 16) | (Su= bClass << 8) | ProgIf) -#define PLDA_BRIDGE_CCR CLASS_CODE_REGISTER(= PCI_CLASS_BRIDGE, \ - = PCI_CLASS_BRIDGE_P2P, \ - = PCI_IF_BRIDGE_P2P) - -STATIC -VOID -SetTranslationAddressEntry ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo, - IN UINTN Entry, - IN UINT64 SourceAddress, - IN UINT64 TranslatedAddress, - IN UINT64 TranslationSize, - IN UINT64 TranslationParameter - ) -{ - UINTN Log2Size =3D HighBitSet64 (TranslationSize); - - // Ensure the size is a power of two. Restriction form the AXI Translati= on logic - // Othwerwise we increase the translation size - if (TranslationSize !=3D (1ULL << Log2Size)) { - DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been = increased to " - "be a power of two for the AXI translation table.\= n", - TranslationSize, SourceAddress)); - Log2Size++; - } - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE, - (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1); - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32); - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)Translated= Address); - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >= > 32); - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter); -} - -EFI_STATUS -HWPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ) -{ - UINT32 Value; - UINT32 Index; - UINTN TranslationTable; - - PCI_TRACE ("VExpressPciRbInit()"); - - PCI_TRACE ("PCIe Setting up Address Translation"); - - // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_= WIN_SUPPORT_IO32 | - PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_M= EM64); - - // Setup the PCI Configuration Registers - // Offset 0a: SubClass 04 PCI-PCI Bridge - // Offset 0b: BaseClass 06 Bridge Device - // The Class Code register is a 24 bit and can be configured by setting = up the PCIE_PCI_IDS - // Refer [1] Chapter 13 - PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((P= LDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); - - // - // PCIE Window 0 -> AXI4 Master 0 Address Translations - // - TranslationTable =3D VEXPRESS_ATR_PCIE_WIN0; - - // MSI Support - SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_= BASE, ARM_JUNO_GIV2M_MSI_BASE, - ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE); - TranslationTable +=3D PCI_ATR_ENTRY_SIZE; - - // System Memory Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystem= MemoryBase), PcdGet64 (PcdSystemMemoryBase), - PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY); - TranslationTable +=3D PCI_ATR_ENTRY_SIZE; - SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYST= EM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, - ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); - - // - // AXI4 Slave 1 -> PCIE Window 0 Address Translations - // - TranslationTable =3D VEXPRESS_ATR_AXI4_SLV1; - - // PCI ECAM Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_= ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); - TranslationTable +=3D PCI_ATR_ENTRY_SIZE; - - // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_= BASE address to the PIO base address of 0 - // AKA, PIO addresses used by endpoints are generally in the range of 0-= 64K. - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI= _IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); - TranslationTable +=3D PCI_ATR_ENTRY_SIZE; - - // PCI MEM32 Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI= _MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); - TranslationTable +=3D PCI_ATR_ENTRY_SIZE; - - // PCI MEM64 Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI= _MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); - - // Add credits - PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818); - PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1); - - // Allow ECRC - PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006); - - // Reset controller - PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_R= EL); - - // Wait for reset - for (Index =3D 0; Index < 1000; Index++) { - gBS->Stall (1000); - PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value); - if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) =3D=3D PCIE_CONTROL_RS= T_STS_RCPHYPLL_OUT) { - break; - } - } - - // Check for reset - if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) { - DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value)= ); - return EFI_NOT_READY; - } - - gBS->Stall (1000); - PCI_TRACE ("Checking link Status..."); - - // Wait for Link Up - for (Index =3D 0; Index < 1000; Index++) { - gBS->Stall (1000); - PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value); - if (Value & LINK_UP) { - break; - } - } - - // Check for link up - if (!(Value & LINK_UP)) { - DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value)); - return EFI_NOT_READY; - } - - PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx); - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3= .h b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h deleted file mode 100644 index a0c11a70567d..000000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @file -* Header containing the Xpress-RICH3 PCIe Root Complex specific values -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the B= SD License -* which accompanies this distribution. The full text of the license may = be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -* -**/ - -#ifndef __XPRESS_RICH3_H__ -#define __XPRESS_RICH3_H__ - -#include -#include - -#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAdd= ress) -#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) -#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoBase) -#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) -#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) -#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) -#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) -#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) - -/* - * Bridge Internal Registers - */ - -// PCIe Available Credit Settings -#define PCIE_VC_CRED 0x090 -// PCIe PCI Standard Configuration Identification Settings registers -#define PCIE_PCI_IDS 0x098 -#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4 -// PCIe Specific 2 Capabilities Settings -#define PCIE_PEX_SPC2 0x0d8 -// PCIe Windows Settings register -#define PCIE_BAR_WIN 0x0FC -// Local Processor Interrupt Mask -#define PCIE_IMASK_LOCAL 0x180 - -#define PCIE_BAR_WIN_SUPPORT_IO BIT0 -#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1 -#define PCIE_BAR_WIN_SUPPORT_MEM BIT2 -#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3 - -#define PCIE_INT_MSI BIT28 -#define PCIE_INT_A BIT24 -#define PCIE_INT_B BIT25 -#define PCIE_INT_C BIT26 -#define PCIE_INT_D BIT27 -#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\ - PCIE_INT_C | PCIE_INT_D) - -/* - * PCIe Control Registers - */ -#define PCIE_CONTROL_RST_CTL 0x1004 -#define PCIE_CONTROL_RST_STS 0x1008 - -/* - * PCI Express Address Translation registers - * All are offsets from PcdPcieControlBaseAddress - */ -#define VEXPRESS_ATR_PCIE_WIN0 0x600 -#define VEXPRESS_ATR_AXI4_SLV0 0x800 -#define VEXPRESS_ATR_AXI4_SLV1 0x820 - -#define PCI_ATR_ENTRY_SIZE 0x20 -#define PCI_ATR_SRC_ADDR_LOW_SIZE 0 -#define PCI_ATR_SRC_ADDR_HI 0x4 -#define PCI_ATR_TRSL_ADDR_LOW 0x8 -#define PCI_ATR_TRSL_ADDR_HI 0xc -#define PCI_ATR_TRSL_PARAM 0x10 - -#define PCI_ATR_TRSLID_AXIDEVICE 0x420004 -#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004 -#define PCI_ATR_TRSLID_PCIE_CONF 0x000001 -#define PCI_ATR_TRSLID_PCIE_IO 0x020000 -#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000 - -#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1) -#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0) -#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | = PCIE_CONTROL_RST_CTL_PHY_REL) - -#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2) -#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1) -#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0) -#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | P= CIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST) - -#define VEXPRESS_BASIC_STATUS 0x18 -#define LINK_UP 0xff - -/* - * Initialize Versatile Express PCIe Host Bridge - */ -EFI_STATUS -VExpressPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ); - -// Does not support neither EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM -// nor EFI_PCI_HOST_BRIDGE_MEM64_DECODE -#define PCI_MEMORY_ALLOCATION_ATTRIBUTES 0 - -#endif --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 10:23:57 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491400719693959.0610887363724; Wed, 5 Apr 2017 06:58:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8E7D720D77DAD; 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charset="utf-8" Having a three way conditional with callbacks would make sense if the callbacks weren't (a) identical and (b) didn't return TRUE all the time. So get rid of the kludge. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Ryan Harkin Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 37 +----------= --------- 1 file changed, 1 insertion(+), 36 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/Ar= mPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c index f7e33961b4e7..da93eb582909 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -400,34 +400,6 @@ OnEndOfDxe ( } } =20 -STATIC -BOOLEAN -AcpiTableJunoR0Check ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - return TRUE; -} - -STATIC -BOOLEAN -AcpiTableJunoR1Check ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - return TRUE; -} - -STATIC -BOOLEAN -AcpiTableJunoR2Check ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - return TRUE; -} - - EFI_STATUS EFIAPI ArmJunoEntryPoint ( @@ -517,14 +489,7 @@ ArmJunoEntryPoint ( // // Try to install the ACPI Tables // - if (JunoRevision =3D=3D JUNO_REVISION_R0) { - Status =3D LocateAndInstallAcpiFromFvConditional (&mJunoAcpiTableFile,= AcpiTableJunoR0Check); - } else if (JunoRevision =3D=3D JUNO_REVISION_R1) { - Status =3D LocateAndInstallAcpiFromFvConditional (&mJunoAcpiTableFile,= AcpiTableJunoR1Check); - } else if (JunoRevision =3D=3D JUNO_REVISION_R2) { - Status =3D LocateAndInstallAcpiFromFvConditional (&mJunoAcpiTableFile,= AcpiTableJunoR2Check); - } - + Status =3D LocateAndInstallAcpiFromFv (&mJunoAcpiTableFile); ASSERT_EFI_ERROR (Status); =20 // --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel