From nobody Sun May 5 14:45:43 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491007956638294.2632783034352; Fri, 31 Mar 2017 17:52:36 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3B6782063E051; Fri, 31 Mar 2017 17:52:32 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DB7121DFA7A8 for ; Fri, 31 Mar 2017 17:52:31 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 17:52:32 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2017 17:52:31 -0700 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491007952; x=1522543952; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=pzSxu0Cv2U0a2qDHay8ggRUAG+suwEAh/sPiExULF+Y=; b=liw/+mke5XSI1gZ7ZB1zx8QCio1IM8QAJ8pGA4aatQECpU311NouZMkI vxbP6VGjtsQoHkpVYLSQ+32hUtNZkA==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,254,1486454400"; d="scan'208";a="840609853" From: Jeff Fan To: edk2-devel@lists.01.org Date: Sat, 1 Apr 2017 08:52:26 +0800 Message-Id: <20170401005228.26896-2-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170401005228.26896-1-jeff.fan@intel.com> References: <20170401005228.26896-1-jeff.fan@intel.com> Subject: [edk2] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" v2: Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement. Cc: Jiewen Yao Cc: Michael Kinney Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan Reviewed-by: Jiewen.yao@intel.com --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 ++++++++++++++++----------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +++- 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index d061482..47cba10 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -108,6 +108,12 @@ UINT64 mAddressEncMask =3D 0; // SPIN_LOCK *mConfigSmmCodeAccessCheckLock =3D NULL; =20 +// +// Saved SMM ranges information +// +EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; +UINTN mSmmCpuSmramRangeCount; + /** Initialize IDT to setup exception handlers for SMM. =20 @@ -971,8 +977,6 @@ FindSmramInfo ( UINTN Size; EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; - EFI_SMRAM_DESCRIPTOR *SmramRanges; - UINTN SmramRangeCount; UINTN Index; UINT64 MaxSize; BOOLEAN Found; @@ -990,31 +994,31 @@ FindSmramInfo ( Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); =20 - SmramRanges =3D (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); - ASSERT (SmramRanges !=3D NULL); + mSmmCpuSmramRanges =3D (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); + ASSERT (mSmmCpuSmramRanges !=3D NULL); =20 - Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges); + Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRan= ges); ASSERT_EFI_ERROR (Status); =20 - SmramRangeCount =3D Size / sizeof (EFI_SMRAM_DESCRIPTOR); + mSmmCpuSmramRangeCount =3D Size / sizeof (EFI_SMRAM_DESCRIPTOR); =20 // // Find the largest SMRAM range between 1MB and 4GB that is at least 256= K - 4K in size // CurrentSmramRange =3D NULL; - for (Index =3D 0, MaxSize =3D SIZE_256KB - EFI_PAGE_SIZE; Index < SmramR= angeCount; Index++) { + for (Index =3D 0, MaxSize =3D SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCp= uSmramRangeCount; Index++) { // // Skip any SMRAM region that is already allocated, needs testing, or = needs ECC initialization // - if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTI= NG | EFI_NEEDS_ECC_INITIALIZATION)) !=3D 0) { + if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEED= S_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) !=3D 0) { continue; } =20 - if (SmramRanges[Index].CpuStart >=3D BASE_1MB) { - if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) = <=3D BASE_4GB) { - if (SmramRanges[Index].PhysicalSize >=3D MaxSize) { - MaxSize =3D SmramRanges[Index].PhysicalSize; - CurrentSmramRange =3D &SmramRanges[Index]; + if (mSmmCpuSmramRanges[Index].CpuStart >=3D BASE_1MB) { + if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].= PhysicalSize) <=3D SMRR_MAX_ADDRESS) { + if (mSmmCpuSmramRanges[Index].PhysicalSize >=3D MaxSize) { + MaxSize =3D mSmmCpuSmramRanges[Index].PhysicalSize; + CurrentSmramRange =3D &mSmmCpuSmramRanges[Index]; } } } @@ -1027,19 +1031,19 @@ FindSmramInfo ( =20 do { Found =3D FALSE; - for (Index =3D 0; Index < SmramRangeCount; Index++) { - if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase =3D=3D (Smr= amRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) { - *SmrrBase =3D (UINT32)SmramRanges[Index].CpuStart; - *SmrrSize =3D (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize= ); + for (Index =3D 0; Index < mSmmCpuSmramRangeCount; Index++) { + if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase && + *SmrrBase =3D=3D (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSm= ramRanges[Index].PhysicalSize)) { + *SmrrBase =3D (UINT32)mSmmCpuSmramRanges[Index].CpuStart; + *SmrrSize =3D (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].Physi= calSize); Found =3D TRUE; - } else if ((*SmrrBase + *SmrrSize) =3D=3D SmramRanges[Index].CpuStar= t && SmramRanges[Index].PhysicalSize > 0) { - *SmrrSize =3D (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize= ); + } else if ((*SmrrBase + *SmrrSize) =3D=3D mSmmCpuSmramRanges[Index].= CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) { + *SmrrSize =3D (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].Physi= calSize); Found =3D TRUE; } } } while (Found); =20 - FreePool (SmramRanges); DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *Sm= rrSize)); } =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 71af2f1..fc9b06e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -105,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITH= ER EXPRESS OR IMPLIED. #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull =20 +#define SMRR_MAX_ADDRESS BASE_4GB + typedef enum { PageNone, Page4K, @@ -415,6 +417,8 @@ extern UINTN mSemaphoreSi= ze; extern SPIN_LOCK *mPFLock; extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; extern SPIN_LOCK *mMemoryMappedLock; +extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; +extern UINTN mSmmCpuSmramRangeCount; =20 // // Copy of the PcdPteMemoryEncryptionAddressOrMask --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 14:45:43 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491007958306678.2692648352611; Fri, 31 Mar 2017 17:52:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6A9AB2063E05A; Fri, 31 Mar 2017 17:52:34 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90E242063E05A for ; Fri, 31 Mar 2017 17:52:32 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 17:52:33 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2017 17:52:32 -0700 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491007953; x=1522543953; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=kxBZJc3lMMrMEIbtqTPww/dXzqnJ4iTXDHpUuFaal9E=; b=J/TxqOn5a1Mmj8acaSes1hGxMTG/rZAAsaxG8yTGjX7u3LeAtJczsnp5 s/yU+xB3axstwRPUCqqCt/9bfvFMKw==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,254,1486454400"; d="scan'208";a="840609865" From: Jeff Fan To: edk2-devel@lists.01.org Date: Sat, 1 Apr 2017 08:52:27 +0800 Message-Id: <20170401005228.26896-3-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170401005228.26896-1-jeff.fan@intel.com> References: <20170401005228.26896-1-jeff.fan@intel.com> Subject: [edk2] [PATCH v2 2/3] UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Internal function IsInSmmRanges() is added t check SMM range by saved SMM r= anges beside by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. Cc: Jiewen Yao Cc: Michael Kinney Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan Reviewed-by: Jiewen.yao@intel.com --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 36 +++++++++++++++++++++++++++++-= ---- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index 1b84e2c..7125aec 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -1,7 +1,7 @@ /** @file Enable SMM profile. =20 -Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -247,6 +247,33 @@ DebugExceptionHandler ( } =20 /** + Check if the input address is in SMM ranges. + + @param[in] Address The input address. + + @retval TRUE The input address is in SMM. + @retval FALSE The input address is not in SMM. +**/ +BOOLEAN +IsInSmmRanges ( + IN EFI_PHYSICAL_ADDRESS Address + ) +{ + UINTN Index; + + if ((Address < mCpuHotPlugData.SmrrBase) || (Address >=3D mCpuHotPlugDat= a.SmrrBase + mCpuHotPlugData.SmrrSize)) { + return TRUE; + } + for (Index =3D 0; Index < mSmmCpuSmramRangeCount; Index++) { + if (Address >=3D mSmmCpuSmramRanges[Index].CpuStart && + Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[= Index].PhysicalSize) { + return TRUE; + } + } + return FALSE; +} + +/** Check if the memory address will be mapped by 4KB-page. =20 @param Address The address of Memory. @@ -261,7 +288,6 @@ IsAddressValid ( { UINTN Index; =20 - *Nx =3D FALSE; if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { // // Check configuration @@ -276,9 +302,9 @@ IsAddressValid ( return FALSE; =20 } else { - if ((Address < mCpuHotPlugData.SmrrBase) || - (Address >=3D mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)= ) { - *Nx =3D TRUE; + *Nx =3D TRUE; + if (IsInSmmRanges (Address)) { + *Nx =3D FALSE; } return TRUE; } --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 14:45:43 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1491007960593549.2480506567051; Fri, 31 Mar 2017 17:52:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AC0B12063E06A; Fri, 31 Mar 2017 17:52:37 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B328B2063E069 for ; Fri, 31 Mar 2017 17:52:35 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 17:52:36 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by FMSMGA003.fm.intel.com with ESMTP; 31 Mar 2017 17:52:33 -0700 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491007956; x=1522543956; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ECfTwZCA1HcBBHCtFAfd17+FqgLj5fIbCwKEjNKwwEw=; b=Zxbdj2LPCWjSpMf8SwiaZrTUh3F+Gy1Xl8MTUwWP2Pi8yQy9HvNWVk6d Ezlbz8mB1ifVqrCLOhQqxTPNoU0ZRQ==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,254,1486454400"; d="scan'208";a="840609876" From: Jeff Fan To: edk2-devel@lists.01.org Date: Sat, 1 Apr 2017 08:52:28 +0800 Message-Id: <20170401005228.26896-4-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170401005228.26896-1-jeff.fan@intel.com> References: <20170401005228.26896-1-jeff.fan@intel.com> Subject: [edk2] [PATCH v2 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" SmmProfile feature required to protect all SMM ranges by structure mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges into mProtectionMemRangeTemplate besides the range specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. Cc: Jiewen Yao Cc: Michael Kinney Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan Reviewed-by: Jiewen.yao@intel.com --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 42 +++++++++++++++++++++++++++++-= ---- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index 7125aec..2713b19 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -83,6 +83,12 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = =3D { {{0x00000000, 0x00000000},TRUE,TRUE}, =20 // + // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.= SmrrSiz (to be fixed in runtime). + // It is always present and instruction fetches are allowed. + // {{0x00000000, 0x00000000},TRUE,FALSE}, + // + + // // Future extended range could be added here. // =20 @@ -360,7 +366,7 @@ InitProtectedMemRange ( { UINTN Index; UINTN NumberOfDescriptors; - UINTN NumberOfMmioDescriptors; + UINTN NumberOfAddedDescriptors; UINTN NumberOfProtectRange; UINTN NumberOfSpliteRange; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; @@ -373,7 +379,7 @@ InitProtectedMemRange ( UINT64 Low4KBPageSize; =20 NumberOfDescriptors =3D 0; - NumberOfMmioDescriptors =3D 0; + NumberOfAddedDescriptors =3D mSmmCpuSmramRangeCount; NumberOfSpliteRange =3D 0; MemorySpaceMap =3D NULL; =20 @@ -386,12 +392,12 @@ InitProtectedMemRange ( ); for (Index =3D 0; Index < NumberOfDescriptors; Index++) { if (MemorySpaceMap[Index].GcdMemoryType =3D=3D EfiGcdMemoryTypeMemoryM= appedIo) { - NumberOfMmioDescriptors++; + NumberOfAddedDescriptors++; } } =20 - if (NumberOfMmioDescriptors !=3D 0) { - TotalSize =3D NumberOfMmioDescriptors * sizeof (MEMORY_PROTECTION_RANG= E) + sizeof (mProtectionMemRangeTemplate); + if (NumberOfAddedDescriptors !=3D 0) { + TotalSize =3D NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RAN= GE) + sizeof (mProtectionMemRangeTemplate); mProtectionMemRange =3D (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (= TotalSize); ASSERT (mProtectionMemRange !=3D NULL); mProtectionMemRangeCount =3D TotalSize / sizeof (MEMORY_PROTECTION_RAN= GE); @@ -409,9 +415,27 @@ InitProtectedMemRange ( ASSERT (mSplitMemRange !=3D NULL); =20 // + // Create SMM ranges which are set to present and execution-enable. + // + NumberOfProtectRange =3D sizeof (mProtectionMemRangeTemplate) / sizeof= (MEMORY_PROTECTION_RANGE); + for (Index =3D 0; Index < mSmmCpuSmramRangeCount; Index++) { + if (mSmmCpuSmramRanges[Index].CpuStart >=3D mProtectionMemRange[0].R= ange.Base && + mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].P= hysicalSize < mProtectionMemRange[0].Range.Top) { + // + // If the address have been already covered by mCpuHotPlugData.Smr= rBase/mCpuHotPlugData.SmrrSiz + // + break; + } + mProtectionMemRange[NumberOfProtectRange].Range.Base =3D mSmmCpuSmra= mRanges[Index].CpuStart; + mProtectionMemRange[NumberOfProtectRange].Range.Top =3D mSmmCpuSmra= mRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize; + mProtectionMemRange[NumberOfProtectRange].Present =3D TRUE; + mProtectionMemRange[NumberOfProtectRange].Nx =3D FALSE; + NumberOfProtectRange++; + } + + // // Create MMIO ranges which are set to present and execution-disable. // - NumberOfProtectRange =3D sizeof (mProtectionMemRangeTemplate) / siz= eof (MEMORY_PROTECTION_RANGE); for (Index =3D 0; Index < NumberOfDescriptors; Index++) { if (MemorySpaceMap[Index].GcdMemoryType !=3D EfiGcdMemoryTypeMemoryM= appedIo) { continue; @@ -422,6 +446,12 @@ InitProtectedMemRange ( mProtectionMemRange[NumberOfProtectRange].Nx =3D TRUE; NumberOfProtectRange++; } + + // + // Check and updated actual protected memory ranges count + // + ASSERT (NumberOfProtectRange <=3D mProtectionMemRangeCount); + mProtectionMemRangeCount =3D NumberOfProtectRange; } =20 // --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel