From nobody Sat Nov 2 12:27:27 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1490969772894487.9411673442588; Fri, 31 Mar 2017 07:16:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DE6872008031F; Fri, 31 Mar 2017 07:16:08 -0700 (PDT) Received: from mail-wr0-x22e.google.com (mail-wr0-x22e.google.com [IPv6:2a00:1450:400c:c0c::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ECCD421BC6A24 for ; Fri, 31 Mar 2017 07:16:06 -0700 (PDT) Received: by mail-wr0-x22e.google.com with SMTP id k6so102859620wre.2 for ; Fri, 31 Mar 2017 07:16:06 -0700 (PDT) Received: from localhost.localdomain ([160.171.180.74]) by smtp.gmail.com with ESMTPSA id h187sm3057561wma.32.2017.03.31.07.16.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Mar 2017 07:16:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1x0lem+KTfH20KoSOFjrKSLpRYqd5pcT7uxFnAUAc+0=; b=hCzvQvNNMxfixcoEiXole5oLBuYAwkJ0cUbpSZfsCvGQvlWJtCRlzzOe0JLuF964iR JM/7Ol878vo5cpn7d72FPvIpmlyojR0YI6ic/APR7Fa2iLt0au+YboUoScCitkKIIo7V 8a9iz3oqpPnsvQHpOPRBQ5mz1rBDB6+Pk8yg8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1x0lem+KTfH20KoSOFjrKSLpRYqd5pcT7uxFnAUAc+0=; b=Uh0UhDERmAjtAwCOfIwThHQdmKBtf5WgEMTBOqjvSVbQ4YLw+KUQbRwI/MGOXkoa8U XNWdOzONqdlqsSx5pnyTHhQEceBSreiWffFeeC7H/kAtxmcN0O794lBD4au3lbmDcB0A IOQV5RyIwh6W5eRzSar0MSb9MPCQeCGM9v6k7VzdsSoZGNxI6WCuIM6virWy2JWtYpZL ZvI2UbFxOg8XvxKM8+YWv5vbdAJv7Omo1FCeHz/b+oUjMHmqMJYl102aOm8yUL3dgatD oqPpS2VtzfChmAkK6EycOIShehz0vmW53OBEIcB6BFA7wgvn9+gfftHHmK1Molmp0ei0 ztAg== X-Gm-Message-State: AFeK/H2G9iHqB+WzznI1B9NBDsMbmggwEo0/8SltoyUwdIrhSTwioxvV6D9HeUSdw2CRqKsM X-Received: by 10.223.136.125 with SMTP id e58mr3347652wre.14.1490969764671; Fri, 31 Mar 2017 07:16:04 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org Date: Fri, 31 Mar 2017 15:15:43 +0100 Message-Id: <20170331141547.20987-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170331141547.20987-1-ard.biesheuvel@linaro.org> References: <20170331141547.20987-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 05/13] Platforms/TC2: move to new DtPlatformDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Replace the slightly overengineered FdtPlatformDxe driver with the new and simple DtPlatformDxe driver, which simply exposes a single builtin device tree binary to the OS. Note that this driver is configurable, i.e., it allows ACPI to be selected instead of device tree, in which case AcpiPlatformDxe is allowed to run. Note that this means we have to move the reference to FdtPlatformDxe.inf from the shared .DSC to the individual .DSCs for Juno and FVP that will keep using it for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/ARM/Juno/ArmJuno.dsc | 8 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 17 +- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 13 +- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 8 + Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 8 - Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi | 442 +++++++++= ++++ Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb | Bin 0 -> 1907= 0 bytes Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts | 659 +++++++++= +++++++++++ 8 files changed, 1133 insertions(+), 22 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 1f56643ae996..71dc5463a84f 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -336,6 +336,14 @@ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf } =20 + # + # FDT installation + # + EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } + [Components.AARCH64] # # EBC diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/AR= M/VExpress/ArmVExpress-CTA15-A7.dsc index 55640837ba7c..43856fe5c3ae 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -55,6 +55,8 @@ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf =20 + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf + [BuildOptions] !ifdef ARM_BIGLITTLE_TC2 *_*_ARM_ARCHCC_FLAGS =3D -DARM_BIGLITTLE_TC2=3D1 @@ -173,11 +175,6 @@ gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|400000 =20 # - # Define the device path to the FDT for the platform - # - gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"VenHw(E7223039-5836-41E1-B54= 2-D7EC736C5E59)/ca15a7" - - # # ARM Architectural Timer Frequency # !ifdef ARM_BIGLITTLE_TC2 @@ -269,7 +266,15 @@ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf =20 - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + } + + # + # FDT installation + # + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf =20 # # Bds diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf b/Platforms/AR= M/VExpress/ArmVExpress-CTA15-A7.fdf index 1903389c8edd..8bdde76a2ad5 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf @@ -181,14 +181,11 @@ FvNameGuid =3D 73dcb643-3862-4904-9076-a94af1= 890243 # # FDT installation # - # The UEFI driver is at the end of the list of the driver to be dispatch= ed - # after the device drivers (eg: Ethernet) to ensure we have support for = them. - INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf - - # Example to add a Device Tree to the Firmware Volume - #FILE FREEFORM =3D PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A= 7x3) { - # SECTION RAW =3D ArmPlatformPkg/ArmVExpressPkg/Fdts/vexpress-v2p-ca15_= a7.dtb - #} + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + FILE FREEFORM =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW =3D OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/vexp= ress-v2p-ca15_a7.dtb + } =20 [FV.FVMAIN_COMPACT] FvBaseAddress =3D 0xB0000000 diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms= /ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1b3c770da03f..e6778aafe8c6 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -315,3 +315,11 @@ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf } + + # + # FDT installation + # + EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VEx= press/ArmVExpress.dsc.inc index 9dfe2ac9e440..8c4de54c8875 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -491,14 +491,6 @@ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf =20 # - # FDT installation - # - EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { - - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } - - # # UEFI application (Shell Embedded Boot Loader) # ShellPkg/Application/Shell/Shell.inf { diff --git a/Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi b/Plat= forms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000000..3086efacd00e --- /dev/null +++ b/Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi @@ -0,0 +1,442 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ + + motherboard { + model =3D "V2M-P1"; + arm,hbi =3D <0x190>; + arm,vexpress,site =3D <0>; + arm,v2m-memory-map =3D "rs1"; + compatible =3D "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells =3D <2>; /* SMB chipselect number and offset */ + #size-cells =3D <1>; + #interrupt-cells =3D <1>; + ranges; + + flash@0,00000000 { + compatible =3D "arm,vexpress-flash", "cfi-flash"; + reg =3D <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width =3D <4>; + }; + + psram@1,00000000 { + compatible =3D "arm,vexpress-psram", "mtd-ram"; + reg =3D <1 0x00000000 0x02000000>; + bank-width =3D <4>; + }; + + v2m_video_ram: vram@2,00000000 { + compatible =3D "arm,vexpress-vram"; + reg =3D <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible =3D "smsc,lan9118", "smsc,lan9115"; + reg =3D <2 0x02000000 0x10000>; + interrupts =3D <15>; + phy-mode =3D "mii"; + reg-io-width =3D <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply =3D <&v2m_fixed_3v3>; + vddvario-supply =3D <&v2m_fixed_3v3>; + }; + + usb@2,03000000 { + compatible =3D "nxp,usb-isp1761"; + reg =3D <2 0x03000000 0x20000>; + interrupts =3D <16>; + port1-otg; + }; + + iofpga@3,00000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible =3D "arm,vexpress-sysreg"; + reg =3D <0x010000 0x1000>; + + v2m_led_gpios: sys_led { + compatible =3D "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + v2m_mmc_gpios: sys_mci { + compatible =3D "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + v2m_flash_gpios: sys_flash { + compatible =3D "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + + v2m_sysctl: sysctl@020000 { + compatible =3D "arm,sp810", "arm,primecell"; + reg =3D <0x020000 0x1000>; + clocks =3D <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names =3D "refclk", "timclk", "apb_pclk"; + #clock-cells =3D <1>; + clock-output-names =3D "timerclken0", "timerclken1", "timerclken2", "t= imerclken3"; + assigned-clocks =3D <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>,= <&v2m_sysctl 3>; + assigned-clock-parents =3D <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m= _refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@030000 { + compatible =3D "arm,versatile-i2c"; + reg =3D <0x030000 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pcie-switch@60 { + compatible =3D "idt,89hpes32h8"; + reg =3D <0x60>; + }; + }; + + aaci@040000 { + compatible =3D "arm,pl041", "arm,primecell"; + reg =3D <0x040000 0x1000>; + interrupts =3D <11>; + clocks =3D <&smbclk>; + clock-names =3D "apb_pclk"; + }; + + mmci@050000 { + compatible =3D "arm,pl180", "arm,primecell"; + reg =3D <0x050000 0x1000>; + interrupts =3D <9 10>; + cd-gpios =3D <&v2m_mmc_gpios 0 0>; + wp-gpios =3D <&v2m_mmc_gpios 1 0>; + max-frequency =3D <12000000>; + vmmc-supply =3D <&v2m_fixed_3v3>; + clocks =3D <&v2m_clk24mhz>, <&smbclk>; + clock-names =3D "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x060000 0x1000>; + interrupts =3D <12>; + clocks =3D <&v2m_clk24mhz>, <&smbclk>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x070000 0x1000>; + interrupts =3D <13>; + clocks =3D <&v2m_clk24mhz>, <&smbclk>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x090000 0x1000>; + interrupts =3D <5>; + clocks =3D <&v2m_oscclk2>, <&smbclk>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0a0000 0x1000>; + interrupts =3D <6>; + clocks =3D <&v2m_oscclk2>, <&smbclk>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0b0000 0x1000>; + interrupts =3D <7>; + clocks =3D <&v2m_oscclk2>, <&smbclk>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0c0000 0x1000>; + interrupts =3D <8>; + clocks =3D <&v2m_oscclk2>, <&smbclk>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible =3D "arm,sp805", "arm,primecell"; + reg =3D <0x0f0000 0x1000>; + interrupts =3D <0>; + clocks =3D <&v2m_refclk32khz>, <&smbclk>; + clock-names =3D "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible =3D "arm,sp804", "arm,primecell"; + reg =3D <0x110000 0x1000>; + interrupts =3D <2>; + clocks =3D <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names =3D "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible =3D "arm,sp804", "arm,primecell"; + reg =3D <0x120000 0x1000>; + interrupts =3D <3>; + clocks =3D <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names =3D "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible =3D "arm,versatile-i2c"; + reg =3D <0x160000 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + dvi-transmitter@39 { + compatible =3D "sil,sii9022-tpi", "sil,sii9022"; + reg =3D <0x39>; + }; + + dvi-transmitter@60 { + compatible =3D "sil,sii9022-cpi", "sil,sii9022"; + reg =3D <0x60>; + }; + }; + + rtc@170000 { + compatible =3D "arm,pl031", "arm,primecell"; + reg =3D <0x170000 0x1000>; + interrupts =3D <4>; + clocks =3D <&smbclk>; + clock-names =3D "apb_pclk"; + }; + + compact-flash@1a0000 { + compatible =3D "arm,vexpress-cf", "ata-generic"; + reg =3D <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift =3D <2>; + }; + + clcd@1f0000 { + compatible =3D "arm,pl111", "arm,primecell"; + reg =3D <0x1f0000 0x1000>; + interrupt-names =3D "combined"; + interrupts =3D <14>; + clocks =3D <&v2m_oscclk1>, <&smbclk>; + clock-names =3D "clcdclk", "apb_pclk"; + memory-region =3D <&v2m_video_ram>; + max-memory-bandwidth =3D <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint =3D <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads =3D <0 8 16>; + }; + }; + + panel { + compatible =3D "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint =3D <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency =3D <25175000>; + hactive =3D <640>; + hback-porch =3D <40>; + hfront-porch =3D <24>; + hsync-len =3D <96>; + vactive =3D <480>; + vback-porch =3D <32>; + vfront-porch =3D <11>; + vsync-len =3D <2>; + }; + }; + }; + }; + + v2m_fixed_3v3: fixed-regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000>; + clock-output-names =3D "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "v2m:refclk32khz"; + }; + + leds { + compatible =3D "gpio-leds"; + + user1 { + label =3D "v2m:green:user1"; + gpios =3D <&v2m_led_gpios 0 0>; + linux,default-trigger =3D "heartbeat"; + }; + + user2 { + label =3D "v2m:green:user2"; + gpios =3D <&v2m_led_gpios 1 0>; + linux,default-trigger =3D "mmc0"; + }; + + user3 { + label =3D "v2m:green:user3"; + gpios =3D <&v2m_led_gpios 2 0>; + linux,default-trigger =3D "cpu0"; + }; + + user4 { + label =3D "v2m:green:user4"; + gpios =3D <&v2m_led_gpios 3 0>; + linux,default-trigger =3D "cpu1"; + }; + + user5 { + label =3D "v2m:green:user5"; + gpios =3D <&v2m_led_gpios 4 0>; + linux,default-trigger =3D "cpu2"; + }; + + user6 { + label =3D "v2m:green:user6"; + gpios =3D <&v2m_led_gpios 5 0>; + linux,default-trigger =3D "cpu3"; + }; + + user7 { + label =3D "v2m:green:user7"; + gpios =3D <&v2m_led_gpios 6 0>; + linux,default-trigger =3D "cpu4"; + }; + + user8 { + label =3D "v2m:green:user8"; + gpios =3D <&v2m_led_gpios 7 0>; + linux,default-trigger =3D "cpu5"; + }; + }; + + mcc { + compatible =3D "arm,vexpress,config-bus"; + arm,vexpress,config-bridge =3D <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 0>; + freq-range =3D <25000000 60000000>; + #clock-cells =3D <0>; + clock-output-names =3D "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 1>; + freq-range =3D <23750000 65000000>; + #clock-cells =3D <0>; + clock-output-names =3D "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 2>; + freq-range =3D <24000000 24000000>; + #clock-cells =3D <0>; + clock-output-names =3D "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible =3D "arm,vexpress-volt"; + arm,vexpress-sysreg,func =3D <2 0>; + regulator-name =3D "VIO"; + regulator-always-on; + label =3D "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible =3D "arm,vexpress-temp"; + arm,vexpress-sysreg,func =3D <4 0>; + label =3D "MCC"; + }; + + reset { + compatible =3D "arm,vexpress-reset"; + arm,vexpress-sysreg,func =3D <5 0>; + }; + + muxfpga { + compatible =3D "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func =3D <7 0>; + }; + + shutdown { + compatible =3D "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func =3D <8 0>; + }; + + reboot { + compatible =3D "arm,vexpress-reboot"; + arm,vexpress-sysreg,func =3D <9 0>; + }; + + dvimode { + compatible =3D "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func =3D <11 0>; + }; + }; + }; diff --git a/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb b/P= latforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb new file mode 100644 index 0000000000000000000000000000000000000000..fe655a05cc6e48d2a9d4247c85c= 04472e1a146ab GIT binary patch literal 19070 zcmcg!U5q5xRj!&@Cv1rEX5)n=3D{LSt`X++8VT`$Rx*mjD-lmT@PGmmmcoNUJn>|ZLA*H%FT5l~5xgM&zVF<7Zk_7x z*_~c*xKef9bI-Zw@1FZtb*tZg^nbn+MPK;sD2lE`(dS>r{YhLO!gUH4(uq%^{H)8j zeq#@<C{u07v<_Qtj6FB{wmoE_14EK$6Hs0LN56W3y zRh#?0GRaafN-swi0YW6@@ig+(LE%p$zh>a;9*(o&w8|%d96nA*MOx(*Vb+D+(W}o? zI-O_s(plZ_TqSII+*qAQI?rQwbspRE zJf^Gj$Se=3DG-R)I)6uqq9y`(I}r{wWltMce<1s-h2I4k$0k&w4-Y}=3De|%tYG0v_?bw zI?9M+UB;TkST>#2`9Xrhk8c3}Az#LLe$&IMcfX4QB&Aca2A^@ZZ)rEYt?s5F`K|@bn2#YSoV3a3Soz`wlinGyP zRp+y$8s&MJY!|yAM53$^$4#ApW9BVfs?*;i`>zK6HpKmvfxjO`?|<9CY&+J~`qYtm z=3DdYGdqoS@yIdDv*d5?O<|L*y)J)zghzcn!RvN1-z2vaY;;&DEn&JO#201xBx`$6-% z!y)H%J%zjU_d6^>>dUXQ^Y)wfM|3pA-}HnAu)gx75MB*2SFSn6myy zafy$bc_7&>GEq#6u1ZN$hdP`C$ojnKBd#@=3D2qVQk{4n3gC9$=3Ds%O`)|j5dH`65FCp zAtk)QAHX-|?qTxMnBkZQyC0)mmh;X&!E%M!CkRWsWLeSgWz7P`({a3Uwr53hv01yQ zJ(k~f&yW16u(OG?ilop!$iy#b=3D_c{yg5PSC?&nFd(}$pr6p5~nBWra?vU)ZG87aIi z@z1B33@wB?$3k`=3Dw;)sPr>)k0!eW1r{p`b#{qi!|wk_y;!XmpI@AWx&0A`|oAI8

`rnWs=3D@fry1L_BTUjeLoz3TJ6ox)g07}2u4FAv6P9~x3Yr(uxc{D`q+t8+gc zzXu7Df{xawzX6o$_^T%WYbO6ilmB&}U&)Rt%V>ufg8EFX|4CdD54zt;KzQVyhe+0R zb!m+B#jpOal;J1Xr{e_?H*nEDiOCuh)r_SL50Q_p)&AuqV5wWjw>g=3Dm35>h!Ok~-X_xD!KHFuH~HW3dGezlDU-7iY;D$QQ#8fs)}<6>OrAE{*eMS3 zL6VK8*)1)HjJOmkM@RT8@#K=3D?8T)sa@S|=3DV+jYJp%<+Y=3D_;}!=3DfwDuN)i~P3OuSR< zCfjb?L>kKdI__x8D0cGD#7-xyGv?wD1VkdSE`9$^+}Zw2TJ}!7zSCd(&+pywWt3rU zWj$}3$P&Gs?5^@zMKfNYUvWcMCKHtRotY>{PT%dUrfRcjVz8&tj|P$Va$%-#Usd#S1=3DjKD$gUU9Um@SpdK zVej>-06OKrAJ>}b!^F5Qy`?$C4_`;kWD#shLsvP>7a#)X-#-|Y@ z_DGxLH6F8X_T0X_18P_2Jnp)N%d28{SSO(DE?MO}df4gK!5j3VBo>K$_H})x;`LeB zXT&Aeq^@2R=3DaWG>#RCKnvkuZ42PftkSJ!YSPY=3DudLV*f%ej!X7^@{7Vz(Z*o8y;+v z{v573TS*!5O-F0f1v=3D6p#IV!TWp3VR{+8@V# z&dxb1)MGnTQYG-`vlZ6+SpQK5;kJw(N*bTu%MMnZkHyobF6D9DQGF?ou*%bWyt6l%&awveRNWAX>w?$#&tk@XpUL^$|{ap+&#s2^8t6OPSVm+~0@ z3R528w!9un8XC$wD$amfh=3DDVvF6Dj1z?4V0EpH1YZF$5mi)$1w$oo-Km-2qXz?4V0 zE$<>q+VU7J$CdYErY`0Eq=3D6}qa9f@%?}E?iPwpj-EAK35wY@0srwmMagjJs2qoXPpRGM?d+iuOd+iuPdkG(5Z~k!NdHq`u z!L-o6+*3Skd+iuSd(Sp9Op zJHU|e0&pR5km4YZL>fsPM0^?fNTOoCjC>`r@qC%TxreVF;8-q+o;7umjnAP-b%LMQ zUUii6`y75DYl9wI1^p$91#fn725Ff#OU^pw#VG6vwr>t#=3Dx*;+VHMt{D}_yu~q$6=3Dy;krEcC( z9On>Qk7KOjn725NM~Y+K;@CwLXSxeY-C9y{oWpHB&T)!k-r_hPD2{oHWA{^>>53?I zYahjN%(3iP2+$Ri;Fu>aHYXAR%2>?)jx(1pB`>%4s~98VH#`mN zvQIJj@o4Q}R!IfIY!g|h>hmzXha4wmH+q1%0J36jH}Xc3xgp*erPUCtC`_=3DD98UCM zEVbk(LL6l~h0i%+@?#(1nqHE3nB06`?fZQYut>(~vYMsies`H{#(!J35J%&Bkf4%? zAy1BFlq)e#rbtU=3D?Nd~*C5m($W7=3D{^NG^_#@^`H7gmT)zIh}Fk<;k2*SZvFANOh9q zz|v+151E*N5?c2AjcQzFo1=3D7cwcEWC8Nh9mgf7Sy;bNi6l6SM_ImX%_j*CM1L$|d* z0ze(98`9dJ;z#p;?enC22YG$APWam%78~}eZK^L1$jp9%EoTKjw_tx4`V&G9vLml44MVNAKjPe1pQlDe?GX9%$bRb*%FJA}z z*6C0BNNr@yaokau@(7C`$!na2IJl=3DwL&xg(lX+oICgC8{4GSo7dNH1kv~`Xaq)TO! zxAM-`J}^&`AqU%lkb_lJmev-4Tz-;=3DW#LdPQJVouXpAV z%j=3Dw@Hs&s`lfu{Ou2jbc!5Ub#9f^J=3DR%yh3u3!TKDxZ{nh!qHCIFMZXiC zev(IM=3DW^6J>Wre(mmFLA${5MIAa>cGE zP^PwFO%b123}NTvTVt5l{vN>k_}P2f#~se1k2ywB*JZk3ogSaL{?d!T^tsPp`?>4w zJ|%4~`dn6b3!mfbBde_7Z?-Y@(DC?z^jY%#h}EZi#5q~WLOipj7yZMiu>Rp1R@(~u zpZE-AE{r(7PdI(T!Cmq>zCIrS^`bs(#rLRB>${fY>%-o-s1IB5J?hi?M&|hXFmf05 zVOu`1K0Kq|X-*Zk+Up+Y(_Q><#9Y*eg;pQVU9I@J*LifAllonrw00x2;}v{FosKwD z>U2VcF42j7mpWnHB;(I{QX%oq@k{l?9wI*DCe(Z)v!cw8z4l1pW8Ld&rh1Wad|f%S zE&7jo&g)A3sVmDLNY^FbRUL0$G_C#_LIdV+lkUTO?G+60v{T9I!-8e zYnVU5 zorz-v{pDrITJ#eJeiM1Z!Cz&H*W4&TVja#<8&Z}G5N(oJqQ~;wtBamOIFt-x&v0?N3^Ncqs3G8 z;D|vPss~}w1J4>N^yJw1tykboqXaf_Fq2Con7QBk$j}iAyG&@ACA*m=3DI(Loivs-klBKD-F#OzJi_SD?7S5zTTa}S7L3PWh$HF zaO+vq|J!#KUpeTnf9>~F542zFI}603>&xc54$=3DLgeQSZU_v`QeLmvvzhxd^$A?oR5 zeCOIh;Wv>dZ1f9#73+$&f0LuXLt%aL#F_x-@9{m2`KIPR`UQFH2j9TOJ+jr0u;?de z(f5lfU?$R>#?^{}s19v+IuJt@lWXc(6A9NsGF7udYpkKOnjWUHV z{!b(KV<>rk7+2elhJbkb^_#eBpB5hDy#xLQ28uQ52m*# zWQ0U{+^MvAwTY}w;3>)5wLP6W!$|Wut~Q@pt^}6HNyozZ2K$upbda-%G>di_0#BoM z$x{ZDQ5So~!)jYTd7aw}lm1@kD>z3{2gc@gTnb}M3-1`BJ`m6S8-4<9d=3D7b~g>K>8 z19|bfiL%#l*F;*TCvZ^~6U(%meL%~_&m=3D%%-_>&RRr-(na`nMUI&>6q2Q=3DI++Ti*(e9+#Rnc1@8I# zR)no`hdc1C*e5jk3-*>rIY606RK!bO!f{o%V9df-!Me@ zh%X(vZzA!R4AU}#Vza{pi{pHf9VYm)E$X-LzZonlhdhtUNQ;aR!-&Mg1Z9+h$8lj&Yv?$utr z-J6DaY*q|*^HyUe?$y*L4gqHo8RCs7G@?iSMuFBCkX{%U*=3D#D~Vna4g50;jvquc3W zl}snmDBVWHxNo+lJI?S|4t1V{Q~CTGm&WpOS|;PPy45an%H!3w|JE5)(RMnymE6Y5 zfnih*4-?OOH^G9{mC7s8V)ms38~OrYs}J$rfqPHNLj3v65I^{ThyB4|Yb#Bvy|Nq~ z653B^VB%p0RX3T|yOFGgn}0)yF1P{-=3DCs0B4cK$L&qS-J4JWP#AW{YiD^=3D0$(r4(v zrbYL$c2&V}a#9V8o!Yp<#h7;j2nsk@nn3;@BY{f>&UVHDpB)@*);o1F>+E*6JJ13P z{GszkG~7x`}bAiYJ literal 0 HcmV?d00001 diff --git a/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts b/P= latforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts new file mode 100644 index 000000000000..bd107c5a0226 --- /dev/null +++ b/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts @@ -0,0 +1,659 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A15x2 A7x3 + * Cortex-A15_A7 MPCore (V2P-CA15_A7) + * + * HBI-0249A + */ + +/dts-v1/; + +/ { + model =3D "V2P-CA15_CA7"; + arm,hbi =3D <0x249>; + arm,vexpress,site =3D <0xf>; + compatible =3D "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + aliases { + serial0 =3D &v2m_serial0; + serial1 =3D &v2m_serial1; + serial2 =3D &v2m_serial2; + serial3 =3D &v2m_serial3; + i2c0 =3D &v2m_i2c_dvi; + i2c1 =3D &v2m_i2c_pcie; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a15"; + reg =3D <0>; + cci-control-port =3D <&cci_control1>; + cpu-idle-states =3D <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz =3D <1024>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a15"; + reg =3D <1>; + cci-control-port =3D <&cci_control1>; + cpu-idle-states =3D <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz =3D <1024>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x100>; + cci-control-port =3D <&cci_control2>; + cpu-idle-states =3D <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz =3D <516>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x101>; + cci-control-port =3D <&cci_control2>; + cpu-idle-states =3D <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz =3D <516>; + }; + + cpu4: cpu@4 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x102>; + cci-control-port =3D <&cci_control2>; + cpu-idle-states =3D <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz =3D <516>; + }; + + idle-states { + CLUSTER_SLEEP_BIG: cluster-sleep-big { + compatible =3D "arm,idle-state"; + local-timer-stop; + entry-latency-us =3D <1000>; + exit-latency-us =3D <700>; + min-residency-us =3D <2000>; + }; + + CLUSTER_SLEEP_LITTLE: cluster-sleep-little { + compatible =3D "arm,idle-state"; + local-timer-stop; + entry-latency-us =3D <1000>; + exit-latency-us =3D <500>; + min-residency-us =3D <2500>; + }; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0 0x80000000 0 0x40000000>; + }; + + wdt@2a490000 { + compatible =3D "arm,sp805", "arm,primecell"; + reg =3D <0 0x2a490000 0 0x1000>; + interrupts =3D <0 98 4>; + clocks =3D <&oscclk6a>, <&oscclk6a>; + clock-names =3D "wdogclk", "apb_pclk"; + }; + + hdlcd@2b000000 { + compatible =3D "arm,hdlcd"; + reg =3D <0 0x2b000000 0 0x1000>; + interrupts =3D <0 85 4>; + clocks =3D <&hdlcd_clk>; + clock-names =3D "pxlclk"; + }; + + memory-controller@2b0a0000 { + compatible =3D "arm,pl341", "arm,primecell"; + reg =3D <0 0x2b0a0000 0 0x1000>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + }; + + gic: interrupt-controller@2c001000 { + compatible =3D "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x2000>, + <0 0x2c004000 0 0x2000>, + <0 0x2c006000 0 0x2000>; + interrupts =3D <1 9 0xf04>; + }; + + cci@2c090000 { + compatible =3D "arm,cci-400"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0 0x2c090000 0 0x1000>; + ranges =3D <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible =3D "arm,cci-400-ctrl-if"; + interface-type =3D "ace"; + reg =3D <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible =3D "arm,cci-400-ctrl-if"; + interface-type =3D "ace"; + reg =3D <0x5000 0x1000>; + }; + + pmu@9000 { + compatible =3D "arm,cci-400-pmu,r0"; + reg =3D <0x9000 0x5000>; + interrupts =3D <0 105 4>, + <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>; + }; + }; + + memory-controller@7ffd0000 { + compatible =3D "arm,pl354", "arm,primecell"; + reg =3D <0 0x7ffd0000 0 0x1000>; + interrupts =3D <0 86 4>, + <0 87 4>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + }; + + dma@7ff00000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0 0x7ff00000 0 0x1000>; + interrupts =3D <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + }; + + scc@7fff0000 { + compatible =3D "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + reg =3D <0 0x7fff0000 0 0x1000>; + interrupts =3D <0 95 4>; + }; + + timer { + compatible =3D "arm,armv7-timer"; + interrupts =3D <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + pmu_a15 { + compatible =3D "arm,cortex-a15-pmu"; + interrupts =3D <0 68 4>, + <0 69 4>; + interrupt-affinity =3D <&cpu0>, + <&cpu1>; + }; + + pmu_a7 { + compatible =3D "arm,cortex-a7-pmu"; + interrupts =3D <0 128 4>, + <0 129 4>, + <0 130 4>; + interrupt-affinity =3D <&cpu2>, + <&cpu3>, + <&cpu4>; + }; + + oscclk6a: oscclk6a { + /* Reference 24MHz clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "oscclk6a"; + }; + + dcc { + compatible =3D "arm,vexpress,config-bus"; + arm,vexpress,config-bridge =3D <&v2m_sysreg>; + + oscclk0 { + /* A15 PLL 0 reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 0>; + freq-range =3D <17000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk0"; + }; + + oscclk1 { + /* A15 PLL 1 reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 1>; + freq-range =3D <17000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk1"; + }; + + oscclk2 { + /* A7 PLL 0 reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 2>; + freq-range =3D <17000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk2"; + }; + + oscclk3 { + /* A7 PLL 1 reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 3>; + freq-range =3D <17000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk3"; + }; + + oscclk4 { + /* External AXI master clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 4>; + freq-range =3D <20000000 40000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk4"; + }; + + hdlcd_clk: oscclk5 { + /* HDLCD PLL reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 5>; + freq-range =3D <23750000 165000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk5"; + }; + + smbclk: oscclk6 { + /* Static memory controller clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 6>; + freq-range =3D <20000000 40000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk6"; + }; + + oscclk7 { + /* SYS PLL reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 7>; + freq-range =3D <17000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk7"; + }; + + oscclk8 { + /* DDR2 PLL reference clock */ + compatible =3D "arm,vexpress-osc"; + arm,vexpress-sysreg,func =3D <1 8>; + freq-range =3D <20000000 50000000>; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk8"; + }; + + volt-a15 { + /* A15 CPU core voltage */ + compatible =3D "arm,vexpress-volt"; + arm,vexpress-sysreg,func =3D <2 0>; + regulator-name =3D "A15 Vcore"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1050000>; + regulator-always-on; + label =3D "A15 Vcore"; + }; + + volt-a7 { + /* A7 CPU core voltage */ + compatible =3D "arm,vexpress-volt"; + arm,vexpress-sysreg,func =3D <2 1>; + regulator-name =3D "A7 Vcore"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1050000>; + regulator-always-on; + label =3D "A7 Vcore"; + }; + + amp-a15 { + /* Total current for the two A15 cores */ + compatible =3D "arm,vexpress-amp"; + arm,vexpress-sysreg,func =3D <3 0>; + label =3D "A15 Icore"; + }; + + amp-a7 { + /* Total current for the three A7 cores */ + compatible =3D "arm,vexpress-amp"; + arm,vexpress-sysreg,func =3D <3 1>; + label =3D "A7 Icore"; + }; + + temp-dcc { + /* DCC internal temperature */ + compatible =3D "arm,vexpress-temp"; + arm,vexpress-sysreg,func =3D <4 0>; + label =3D "DCC"; + }; + + power-a15 { + /* Total power for the two A15 cores */ + compatible =3D "arm,vexpress-power"; + arm,vexpress-sysreg,func =3D <12 0>; + label =3D "A15 Pcore"; + }; + + power-a7 { + /* Total power for the three A7 cores */ + compatible =3D "arm,vexpress-power"; + arm,vexpress-sysreg,func =3D <12 1>; + label =3D "A7 Pcore"; + }; + + energy-a15 { + /* Total energy for the two A15 cores */ + compatible =3D "arm,vexpress-energy"; + arm,vexpress-sysreg,func =3D <13 0>, <13 1>; + label =3D "A15 Jcore"; + }; + + energy-a7 { + /* Total energy for the three A7 cores */ + compatible =3D "arm,vexpress-energy"; + arm,vexpress-sysreg,func =3D <13 2>, <13 3>; + label =3D "A7 Jcore"; + }; + }; + + etb@0,20010000 { + compatible =3D "arm,coresight-etb10", "arm,primecell"; + reg =3D <0 0x20010000 0 0x1000>; + + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + etb_in_port: endpoint { + slave-mode; + remote-endpoint =3D <&replicator_out_port0>; + }; + }; + }; + + tpiu@0,20030000 { + compatible =3D "arm,coresight-tpiu", "arm,primecell"; + reg =3D <0 0x20030000 0 0x1000>; + + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint =3D <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible =3D "arm,coresight-replicator"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* replicator output ports */ + port@0 { + reg =3D <0>; + replicator_out_port0: endpoint { + remote-endpoint =3D <&etb_in_port>; + }; + }; + + port@1 { + reg =3D <1>; + replicator_out_port1: endpoint { + remote-endpoint =3D <&tpiu_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg =3D <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint =3D <&funnel_out_port0>; + }; + }; + }; + }; + + funnel@0,20040000 { + compatible =3D "arm,coresight-funnel", "arm,primecell"; + reg =3D <0 0x20040000 0 0x1000>; + + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* funnel output port */ + port@0 { + reg =3D <0>; + funnel_out_port0: endpoint { + remote-endpoint =3D + <&replicator_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg =3D <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint =3D <&ptm0_out_port>; + }; + }; + + port@2 { + reg =3D <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint =3D <&ptm1_out_port>; + }; + }; + + port@3 { + reg =3D <2>; + funnel_in_port2: endpoint { + slave-mode; + remote-endpoint =3D <&etm0_out_port>; + }; + }; + + /* Input port #3 is for ITM, not supported here */ + + port@4 { + reg =3D <4>; + funnel_in_port4: endpoint { + slave-mode; + remote-endpoint =3D <&etm1_out_port>; + }; + }; + + port@5 { + reg =3D <5>; + funnel_in_port5: endpoint { + slave-mode; + remote-endpoint =3D <&etm2_out_port>; + }; + }; + }; + }; + + ptm@0,2201c000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0 0x2201c000 0 0x1000>; + + cpu =3D <&cpu0>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + ptm0_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port0>; + }; + }; + }; + + ptm@0,2201d000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0 0x2201d000 0 0x1000>; + + cpu =3D <&cpu1>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + ptm1_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port1>; + }; + }; + }; + + etm@0,2203c000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0 0x2203c000 0 0x1000>; + + cpu =3D <&cpu2>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + etm0_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port2>; + }; + }; + }; + + etm@0,2203d000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0 0x2203d000 0 0x1000>; + + cpu =3D <&cpu3>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + etm1_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port4>; + }; + }; + }; + + etm@0,2203e000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0 0x2203e000 0 0x1000>; + + cpu =3D <&cpu4>; + clocks =3D <&oscclk6a>; + clock-names =3D "apb_pclk"; + port { + etm2_out_port: endpoint { + remote-endpoint =3D <&funnel_in_port5>; + }; + }; + }; + + smb@08000000 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 63>; + interrupt-map =3D <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m-rs1.dtsi" + }; + + site2: hsb@40000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x40000000 0x3fef0000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 3>; + interrupt-map =3D <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel