From nobody Sat Nov 2 12:24:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1490756655256784.2803992014433; Tue, 28 Mar 2017 20:04:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ED51F21940D13; Tue, 28 Mar 2017 20:04:02 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A7A8C21940D01 for ; Tue, 28 Mar 2017 20:03:58 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP; 28 Mar 2017 20:03:58 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.25]) by orsmga001.jf.intel.com with ESMTP; 28 Mar 2017 20:03:57 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,239,1486454400"; d="scan'208";a="1113146624" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Wed, 29 Mar 2017 11:03:45 +0800 Message-Id: <20170329030346.249872-10-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.9.0.windows.1 In-Reply-To: <20170329030346.249872-1-ruiyu.ni@intel.com> References: <20170329030346.249872-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH 09/10] UefiCpuPkg/MtrrLib: Refine MtrrGetMemoryAttributeByAddressWorker X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Jeff Fan --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 237 ++++++++++++-------------------= ---- 1 file changed, 80 insertions(+), 157 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index 34e6ad6..920cc5f 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -568,20 +568,19 @@ MtrrLibProgramFixedMtrr ( This function shadows the content of variable MTRRs into an internal array: VariableMtrr. =20 - @param[in] VariableSettings The variable MTRR values to shad= ow - @param[in] FirmwareVariableMtrrCount The number of variable MTRRs ava= ilable to firmware - @param[in] MtrrValidBitsMask The mask for the valid bit of th= e MTRR - @param[in] MtrrValidAddressMask The valid address mask for MTRR - @param[out] VariableMtrr The array to shadow variable MTR= Rs content + @param[in] VariableSettings The variable MTRR values to shadow + @param[in] VariableMtrrCount The number of variable MTRRs + @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR + @param[in] MtrrValidAddressMask The valid address mask for MTRR + @param[out] VariableMtrr The array to shadow variable MTRRs co= ntent =20 - @return The return value of this parameter indicat= es the - number of MTRRs which has been used. + @return Number of MTRRs which has been used. =20 **/ UINT32 MtrrGetMemoryAttributeInVariableMtrrWorker ( IN MTRR_VARIABLE_SETTINGS *VariableSettings, - IN UINTN FirmwareVariableMtrrCount, + IN UINTN VariableMtrrCount, IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT VARIABLE_MTRR *VariableMtrr @@ -591,7 +590,7 @@ MtrrGetMemoryAttributeInVariableMtrrWorker ( UINT32 UsedMtrr; =20 ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * MTRR_NUMBER_OF_VARIABLE_= MTRR); - for (Index =3D 0, UsedMtrr =3D 0; Index < FirmwareVariableMtrrCount; Ind= ex++) { + for (Index =3D 0, UsedMtrr =3D 0; Index < VariableMtrrCount; Index++) { if ((VariableSettings->Mtrr[Index].Mask & MTRR_LIB_CACHE_MTRR_ENABLED)= !=3D 0) { VariableMtrr[Index].Msr =3D (UINT32)Index; VariableMtrr[Index].BaseAddress =3D (VariableSettings->Mtrr[Index].B= ase & MtrrValidAddressMask); @@ -724,8 +723,10 @@ MtrrLibGetPositiveMtrrNumber ( Return whether the left MTRR type precedes the right MTRR type. =20 The MTRR type precedence rules are: - 1. UC precedes any other type - 2. WT precedes WB + 1. UC precedes any other type + 2. WT precedes WB + For further details, please refer the IA32 Software Developer's Manual, + Volume 3, Section "MTRR Precedences". =20 @param Left The left MTRR type. @param Right The right MTRR type. @@ -954,46 +955,6 @@ MtrrLibGetMtrrNumber ( return LeastSubtractiveMtrrNumber + MiddleMtrrNumber + LeastRightMtrrNum= ber; } =20 - -/** - Converts the Memory attribute value to MTRR_MEMORY_CACHE_TYPE. - - If MtrrSetting is not NULL, gets the default memory attribute from input - MTRR settings buffer. - If MtrrSetting is NULL, gets the default memory attribute from MSR. - - @param[in] MtrrSetting A buffer holding all MTRRs content. - @param[in] MtrrType MTRR memory type - - @return The enum item in MTRR_MEMORY_CACHE_TYPE - -**/ -MTRR_MEMORY_CACHE_TYPE -GetMemoryCacheTypeFromMtrrType ( - IN MTRR_SETTINGS *MtrrSetting, - IN UINT64 MtrrType - ) -{ - switch (MtrrType) { - case MTRR_CACHE_UNCACHEABLE: - return CacheUncacheable; - case MTRR_CACHE_WRITE_COMBINING: - return CacheWriteCombining; - case MTRR_CACHE_WRITE_THROUGH: - return CacheWriteThrough; - case MTRR_CACHE_WRITE_PROTECTED: - return CacheWriteProtected; - case MTRR_CACHE_WRITE_BACK: - return CacheWriteBack; - default: - // - // MtrrType is MTRR_CACHE_INVALID_TYPE, that means - // no MTRR covers the range - // - return MtrrGetDefaultMemoryTypeWorker (MtrrSetting); - } -} - /** Initializes the valid bits mask and valid address mask for MTRRs. =20 @@ -1030,71 +991,34 @@ MtrrLibInitializeMtrrMask ( Determines the real attribute of a memory range. =20 This function is to arbitrate the real attribute of the memory when - there are 2 MTRRs covers the same memory range. For further details, + there are 2 MTRRs covers the same memory range. For further details, please refer the IA32 Software Developer's Manual, Volume 3, - Section 10.11.4.1. + Section "MTRR Precedences". =20 @param[in] MtrrType1 The first kind of Memory type @param[in] MtrrType2 The second kind of memory type =20 **/ -UINT64 +MTRR_MEMORY_CACHE_TYPE MtrrLibPrecedence ( - IN UINT64 MtrrType1, - IN UINT64 MtrrType2 + IN MTRR_MEMORY_CACHE_TYPE MtrrType1, + IN MTRR_MEMORY_CACHE_TYPE MtrrType2 ) { - UINT64 MtrrType; - - MtrrType =3D MTRR_CACHE_INVALID_TYPE; - switch (MtrrType1) { - case MTRR_CACHE_UNCACHEABLE: - MtrrType =3D MTRR_CACHE_UNCACHEABLE; - break; - case MTRR_CACHE_WRITE_COMBINING: - if ( - MtrrType2=3D=3DMTRR_CACHE_WRITE_COMBINING || - MtrrType2=3D=3DMTRR_CACHE_UNCACHEABLE - ) { - MtrrType =3D MtrrType2; - } - break; - case MTRR_CACHE_WRITE_THROUGH: - if ( - MtrrType2=3D=3DMTRR_CACHE_WRITE_THROUGH || - MtrrType2=3D=3DMTRR_CACHE_WRITE_BACK - ) { - MtrrType =3D MTRR_CACHE_WRITE_THROUGH; - } else if(MtrrType2=3D=3DMTRR_CACHE_UNCACHEABLE) { - MtrrType =3D MTRR_CACHE_UNCACHEABLE; - } - break; - case MTRR_CACHE_WRITE_PROTECTED: - if (MtrrType2 =3D=3D MTRR_CACHE_WRITE_PROTECTED || - MtrrType2 =3D=3D MTRR_CACHE_UNCACHEABLE) { - MtrrType =3D MtrrType2; - } - break; - case MTRR_CACHE_WRITE_BACK: - if ( - MtrrType2=3D=3D MTRR_CACHE_UNCACHEABLE || - MtrrType2=3D=3DMTRR_CACHE_WRITE_THROUGH || - MtrrType2=3D=3D MTRR_CACHE_WRITE_BACK - ) { - MtrrType =3D MtrrType2; - } - break; - case MTRR_CACHE_INVALID_TYPE: - MtrrType =3D MtrrType2; - break; - default: - break; + if (MtrrType1 =3D=3D MtrrType2) { + return MtrrType1; } =20 - if (MtrrType2 =3D=3D MTRR_CACHE_INVALID_TYPE) { - MtrrType =3D MtrrType1; + ASSERT ( + MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) || + MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1) + ); + + if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) { + return MtrrType1; + } else { + return MtrrType2; } - return MtrrType; } =20 /** @@ -1116,29 +1040,27 @@ MtrrGetMemoryAttributeByAddressWorker ( IN PHYSICAL_ADDRESS Address ) { - UINT64 TempQword; - UINTN Index; - UINTN SubIndex; - UINT64 MtrrType; - UINT64 TempMtrrType; - MTRR_MEMORY_CACHE_TYPE CacheType; - VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - UINTN VariableMtrrCount; - MTRR_VARIABLE_SETTINGS VariableSettings; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + UINT64 FixedMtrr; + UINTN Index; + UINTN SubIndex; + MTRR_MEMORY_CACHE_TYPE MtrrType; + VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTR= R]; + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + UINT32 VariableMtrrCount; + MTRR_VARIABLE_SETTINGS VariableSettings; =20 // // Check if MTRR is enabled, if not, return UC as attribute // if (MtrrSetting =3D=3D NULL) { - TempQword =3D AsmReadMsr64 (MTRR_LIB_IA32_MTRR_DEF_TYPE); + DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); } else { - TempQword =3D MtrrSetting->MtrrDefType; + DefType.Uint64 =3D MtrrSetting->MtrrDefType; } - MtrrType =3D MTRR_CACHE_INVALID_TYPE; =20 - if ((TempQword & MTRR_LIB_CACHE_MTRR_ENABLED) =3D=3D 0) { + if (DefType.Bits.E =3D=3D 0) { return CacheUncacheable; } =20 @@ -1146,65 +1068,66 @@ MtrrGetMemoryAttributeByAddressWorker ( // If address is less than 1M, then try to go through the fixed MTRR // if (Address < BASE_1MB) { - if ((TempQword & MTRR_LIB_CACHE_FIXED_MTRR_ENABLED) !=3D 0) { + if (DefType.Bits.FE !=3D 0) { // // Go through the fixed MTRR // for (Index =3D 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - if (Address >=3D mMtrrLibFixedMtrrTable[Index].BaseAddress && - Address < ( - mMtrrLibFixedMtrrTable[Index].BaseAddress + - (mMtrrLibFixedMtrrTable[Index].Length * 8) - ) - ) { - SubIndex =3D - ((UINTN)Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) / - mMtrrLibFixedMtrrTable[Index].Length; - if (MtrrSetting =3D=3D NULL) { - TempQword =3D AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr= ); - } else { - TempQword =3D MtrrSetting->Fixed.Mtrr[Index]; - } - MtrrType =3D RShiftU64 (TempQword, SubIndex * 8) & 0xFF; - return GetMemoryCacheTypeFromMtrrType (MtrrSetting, MtrrType); - } + if (Address >=3D mMtrrLibFixedMtrrTable[Index].BaseAddress && + Address < mMtrrLibFixedMtrrTable[Index].BaseAddress + + (mMtrrLibFixedMtrrTable[Index].Length * 8)) { + SubIndex =3D + ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) / + mMtrrLibFixedMtrrTable[Index].Length; + if (MtrrSetting =3D=3D NULL) { + FixedMtrr =3D AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr); + } else { + FixedMtrr =3D MtrrSetting->Fixed.Mtrr[Index]; + } + return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex = * 8) & 0xFF); + } } } } - MtrrLibInitializeMtrrMask(&MtrrValidBitsMask, &MtrrValidAddressMask); =20 - MtrrGetVariableMtrrWorker ( - MtrrSetting, - GetVariableMtrrCountWorker (), - &VariableSettings - ); + VariableMtrrCount =3D GetVariableMtrrCountWorker (); + ASSERT (VariableMtrrCount <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); + MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSett= ings); =20 + MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); MtrrGetMemoryAttributeInVariableMtrrWorker ( - &VariableSettings, - GetFirmwareVariableMtrrCountWorker (), - MtrrValidBitsMask, - MtrrValidAddressMask, - VariableMtrr - ); + &VariableSettings, + VariableMtrrCount, + MtrrValidBitsMask, + MtrrValidAddressMask, + VariableMtrr + ); =20 // // Go through the variable MTRR // - VariableMtrrCount =3D GetVariableMtrrCountWorker (); - ASSERT (VariableMtrrCount <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); - + MtrrType =3D CacheInvalid; for (Index =3D 0; Index < VariableMtrrCount; Index++) { if (VariableMtrr[Index].Valid) { if (Address >=3D VariableMtrr[Index].BaseAddress && - Address < VariableMtrr[Index].BaseAddress+VariableMtrr[Index].Le= ngth) { - TempMtrrType =3D VariableMtrr[Index].Type; - MtrrType =3D MtrrLibPrecedence (MtrrType, TempMtrrType); + Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].= Length) { + if (MtrrType =3D=3D CacheInvalid) { + MtrrType =3D (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type; + } else { + MtrrType =3D MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYP= E) VariableMtrr[Index].Type); + } } } } - CacheType =3D GetMemoryCacheTypeFromMtrrType (MtrrSetting, MtrrType); =20 - return CacheType; + // + // If there is no MTRR which covers the Address, use the default MTRR ty= pe. + // + if (MtrrType =3D=3D CacheInvalid) { + MtrrType =3D (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type; + } + + return MtrrType; } =20 =20 --=20 2.9.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel