From nobody Sun May 5 06:33:49 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1490662605807256.2076406670103; Mon, 27 Mar 2017 17:56:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 979EB21A18AAC; Mon, 27 Mar 2017 17:56:43 -0700 (PDT) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1589721A18AAA for ; Mon, 27 Mar 2017 17:56:42 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Mar 2017 17:56:41 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by fmsmga006.fm.intel.com with ESMTP; 27 Mar 2017 17:56:40 -0700 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490662602; x=1522198602; h=from:to:cc:subject:date:message-id; bh=aC4IXK7YBrzrp2RsCAK2cUaXCM+fxcy96Qe/ppBEjFY=; b=Kcg+bHAM1qICWgz42wXLVwdn8m0YrkiqrxaVtJOazMGFhNhqnIa+4qLf zIsL8qmxIMoKy/51P8PDTY/8r8FcaA==; X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,234,1486454400"; d="scan'208";a="81661354" From: Jeff Fan To: edk2-devel@lists.01.org Date: Tue, 28 Mar 2017 08:56:35 +0800 Message-Id: <20170328005635.20988-1-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 Subject: [edk2] [PATCH v2] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Exec= ute Disable feature is not working actually. Thus, we cannot enable it on APs. v2: Correct the commit log. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan Reviewed-by: Feng Tian --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++++++++++++++++++++++---------= ---- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 55fe812..bb93526 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1,7 +1,7 @@ /** @file CPU MP Initialize Library common functions. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GU= ID; =20 /** The function will check if BSP Execute Disable is enabled. - DxeIpl may have enabled Execute Disable for BSP, - APs need to get the status and sync up the settings. + + DxeIpl may have enabled Execute Disable for BSP, APs need to + get the status and sync up the settings. + If BSP's CR0.Paging is not set, BSP execute Disble feature is + not working actually. =20 @retval TRUE BSP Execute Disable is enabled. @retval FALSE BSP Execute Disable is not enabled. @@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled ( CPUID_EXTENDED_CPU_SIG_EDX Edx; MSR_IA32_EFER_REGISTER EferMsr; BOOLEAN Enabled; + IA32_CR0 Cr0; =20 Enabled =3D FALSE; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); - if (Eax >=3D CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32); + Cr0.UintN =3D AsmReadCr0 (); + if (Cr0.Bits.PG !=3D 0) { // - // CPUID 0x80000001 - // Bit 20: Execute Disable Bit available. + // If CR0 Paging bit is set // - if (Edx.Bits.NX !=3D 0) { - EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); + if (Eax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32); // - // MSR 0xC0000080 - // Bit 11: Execute Disable Bit enable. + // CPUID 0x80000001 + // Bit 20: Execute Disable Bit available. // - if (EferMsr.Bits.NXE !=3D 0) { - Enabled =3D TRUE; + if (Edx.Bits.NX !=3D 0) { + EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + // + // MSR 0xC0000080 + // Bit 11: Execute Disable Bit enable. + // + if (EferMsr.Bits.NXE !=3D 0) { + Enabled =3D TRUE; + } } } } --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel