From nobody Sat Nov 2 14:39:17 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1489729771470915.372064842674; Thu, 16 Mar 2017 22:49:31 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6D2E580431; Thu, 16 Mar 2017 22:49:28 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C563E8042E for ; Thu, 16 Mar 2017 22:49:26 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 16 Mar 2017 22:49:26 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by orsmga002.jf.intel.com with ESMTP; 16 Mar 2017 22:49:25 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,175,1486454400"; d="scan'208";a="61536930" From: Jeff Fan To: edk2-devel@lists.01.org Date: Fri, 17 Mar 2017 13:49:19 +0800 Message-Id: <20170317054921.12204-2-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170317054921.12204-1-jeff.fan@intel.com> References: <20170317054921.12204-1-jeff.fan@intel.com> Subject: [edk2] [PATCH v4 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Needn't to copy register table if AllocatedSize is 0. v4: Fix potential uninitialized variable issue. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 12efc1f..2588979 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -826,18 +826,21 @@ CopyRegisterTable ( =20 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOf= Cpus * sizeof (CPU_REGISTER_TABLE)); for (Index =3D 0; Index < NumberOfCpus; Index++) { - RegisterTableEntry =3D AllocatePool (DestinationRegisterTableList[Inde= x].AllocatedSize); - ASSERT (RegisterTableEntry !=3D NULL); - CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[In= dex].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize); - // - // Go though all MSRs in register table to initialize MSR spin lock - // - for (Index1 =3D 0; Index1 < DestinationRegisterTableList[Index].TableL= ength; Index1++, RegisterTableEntry++) { - if ((RegisterTableEntry->RegisterType =3D=3D Msr) && (RegisterTableE= ntry->ValidBitLength < 64)) { - // - // Initialize MSR spin lock only for those MSRs need bit field wri= ting - // - InitMsrSpinLockByIndex (RegisterTableEntry->Index); + RegisterTableEntry =3D NULL; + if (DestinationRegisterTableList[Index].AllocatedSize !=3D 0) { + RegisterTableEntry =3D AllocatePool (DestinationRegisterTableList[In= dex].AllocatedSize); + ASSERT (RegisterTableEntry !=3D NULL); + CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[= Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSiz= e); + // + // Go though all MSRs in register table to initialize MSR spin lock + // + for (Index1 =3D 0; Index1 < DestinationRegisterTableList[Index].Tabl= eLength; Index1++, RegisterTableEntry++) { + if ((RegisterTableEntry->RegisterType =3D=3D Msr) && (RegisterTabl= eEntry->ValidBitLength < 64)) { + // + // Initialize MSR spin lock only for those MSRs need bit field w= riting + // + InitMsrSpinLockByIndex (RegisterTableEntry->Index); + } } } DestinationRegisterTableList[Index].RegisterTableEntry =3D (EFI_PHYSIC= AL_ADDRESS)(UINTN)RegisterTableEntry; --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel