From nobody Sat Nov 2 14:37:16 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1489048578619672.1796955351521; Thu, 9 Mar 2017 00:36:18 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9EB6C80392; Thu, 9 Mar 2017 00:36:13 -0800 (PST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3369680396 for ; Thu, 9 Mar 2017 00:36:12 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Mar 2017 00:36:12 -0800 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2017 00:36:10 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,268,1486454400"; d="scan'208";a="1139930916" From: Jeff Fan To: edk2-devel@lists.01.org Date: Thu, 9 Mar 2017 16:35:46 +0800 Message-Id: <20170309083553.6016-5-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170309083553.6016-1-jeff.fan@intel.com> References: <20170309083553.6016-1-jeff.fan@intel.com> Subject: [edk2] [PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" All model-specific MSRs are related to processor signatures that are define= d in each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 22 ++++++++++++++++++++= +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 ++++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 ++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 ++++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/P6Msr.h | 23 ++++++++++++++++++++= ++- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 15 ++++++++++++++- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 ++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 22 ++++++++++++++++++++= +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 ++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 19 ++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 ++++++++++++++++++- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 18 +++++++++++++++++- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +++++++++++++++++- 20 files changed, 365 insertions(+), 20 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include= /Register/Msr/AtomMsr.h index c314195..b276469 100644 --- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,26 @@ #include =20 /** + Is Intel(R) Atom(TM) Processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x1C || \ + DisplayModel =3D=3D 0x26 || \ + DisplayModel =3D=3D 0x27 || \ + DisplayModel =3D=3D 0x35 || \ + DisplayModel =3D=3D 0x36 \ + ) \ + ) + +/** Shared. Model Specific Platform ID (R). =20 @param ECX MSR_ATOM_PLATFORM_ID (0x00000017) diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/In= clude/Register/Msr/BroadwellMsr.h index 1c3c2dc..90bd523 100644 --- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,25 @@ #include =20 /** + Is Intel processors based on the Broadwell microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x3D || \ + DisplayModel =3D=3D 0x47 || \ + DisplayModel =3D=3D 0x4F || \ + DisplayModel =3D=3D 0x56 \ + ) \ + ) + +/** Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.". =20 diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Includ= e/Register/Msr/Core2Msr.h index 9f0e790..9ebca5e 100644 --- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,23 @@ #include =20 /** + Is Intel(R) Core(TM) 2 Processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x0F || \ + DisplayModel =3D=3D 0x17 \ + ) \ + ) + +/** Shared. Model Specific Platform ID (R). =20 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017) diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include= /Register/Msr/CoreMsr.h index 0902aa9..4897c74 100644 --- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel Core Solo and Intel Core Duo Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x0E \ + ) \ + ) + +/** Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 3= 5-2. =20 @param ECX MSR_CORE_P5_MC_ADDR (0x00000000) diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Inc= lude/Register/Msr/GoldmontMsr.h index 58b9c57..5730918 100644 --- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel Atom processors based on the Goldmont microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x5C \ + ) \ + ) + +/** Core. Control Features in Intel 64Processor (R/W). =20 @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A) diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Inc= lude/Register/Msr/HaswellEMsr.h index 7b190b5..b737a9e 100644 --- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel processors based on the Haswell-E microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x3F \ + ) \ + ) + +/** Package. Configured State of Enabled Processor Core Count and Logical Processor Count (RO) - After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical processors in= the diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Incl= ude/Register/Msr/HaswellMsr.h index 8bf2c38..3cd1584 100644 --- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,24 @@ #include =20 /** + Is Intel processors based on the Haswell microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x3C || \ + DisplayModel =3D=3D 0x45 || \ + DisplayModel =3D=3D 0x46 \ + ) \ + ) + +/** Package. =20 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE) diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/In= clude/Register/Msr/IvyBridgeMsr.h index 41cbd2e..9eb0799 100644 --- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel processors based on the Ivy Bridge microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x3A \ + ) \ + ) + +/** Package. See http://biosbits.org. =20 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE) diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Incl= ude/Register/Msr/NehalemMsr.h index 20e60df..94aebba 100644 --- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,25 @@ #include =20 /** + Is Intel processors based on the Nehalem microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x1A || \ + DisplayModel =3D=3D 0x1E || \ + DisplayModel =3D=3D 0x1F || \ + DisplayModel =3D=3D 0x2E \ + ) \ + ) + +/** Package. Model Specific Platform ID (R). =20 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017) diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/R= egister/Msr/P6Msr.h index ef90800..aec2e2c 100644 --- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,27 @@ #include =20 /** + Is P6 Family Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x03 || \ + DisplayModel =3D=3D 0x05 || \ + DisplayModel =3D=3D 0x07 || \ + DisplayModel =3D=3D 0x08 || \ + DisplayModel =3D=3D 0x0A || \ + DisplayModel =3D=3D 0x0B \ + ) \ + ) + +/** See Section 35.22, "MSRs in Pentium Processors.". =20 @param ECX MSR_P6_P5_MC_ADDR (0x00000000) diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Inc= lude/Register/Msr/Pentium4Msr.h index 6cf68b2..8922d56 100644 --- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,19 @@ #include =20 /** + Is Pentium(R) 4 Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x0F \ + ) + +/** 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range Determination.". =20 diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Inc= lude/Register/Msr/PentiumMMsr.h index 294a381..70d54c8 100644 --- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Pentium M Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x0D \ + ) \ + ) + +/** See Section 35.22, "MSRs in Pentium Processors.". =20 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000) diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Incl= ude/Register/Msr/PentiumMsr.h index cd846ea..9b2578b 100644 --- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,24 @@ #include =20 /** + Is Pentium Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x05 && \ + ( \ + DisplayModel =3D=3D 0x01 || \ + DisplayModel =3D=3D 0x02 || \ + DisplayModel =3D=3D 0x04 \ + ) \ + ) + +/** See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling= .". =20 @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000) diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/= Include/Register/Msr/SandyBridgeMsr.h index 1819ecb..c8a0b97 100644 --- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,23 @@ #include =20 /** + Is Intel processors based on the Sandy Bridge microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x2A || \ + DisplayModel =3D=3D 0x2D \ + ) \ + ) + +/** Thread. SMI Counter (R/O). =20 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034) diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/I= nclude/Register/Msr/SilvermontMsr.h index b3b6b76..ec09bf3 100644 --- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,26 @@ #include =20 /** + Is Intel processors based on the Silvermont microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x37 || \ + DisplayModel =3D=3D 0x4A || \ + DisplayModel =3D=3D 0x4D || \ + DisplayModel =3D=3D 0x5A || \ + DisplayModel =3D=3D 0x5D \ + ) \ + ) + +/** Module. Model Specific Platform ID (R). =20 @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017) diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Incl= ude/Register/Msr/SkylakeMsr.h index 23ca3e1..7166e5f 100644 --- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,23 @@ #include =20 /** + Is Intel processors based on the Skylake microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x4E || \ + DisplayModel =3D=3D 0x5E \ + ) \ + ) + +/** Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = =3D 0, RW if MSR_PLATFORM_INFO.[28] =3D 1. =20 diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Inc= lude/Register/Msr/Xeon5600Msr.h index ea22e22..ad7128a 100644 --- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,23 @@ #include =20 /** + Is Intel(R) Xeon(R) Processor Series 5600? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x25 || \ + DisplayModel =3D=3D 0x2C \ + ) \ + ) + +/** Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a= #GP handler to handle unsuccessful read of this MSR. =20 diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Includ= e/Register/Msr/XeonDMsr.h index 5e7e13a..7b31288 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,23 @@ #include =20 /** + Is Intel(R) Xeon(R) Processor D product Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x4F || \ + DisplayModel =3D=3D 0x56 \ + ) \ + ) + +/** Package. Protected Processor Inventory Number Enable Control (R/W). =20 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E) diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Inclu= de/Register/Msr/XeonE7Msr.h index d14ef21..d509660 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel(R) Xeon(R) Processor E7 Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x2F \ + ) \ + ) + +/** Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a= #GP handler to handle unsuccessful read of this MSR. =20 diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Incl= ude/Register/Msr/XeonPhiMsr.h index 853d83b..43354d1 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -27,6 +27,22 @@ #include =20 /** + Is Intel(R) Xeon(R) Phi(TM) processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily =3D=3D 0x06 && \ + ( \ + DisplayModel =3D=3D 0x57 \ + ) \ + ) + +/** Thread. SMI Counter (R/O). =20 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034) --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel