From nobody Sat Nov 2 14:24:24 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1489048571243151.27594227550674; Thu, 9 Mar 2017 00:36:11 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 067D18038C; Thu, 9 Mar 2017 00:36:09 -0800 (PST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C1A1E80289 for ; Thu, 9 Mar 2017 00:36:07 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Mar 2017 00:36:07 -0800 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2017 00:36:06 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,268,1486454400"; d="scan'208";a="1139930897" From: Jeff Fan To: edk2-devel@lists.01.org Date: Thu, 9 Mar 2017 16:35:43 +0800 Message-Id: <20170309083553.6016-2-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170309083553.6016-1-jeff.fan@intel.com> References: <20170309083553.6016-1-jeff.fan@intel.com> Subject: [edk2] [PATCH 01/11] UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Feng Tian MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32b= it PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry. This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and make RegisterTableEntry is fixed length. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 6 +++--- UefiCpuPkg/Include/AcpiCpuData.h | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/= CpuS3Data.c index 3489b95..07c7102 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so thi= s module does not support hot plug CPUs. This module can be copied into a CPU specific pack= age and customized if these additional features are required. =20 -Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2015, Red Hat, Inc. =20 This program and the accompanying materials @@ -246,12 +246,12 @@ CpuS3DataInitialize ( RegisterTable[Index].InitialApicId =3D (UINT32)ProcessorInfoBuffe= r.ProcessorId; RegisterTable[Index].TableLength =3D 0; RegisterTable[Index].AllocatedSize =3D 0; - RegisterTable[Index].RegisterTableEntry =3D NULL; + RegisterTable[Index].RegisterTableEntry =3D 0; =20 RegisterTable[NumberOfCpus + Index].InitialApicId =3D (UINT32)Pro= cessorInfoBuffer.ProcessorId; RegisterTable[NumberOfCpus + Index].TableLength =3D 0; RegisterTable[NumberOfCpus + Index].AllocatedSize =3D 0; - RegisterTable[NumberOfCpus + Index].RegisterTableEntry =3D NULL; + RegisterTable[NumberOfCpus + Index].RegisterTableEntry =3D 0; } AcpiCpuData->RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Re= gisterTable; AcpiCpuData->PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(R= egisterTable + NumberOfCpus); diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index 12e9692..130eb90 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -1,7 +1,7 @@ /** @file Definitions for CPU S3 data. =20 -Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -55,10 +55,10 @@ typedef struct { // UINT32 InitialApicId; // - // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be + // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer= must be // allocated below 4GB from memory of type EfiACPIMemoryNVS. // - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; + EFI_PHYSICAL_ADDRESS RegisterTableEntry; } CPU_REGISTER_TABLE; =20 // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 532b7c4..12efc1f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file Code for Processor S3 restoration =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -826,13 +826,12 @@ CopyRegisterTable ( =20 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOf= Cpus * sizeof (CPU_REGISTER_TABLE)); for (Index =3D 0; Index < NumberOfCpus; Index++) { - DestinationRegisterTableList[Index].RegisterTableEntry =3D AllocatePoo= l (DestinationRegisterTableList[Index].AllocatedSize); - ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry !=3D NU= LL); - CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, Sourc= eRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[= Index].AllocatedSize); + RegisterTableEntry =3D AllocatePool (DestinationRegisterTableList[Inde= x].AllocatedSize); + ASSERT (RegisterTableEntry !=3D NULL); + CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[In= dex].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize); // // Go though all MSRs in register table to initialize MSR spin lock // - RegisterTableEntry =3D DestinationRegisterTableList[Index].RegisterTab= leEntry; for (Index1 =3D 0; Index1 < DestinationRegisterTableList[Index].TableL= ength; Index1++, RegisterTableEntry++) { if ((RegisterTableEntry->RegisterType =3D=3D Msr) && (RegisterTableE= ntry->ValidBitLength < 64)) { // @@ -841,6 +840,7 @@ CopyRegisterTable ( InitMsrSpinLockByIndex (RegisterTableEntry->Index); } } + DestinationRegisterTableList[Index].RegisterTableEntry =3D (EFI_PHYSIC= AL_ADDRESS)(UINTN)RegisterTableEntry; } } =20 --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel