From nobody Sat Nov 2 14:24:37 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487579899883706.6336893467641; Mon, 20 Feb 2017 00:38:19 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1993F821E8; Mon, 20 Feb 2017 00:38:17 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EBD1C821E7 for ; Mon, 20 Feb 2017 00:38:15 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 20 Feb 2017 00:38:15 -0800 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by fmsmga004.fm.intel.com with ESMTP; 20 Feb 2017 00:38:14 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,185,1484035200"; d="scan'208";a="227414756" From: Jeff Fan To: edk2-devel@lists.01.org Date: Mon, 20 Feb 2017 16:38:08 +0800 Message-Id: <20170220083808.27256-1-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 Subject: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod value X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Feng Tian MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current CpuGetTimerValue() implementation return hard code TimerPeriod valu= e. We could calculate the actual TimerPeriod value over period of time (100us) at= the first time invoking CpuGetTimerValue() and save the TimerPeriod value into = one global variable to avoid delay at the next CpuGetTimerValue() invoking. https://bugzilla.tianocore.org/show_bug.cgi?id=3D382 Cc: Feng Tian Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan Reviewed-by: Feng Tian --- UefiCpuPkg/CpuDxe/CpuDxe.c | 26 +++++++++++++++++++++++--- UefiCpuPkg/CpuDxe/CpuDxe.h | 3 ++- UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 ++- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index f6d0a67..9fb6d76 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -1,7 +1,7 @@ /** @file CPU DXE Module to produce CPU ARCH Protocol. =20 - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -23,6 +23,7 @@ EFI_HANDLE mCpuHandle =3D NULL; BOOLEAN mIsFlushingGCD; UINT64 mValidMtrrAddressMask =3D MTRR_LIB_CACHE_VALID_A= DDRESS; UINT64 mValidMtrrBitsMask =3D MTRR_LIB_MSR_VALID_MAS= K; +UINT64 mTimerPeriod =3D 0; =20 FIXED_MTRR mFixedMtrrTable[] =3D { { @@ -293,6 +294,9 @@ CpuGetTimerValue ( OUT UINT64 *TimerPeriod OPTIONAL ) { + UINT64 BeginValue; + UINT64 EndValue; + if (TimerValue =3D=3D NULL) { return EFI_INVALID_PARAMETER; } @@ -304,10 +308,26 @@ CpuGetTimerValue ( *TimerValue =3D AsmReadTsc (); =20 if (TimerPeriod !=3D NULL) { + if (mTimerPeriod =3D=3D 0) { + // + // Read time stamp counter before and after delay of 100 microseconds // - // BugBug: Hard coded. Don't know how to do this generically + BeginValue =3D AsmReadTsc (); + MicroSecondDelay (100); + EndValue =3D AsmReadTsc (); // - *TimerPeriod =3D 1000000000; + // Calculate the actual frequency + // + mTimerPeriod =3D DivU64x64Remainder ( + MultU64x32 ( + 1000 * 1000 * 1000, + 100 + ), + EndValue - BeginValue, + NULL + ); + } + *TimerPeriod =3D mTimerPeriod; } =20 return EFI_SUCCESS; diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h index 6dd0ad3..27ad45b 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.h +++ b/UefiCpuPkg/CpuDxe/CpuDxe.h @@ -1,7 +1,7 @@ /** @file CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol. =20 - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -39,6 +39,7 @@ #include #include #include +#include =20 #include #include diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index bf389bb..3cedce1 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,7 +1,7 @@ ## @file # CPU driver installs CPU Architecture Protocol and CPU MP protocol. # -# Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -44,6 +44,7 @@ HobLib ReportStatusCodeLib MpInitLib + TimerLib =20 [Sources] CpuDxe.c --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel