From nobody Sat Nov 2 16:22:58 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1487283291705579.2837294131165; Thu, 16 Feb 2017 14:14:51 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7AD9C8211A; Thu, 16 Feb 2017 14:14:43 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BBC7C820F7 for ; Thu, 16 Feb 2017 14:14:40 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.29.56]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v1GMEbK2013954; Thu, 16 Feb 2017 22:14:38 GMT X-Original-To: edk2-devel@ml01.01.org From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 16 Feb 2017 22:14:27 +0000 Message-Id: <20170216221431.280072-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170216221431.280072-1-evan.lloyd@arm.com> References: <20170216221431.280072-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 1/5] ArmPkg: Tidy GIC code before changes. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Harkin , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Evan Lloyd This change is purely cosmetic, to tidy some code before change. Mods involve: Reflow overlength comments. Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd Signed-off-by: Girish Pathak --- Notes: v2: Following comments on the v1 series of patches, some changes were extracted here to make the actual edits more visible. - 2017 [Leif] - Line splits [Leif] (comments about "1 per line") - STATIC [Leif] ArmPkg/Drivers/ArmGic/ArmGicDxe.h | 12 +-- ArmPkg/Include/Library/ArmGicLib.h | 29 ++++--- ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 36 +++++---- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 72 +++++++++++++-= --- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 57 +++++++++----- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 81 +++++++++++++-= ------ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 12 +-- 7 files changed, 195 insertions(+), 104 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmG= icDxe.h index af33aa90b00c6775e10a831d63ed707394862362..1018f2004e75d879a72c2d6bf37= b64051e720d12 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -28,9 +28,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. extern UINTN mGicNumInterrupts; extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; =20 -// + // Common API -// + EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, @@ -46,18 +46,18 @@ RegisterInterruptSource ( IN HARDWARE_INTERRUPT_HANDLER Handler ); =20 -// + // GicV2 API -// + EFI_STATUS GicV2DxeInitialize ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ); =20 -// + // GicV3 API -// + EFI_STATUS GicV3DxeInitialize ( IN EFI_HANDLE ImageHandle, diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/Ar= mGicLib.h index 4364f3ffef464596f64cf59881d703cf54cf0ddd..f7b546895d116f81c65a853fcdb= 067ec7601b2da 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -17,9 +17,9 @@ =20 #include =20 -// + // GIC Distributor -// + #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Regist= er @@ -51,9 +51,9 @@ #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) =20 -// + // GIC Redistributor -// + =20 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB @@ -65,9 +65,9 @@ #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers =20 -// + // GIC Cpu interface -// + #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register #define ARM_GIC_ICCBPR 0x08 // Binary Point Register @@ -104,9 +104,9 @@ ArmGicGetInterfaceIdentification ( IN INTN GicInterruptInterfaceBase ); =20 -// + // GIC Secure interfaces -// + VOID EFIAPI ArmGicSetupNonSecure ( @@ -170,7 +170,8 @@ ArmGicSendSgiTo ( * in the GICv3 the register value is only the InterruptId. * * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface - * @param InterruptId InterruptId read from the Interrupt = Acknowledge Register + * @param InterruptId InterruptId read from the Interrupt + * Acknowledge Register * * @retval value returned by the Interrupt Acknowledge Register * @@ -220,12 +221,12 @@ ArmGicIsInterruptEnabled ( IN UINTN Source ); =20 -// // GIC revision 2 specific declarations -// =20 -// Interrupts from 1020 to 1023 are considered as special interrupts (eg: = spurious interrupts) -#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >=3D 1020) = && ((Interrupt) <=3D 1023)) +// Interrupts from 1020 to 1023 are considered as special interrupts +// (eg: spurious interrupts) +#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \ + (((Interrupt) >=3D 1020) && ((Interrupt) <=3D 1023)) =20 VOID EFIAPI @@ -260,9 +261,7 @@ ArmGicV2EndOfInterrupt ( IN UINTN Source ); =20 -// // GIC revision 3 specific declarations -// =20 #define ICC_SRE_EL2_SRE (1 << 0) =20 diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGi= c/ArmGicCommonDxe.c index be77b8361c5af033fd2889cdb48902af867f321d..88cb455b75bb8e8cb22157643a3= 92403ce93129d 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -28,14 +28,14 @@ ExitBootServicesEvent ( IN VOID *Context ); =20 -// + // Making this global saves a few bytes in image size -// + EFI_HANDLE gHardwareInterruptHandle =3D NULL; =20 -// + // Notifications -// + EFI_EVENT EfiExitBootServicesEvent =3D (EFI_EVENT)NULL; =20 // Maximum Number of Interrupts @@ -96,7 +96,8 @@ InstallAndRegisterInterruptService ( EFI_CPU_ARCH_PROTOCOL *Cpu; =20 // Initialize the array for the Interrupt Handlers - gRegisteredInterruptHandlers =3D (HARDWARE_INTERRUPT_HANDLER*)AllocateZe= roPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); + gRegisteredInterruptHandlers =3D (HARDWARE_INTERRUPT_HANDLER*) + AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrup= ts); if (gRegisteredInterruptHandlers =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } @@ -110,32 +111,41 @@ InstallAndRegisterInterruptService ( return Status; } =20 - // + // Get the CPU protocol that this driver requires. - // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&Cpu); if (EFI_ERROR (Status)) { return Status; } =20 - // + // Unregister the default exception handler. - // + Status =3D Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, N= ULL); if (EFI_ERROR (Status)) { return Status; } =20 - // + // Register to receive interrupts - // - Status =3D Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, I= nterruptHandler); + Status =3D Cpu->RegisterInterruptHandler ( + Cpu, + ARM_ARCH_EXCEPTION_IRQ, + InterruptHandler + ); if (EFI_ERROR (Status)) { return Status; } =20 // Register for an ExitBootServicesEvent - Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, = ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); + Status =3D gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + ExitBootServicesEvent, + NULL, + &EfiExitBootServicesEvent + ); =20 return Status; } diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmG= icLib.c index e658e9bff5d8107b3914bdf1e9e1e51a4e4d4cd7..852330b80db9726f860f6868f7e= 90d48756b6e58 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -55,13 +55,17 @@ GicGetCpuRedistributorBase ( UINTN GicCpuRedistributorBase; =20 MpId =3D ArmReadMpidr (); - // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:= 23], Affinity3[24:32] + // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], + // Affinity2[16:23], Affinity3[24:32] // whereas Affinity3 is defined at [32:39] in MPIDR - CpuAffinity =3D (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2))= | ((MpId & ARM_CORE_AFF3) >> 8); + CpuAffinity =3D (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) + | ((MpId & ARM_CORE_AFF3) >> 8); =20 if (Revision =3D=3D ARM_GIC_ARCH_REVISION_3) { - // 2 x 64KB frame: Redistributor control frame + SGI Control & Generat= ion frame - GicRedistributorGranularity =3D ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_SG= I_PPI_FRAME_SIZE; + // 2 x 64KB frame: + // Redistributor control frame + SGI Control & Generation frame + GicRedistributorGranularity =3D ARM_GICR_CTLR_FRAME_SIZE + + ARM_GICR_SGI_PPI_FRAME_SIZE; } else { ASSERT_EFI_ERROR (EFI_UNSUPPORTED); return 0; @@ -112,7 +116,10 @@ ArmGicSendSgiTo ( IN INTN SgiId ) { - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & = 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); + MmioWrite32 ( + GicDistributorBase + ARM_GIC_ICDSGIR, + ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | Sg= iId + ); } =20 /* @@ -123,7 +130,8 @@ ArmGicSendSgiTo ( * in the GICv3 the register value is only the InterruptId. * * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface - * @param InterruptId InterruptId read from the Interrupt = Acknowledge Register + * @param InterruptId InterruptId read from the Interrupt + * Acknowledge Register * * @retval value returned by the Interrupt Acknowledge Register * @@ -200,16 +208,28 @@ ArmGicEnableInterrupt ( FeaturePcdGet (PcdArmGicV3WithV2Legacy) || SourceIsSpi (Source)) { // Write set-enable register - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1= << RegShift); + MmioWrite32 ( + GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), + 1 << RegShift + ); } else { - GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (GicRedistribut= orBase, Revision); + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase ( + GicRedistributorBase, + Revision + ); if (GicCpuRedistributorBase =3D=3D 0) { ASSERT_EFI_ERROR (EFI_NOT_FOUND); return; } =20 // Write set-enable register - MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_= GICR_ISENABLER + (4 * RegOffset), 1 << RegShift); + MmioWrite32 ( + (GicCpuRedistributorBase + + ARM_GICR_CTLR_FRAME_SIZE + + ARM_GICR_ISENABLER + + (4 * RegOffset)), + 1 << RegShift + ); } } =20 @@ -235,15 +255,27 @@ ArmGicDisableInterrupt ( FeaturePcdGet (PcdArmGicV3WithV2Legacy) || SourceIsSpi (Source)) { // Write clear-enable register - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1= << RegShift); + MmioWrite32 ( + GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), + 1 << RegShift + ); } else { - GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (GicRedistribut= orBase, Revision); + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase ( + GicRedistributorBase, + Revision + ); if (GicCpuRedistributorBase =3D=3D 0) { return; } =20 // Write clear-enable register - MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_= GICR_ICENABLER + (4 * RegOffset), 1 << RegShift); + MmioWrite32 ( + (GicCpuRedistributorBase + + ARM_GICR_CTLR_FRAME_SIZE + + ARM_GICR_ICENABLER + + (4 * RegOffset)), + 1 << RegShift + ); } } =20 @@ -269,15 +301,25 @@ ArmGicIsInterruptEnabled ( if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) || SourceIsSpi (Source)) { - Interrupts =3D ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4= * RegOffset)) & (1 << RegShift)) !=3D 0); + Interrupts =3D ((MmioRead32 ( + GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset) + ) + & (1 << RegShift)) !=3D 0); } else { - GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (GicRedistribut= orBase, Revision); + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase ( + GicRedistributorBase, + Revision + ); if (GicCpuRedistributorBase =3D=3D 0) { return 0; } =20 // Read set-enable register - Interrupts =3D MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRA= ME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset)); + Interrupts =3D MmioRead32 ( + GicCpuRedistributorBase + + ARM_GICR_CTLR_FRAME_SIZE + + ARM_GICR_ISENABLER + + (4 * RegOffset)); } =20 return ((Interrupts & (1 << RegShift)) !=3D 0); diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV2/ArmGicV2Dxe.c index b9ecd5543a3e2e0b00fffbcf5543a60567bb5dde..50ec90207b515d849cbf64f0a4b= 0d639b3868e60 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -2,7 +2,7 @@ =20 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
-Portions copyright (c) 2011-2016, ARM Ltd. All rights reserved.
+Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License @@ -43,6 +43,7 @@ STATIC UINT32 mGicDistributorBase; @retval EFI_UNSUPPORTED Source interrupt is not supported =20 **/ +STATIC EFI_STATUS EFIAPI GicV2EnableInterruptSource ( @@ -70,6 +71,7 @@ GicV2EnableInterruptSource ( @retval EFI_UNSUPPORTED Source interrupt is not supported =20 **/ +STATIC EFI_STATUS EFIAPI GicV2DisableInterruptSource ( @@ -98,6 +100,7 @@ GicV2DisableInterruptSource ( @retval EFI_UNSUPPORTED Source interrupt is not supported =20 **/ +STATIC EFI_STATUS EFIAPI GicV2GetInterruptSourceState ( @@ -127,6 +130,7 @@ GicV2GetInterruptSourceState ( @retval EFI_UNSUPPORTED Source interrupt is not supported =20 **/ +STATIC EFI_STATUS EFIAPI GicV2EndOfInterrupt ( @@ -147,13 +151,15 @@ GicV2EndOfInterrupt ( EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occu= rs. =20 @param InterruptType Defines the type of interrupt or exception that - occurred on the processor.This parameter is pro= cessor architecture specific. + occurred on the processor.This parameter is + processor architecture specific. @param SystemContext A pointer to the processor context when the interrupt occurred on the processor. =20 @return None =20 **/ +STATIC VOID EFIAPI GicV2IrqInterruptHandler ( @@ -166,7 +172,8 @@ GicV2IrqInterruptHandler ( =20 GicInterrupt =3D ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBas= e); =20 - // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than = the number of interrupt (ie: Spurious interrupt). + // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than = the + // number of interrupt (ie: Spurious interrupt). if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >=3D mGicNumInterrupts) { // The special interrupt do not need to be acknowledge return; @@ -182,9 +189,9 @@ GicV2IrqInterruptHandler ( } } =20 -// + // The protocol instance produced by this driver -// + EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol =3D { RegisterInterruptSource, GicV2EnableInterruptSource, @@ -196,12 +203,13 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2P= rotocol =3D { /** Shutdown our hardware =20 - DXE Core will disable interrupts and turn off the timer and disable inte= rrupts - after all the event handlers have run. + DXE Core will disable interrupts and turn off the timer and disable + interrupts after all the event handlers have run. =20 @param[in] Event The Event that is being processed @param[in] Context Event Context **/ +STATIC VOID EFIAPI GicV2ExitBootServicesEvent ( @@ -256,7 +264,8 @@ GicV2DxeInitialize ( UINTN RegShift; UINT32 CpuTarget; =20 - // Make sure the Interrupt Controller Protocol is not already installed = in the system. + // Make sure the Interrupt Controller Protocol is not already installed = in + // the system. ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid= ); =20 mGicInterruptInterfaceBase =3D PcdGet64 (PcdGicInterruptInterfaceBase); @@ -276,25 +285,28 @@ GicV2DxeInitialize ( ); } =20 - // + // Targets the interrupts to the Primary Cpu - // =20 - // Only Primary CPU will run this code. We can identify our GIC CPU ID b= y reading - // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are = banked to each - // connected CPU. These 8 registers hold the CPU targets fields for inte= rrupts 0-31. - // More Info in the GIC Specification about "Interrupt Processor Targets= Registers" - // - // Read the first Interrupt Processor Targets Register (that corresponds= to the 4 - // first SGIs) + // Only Primary CPU will run this code. We can identify our GIC CPU ID by + // reading the GIC Distributor Target register. The 8 first GICD_ITARGET= SRn + // are banked to each connected CPU. These 8 registers hold the CPU targ= ets + // fields for interrupts 0-31. More Info in the GIC Specification about + // "Interrupt Processor Targets Registers" + + // Read the first Interrupt Processor Targets Register (that corresponds= to + // the 4 first SGIs) CpuTarget =3D MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR); =20 - // The CPU target is a bit field mapping each CPU to a GIC CPU Interface= . This value - // is 0 when we run on a uniprocessor platform. + // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. + // This value is 0 when we run on a uniprocessor platform. if (CpuTarget !=3D 0) { // The 8 first Interrupt Processor Targets Registers are read-only for (Index =3D 8; Index < (mGicNumInterrupts / 4); Index++) { - MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), Cp= uTarget); + MmioWrite32 ( + mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), + CpuTarget + ); } } =20 @@ -311,7 +323,10 @@ GicV2DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2Ex= itBootServicesEvent); + &gHardwareInterruptV2Protocol, + GicV2IrqInterruptHandler, + GicV2ExitBootServicesEvent + ); =20 return Status; } diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV3/ArmGicV3Dxe.c index 8af97a93b1889b33978a7c7fb2a8417c83139142..69b2d8d794e151e25f06cbea079= e2796d9793a43 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -33,6 +33,7 @@ STATIC UINTN mGicRedistributorsBase; @retval EFI_DEVICE_ERROR Hardware could not be programmed. =20 **/ +STATIC EFI_STATUS EFIAPI GicV3EnableInterruptSource ( @@ -60,6 +61,7 @@ GicV3EnableInterruptSource ( @retval EFI_DEVICE_ERROR Hardware could not be programmed. =20 **/ +STATIC EFI_STATUS EFIAPI GicV3DisableInterruptSource ( @@ -88,6 +90,7 @@ GicV3DisableInterruptSource ( @retval EFI_DEVICE_ERROR InterruptState is not valid =20 **/ +STATIC EFI_STATUS EFIAPI GicV3GetInterruptSourceState ( @@ -101,7 +104,10 @@ GicV3GetInterruptSourceState ( return EFI_UNSUPPORTED; } =20 - *InterruptState =3D ArmGicIsInterruptEnabled (mGicDistributorBase, mGicR= edistributorsBase, Source); + *InterruptState =3D ArmGicIsInterruptEnabled ( + mGicDistributorBase, + mGicRedistributorsBase, + Source); =20 return EFI_SUCCESS; } @@ -117,6 +123,7 @@ GicV3GetInterruptSourceState ( @retval EFI_DEVICE_ERROR Hardware could not be programmed. =20 **/ +STATIC EFI_STATUS EFIAPI GicV3EndOfInterrupt ( @@ -137,13 +144,15 @@ GicV3EndOfInterrupt ( EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occu= rs. =20 @param InterruptType Defines the type of interrupt or exception that - occurred on the processor.This parameter is pro= cessor architecture specific. + occurred on the processor. This parameter is + processor architecture specific. @param SystemContext A pointer to the processor context when the interrupt occurred on the processor. =20 @return None =20 **/ +STATIC VOID EFIAPI GicV3IrqInterruptHandler ( @@ -173,9 +182,9 @@ GicV3IrqInterruptHandler ( } } =20 -// + // The protocol instance produced by this driver -// + EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol =3D { RegisterInterruptSource, GicV3EnableInterruptSource, @@ -242,17 +251,16 @@ GicV3DxeInitialize ( UINT64 CpuTarget; UINT64 MpId; =20 - // Make sure the Interrupt Controller Protocol is not already installed = in the system. + // Make sure the Interrupt Controller Protocol is not already installed = in + // the system. ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid= ); =20 mGicDistributorBase =3D PcdGet64 (PcdGicDistributorBase); mGicRedistributorsBase =3D PcdGet64 (PcdGicRedistributorsBase); mGicNumInterrupts =3D ArmGicGetMaxNumInterrupts (mGicDistributorBas= e); =20 - // // We will be driving this GIC in native v3 mode, i.e., with Affinity // Routing enabled. So ensure that the ARE bit is set. - // if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); } @@ -270,51 +278,65 @@ GicV3DxeInitialize ( ); } =20 - // // Targets the interrupts to the Primary Cpu - // =20 if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { - // Only Primary CPU will run this code. We can identify our GIC CPU ID= by reading - // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn ar= e banked to each - // connected CPU. These 8 registers hold the CPU targets fields for in= terrupts 0-31. - // More Info in the GIC Specification about "Interrupt Processor Targe= ts Registers" - // - // Read the first Interrupt Processor Targets Register (that correspon= ds to the 4 - // first SGIs) + // Only Primary CPU will run this code. We can identify our GIC CPU ID= by + // reading the GIC Distributor Target register. The 8 first + // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers + // hold the CPU targets fields for interrupts 0-31. More Info in the G= IC + // Specification about "Interrupt Processor Targets Registers" + + // Read the first Interrupt Processor Targets Register (that correspon= ds + // to the 4 first SGIs) CpuTarget =3D MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR); =20 - // The CPU target is a bit field mapping each CPU to a GIC CPU Interfa= ce. This value - // is 0 when we run on a uniprocessor platform. + // The CPU target is a bit field mapping each CPU to a GIC CPU Interfa= ce. + // This value is 0 when we run on a uniprocessor platform. if (CpuTarget !=3D 0) { // The 8 first Interrupt Processor Targets Registers are read-only for (Index =3D 8; Index < (mGicNumInterrupts / 4); Index++) { - MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), = CpuTarget); + MmioWrite32 ( + mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), + CpuTarget + ); } } } else { MpId =3D ArmReadMpidr (); - CpuTarget =3D MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | = ARM_CORE_AFF3); + CpuTarget =3D MpId & + (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_= AFF3); + + if ((MmioRead32 ( + mGicDistributorBase + ARM_GIC_ICDDCR + ) & ARM_GIC_ICDDCR_DS) !=3D 0) { =20 - if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDC= R_DS) !=3D 0) { - // // If the Disable Security (DS) control bit is set, we are dealing w= ith a // GIC that has only one security state. In this case, let's assume = we are // executing in non-secure state (which is appropriate for DXE modul= es) // and that no other firmware has performed any configuration on the= GIC. // This means we need to reconfigure all interrupts to non-secure Gr= oup 1 // first. - // - MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM= _GIC_ICDISR, 0xffffffff); + + MmioWrite32 ( + mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, + 0xffffffff + ); =20 for (Index =3D 32; Index < mGicNumInterrupts; Index +=3D 32) { - MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xf= fffffff); + MmioWrite32 ( + mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, + 0xffffffff + ); } } =20 // Route the SPIs to the primary CPU. SPIs start at the INTID 32 for (Index =3D 0; Index < (mGicNumInterrupts - 32); Index++) { - MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), C= puTarget | ARM_GICD_IROUTER_IRM); + MmioWrite32 ( + mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), + CpuTarget | ARM_GICD_IROUTER_IRM + ); } } =20 @@ -331,7 +353,10 @@ GicV3DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3Ex= itBootServicesEvent); + &gHardwareInterruptV3Protocol, + GicV3IrqInterruptHandler, + GicV3ExitBootServicesEvent + ); =20 return Status; } diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPk= g/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 54a1625a32137556b58fa93ddf7fbe4d0f22c786..6d102e25047253048ac555d6fb5= de7223d78f381 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -193,18 +193,18 @@ WatchdogSetTimerPeriod ( // Work out how many timer ticks will equate to TimerPeriod mNumTimerTicks =3D (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SE= COND; =20 - // + // If the number of required ticks is greater than the max number the // watchdog's offset register (WOR) can hold, we need to manually comput= e and // set the compare register (WCV) - // + if (mNumTimerTicks > MAX_UINT32) { - // + // We need to enable the watchdog *before* writing to the compare regi= ster, // because enabling the watchdog causes an "explicit refresh", which // clobbers the compare register (WCV). In order to make sure this doe= sn't // trigger an interrupt, set the offset to max. - // + Status =3D WatchdogWriteOffsetRegister (MAX_UINT32); if (EFI_ERROR (Status)) { return Status; @@ -302,11 +302,11 @@ GenericWatchdogEntry ( EFI_STATUS Status; EFI_HANDLE Handle; =20 - // + // Make sure the Watchdog Timer Architectural Protocol has not been inst= alled // in the system yet. // This will avoid conflicts with the universal watchdog - // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolG= uid); =20 mTimerFrequencyHz =3D ArmGenericTimerGetTimerFreq (); --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel