From nobody Sat Nov 2 14:36:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486668399936944.8297845387394; Thu, 9 Feb 2017 11:26:39 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A5C3C81FF5; Thu, 9 Feb 2017 11:26:34 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EA73281F3D for ; Thu, 9 Feb 2017 11:26:31 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.31.76]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v19JQSog006780; Thu, 9 Feb 2017 19:26:29 GMT X-Original-To: edk2-devel@ml01.01.org From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 9 Feb 2017 19:26:20 +0000 Message-Id: <20170209192623.262044-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170209192623.262044-1-evan.lloyd@arm.com> References: <20170209192623.262044-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 1/4] EmbeddedPkg: introduce HardwareInterrupt2 protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Harkin , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The existing HardwareInterrupt protocol lacks the method to configure the level/edge and polarity properties of an interrupt. So introduce a new protocol HardwareInterrupt2, and add some new members that allow the manipulation of those properties. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- EmbeddedPkg/EmbeddedPkg.dec | 1 + EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h | 181 ++++++++++++++++++= ++ 2 files changed, 182 insertions(+) diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index 2c2cf41103c282103c2a83ad9a105d0f6ac2e9a3..2464f715e68c8e0eb1214c0170f= b040830b88f06 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -58,6 +58,7 @@ [Guids.common] =20 [Protocols.common] gHardwareInterruptProtocolGuid =3D { 0x2890B3EA, 0x053D, 0x1643, { 0xAD= , 0x0C, 0xD6, 0x48, 0x08, 0xDA, 0x3F, 0xF1 } } + gHardwareInterrupt2ProtocolGuid =3D { 0x32898322, 0x2da1, 0x474a, { 0xba= , 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } } gEfiDebugSupportPeriodicCallbackProtocolGuid =3D { 0x9546e07c, 0x2cbb, 0= x4c88, { 0x98, 0x6c, 0xcd, 0x34, 0x10, 0x86, 0xf0, 0x44 } } gEfiEblAddCommandProtocolGuid =3D { 0xaeda2428, 0x9a22, 0x4637, { 0x9b= , 0x21, 0x54, 0x5e, 0x28, 0xfb, 0xb8, 0x29 } } gEmbeddedDeviceGuid =3D { 0xbf4b9d10, 0x13ec, 0x43dd, { 0x88, 0x80, 0x= e9, 0xb, 0x71, 0x8f, 0x27, 0xde } } diff --git a/EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h b/EmbeddedPk= g/Include/Protocol/HardwareInterrupt2.h new file mode 100644 index 0000000000000000000000000000000000000000..61acdaac4341951b8c191685849= 0a815cf94dc99 --- /dev/null +++ b/EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h @@ -0,0 +1,181 @@ +/** @file + + Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __HARDWARE_INTERRUPT2_H__ +#define __HARDWARE_INTERRUPT2_H__ + +#include + +// 22838932-1a2d-4a47-aaba-f3f7cf569470 + +#define EFI_HARDWARE_INTERRUPT2_PROTOCOL_GUID \ + { 0x32898322, 0x2da1, 0x474a, { 0xba, 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94= , 0x70 } } + +typedef enum { + EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_LOW, + EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH, + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_FALLING, + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING, +} EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE; + +typedef struct _EFI_HARDWARE_INTERRUPT2_PROTOCOL EFI_HARDWARE_INTERRUPT2_P= ROTOCOL; + +/** + Register Handler for the specified interrupt source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param Handler Callback for interrupt. NULL to unregister + + @retval EFI_SUCCESS Source was updated to support Handler. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_REGISTER) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN HARDWARE_INTERRUPT_HANDLER Handler + ); + + +/** + Enable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt enabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_ENABLE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + + + +/** + Disable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt disabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_DISABLE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + + +/** + Return current state of interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param InterruptState TRUE: source enabled, FALSE: source disabled. + + @retval EFI_SUCCESS InterruptState is valid + @retval EFI_DEVICE_ERROR InterruptState is not valid + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_INTERRUPT_STATE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN BOOLEAN *InterruptState + ); + +/** + Signal to the hardware that the End Of Intrrupt state + has been reached. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt EOI'ed. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_END_OF_INTERRUPT) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + +/** + Return the configured trigger type for an interrupt source + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param TriggerType The configured trigger type + + @retval EFI_SUCCESS Operation successful + @retval EFI_DEVICE_ERROR Information could not be returned + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_GET_TRIGGER_TYPE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ); + + +/** + Configure the trigger type for an interrupt source + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param TriggerType The trigger type to configure + + @retval EFI_SUCCESS Operation successful + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_SET_TRIGGER_TYPE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ); + +struct _EFI_HARDWARE_INTERRUPT2_PROTOCOL { + HARDWARE_INTERRUPT2_REGISTER RegisterInterruptSource; + HARDWARE_INTERRUPT2_ENABLE EnableInterruptSource; + HARDWARE_INTERRUPT2_DISABLE DisableInterruptSource; + HARDWARE_INTERRUPT2_INTERRUPT_STATE GetInterruptSourceState; + HARDWARE_INTERRUPT2_END_OF_INTERRUPT EndOfInterrupt; + + // v2 members + HARDWARE_INTERRUPT2_GET_TRIGGER_TYPE GetTriggerType; + HARDWARE_INTERRUPT2_SET_TRIGGER_TYPE SetTriggerType; +}; + +extern EFI_GUID gHardwareInterrupt2ProtocolGuid; + +#endif --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:36:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486668394880170.37617607665322; Thu, 9 Feb 2017 11:26:34 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 06C9181F3D; Thu, 9 Feb 2017 11:26:33 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BBA8481F39 for ; Thu, 9 Feb 2017 11:26:31 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.31.76]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v19JQSoh006780; Thu, 9 Feb 2017 19:26:29 GMT X-Original-To: edk2-devel@ml01.01.org From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 9 Feb 2017 19:26:21 +0000 Message-Id: <20170209192623.262044-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170209192623.262044-1-evan.lloyd@arm.com> References: <20170209192623.262044-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 2/4] ArmPkg/ArmGicDxe: expose HardwareInterrupt2 protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Harkin , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 1 + ArmPkg/Drivers/ArmGic/ArmGicDxe.h | 2 ++ ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 2 ++ ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 38 +++++++++++++++++++- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 37 ++++++++++++++++++- 5 files changed, 78 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/Ar= mGicDxe.inf index e554301c4b28022c805f69242cf6ee979d19abc2..69390638a9afb6aeccad510e7b5= 72450568c1409 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -48,6 +48,7 @@ [LibraryClasses] =20 [Protocols] gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid gEfiCpuArchProtocolGuid =20 [Pcd.common] diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmG= icDxe.h index af33aa90b00c6775e10a831d63ed707394862362..2633e1ea194fa67511861a4165d= 54dad99a6f39b 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -24,6 +24,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include #include +#include =20 extern UINTN mGicNumInterrupts; extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; @@ -34,6 +35,7 @@ extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptH= andlers; EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_EVENT_NOTIFY ExitBootServicesEvent ); diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGi= c/ArmGicCommonDxe.c index be77b8361c5af033fd2889cdb48902af867f321d..ef6746f1ad7afba5bba30fc1777= 4987cf17121b6 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -88,6 +88,7 @@ RegisterInterruptSource ( EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_EVENT_NOTIFY ExitBootServicesEvent ) @@ -104,6 +105,7 @@ InstallAndRegisterInterruptService ( Status =3D gBS->InstallMultipleProtocolInterfaces ( &gHardwareInterruptHandle, &gHardwareInterruptProtocolGuid, InterruptProtocol, + &gHardwareInterrupt2ProtocolGuid, Interrupt2Protocol, NULL ); if (EFI_ERROR (Status)) { diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV2/ArmGicV2Dxe.c index b9ecd5543a3e2e0b00fffbcf5543a60567bb5dde..8c4d66125e2e8c7af9898f336ee= 742ed0aebf058 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -193,6 +193,41 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Pr= otocol =3D { GicV2EndOfInterrupt }; =20 +STATIC +EFI_STATUS +EFIAPI +GicV2GetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ) +{ + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +GicV2SetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ) +{ + return EFI_SUCCESS; +} + +STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol =3D { + (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt, + GicV2GetTriggerType, + GicV2SetTriggerType +}; + + /** Shutdown our hardware =20 @@ -311,7 +346,8 @@ GicV2DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2Ex= itBootServicesEvent); + &gHardwareInterruptV2Protocol, &gHardwareInterrupt2V2Protocol, + GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent); =20 return Status; } diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV3/ArmGicV3Dxe.c index 8af97a93b1889b33978a7c7fb2a8417c83139142..02deeef78b6d7737172a5992c6d= ecac43cfdd64a 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -184,6 +184,40 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Pr= otocol =3D { GicV3EndOfInterrupt }; =20 +STATIC +EFI_STATUS +EFIAPI +GicV3GetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ) +{ + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +GicV3SetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ) +{ + return EFI_SUCCESS; +} + +STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol =3D { + (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt, + GicV3GetTriggerType, + GicV3SetTriggerType +}; + /** Shutdown our hardware =20 @@ -331,7 +365,8 @@ GicV3DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3Ex= itBootServicesEvent); + &gHardwareInterruptV3Protocol, &gHardwareInterrupt2V3Protocol, + GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent); =20 return Status; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:36:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486668397935889.2109755223222; Thu, 9 Feb 2017 11:26:37 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6EE7D81F6D; Thu, 9 Feb 2017 11:26:33 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 03C1A81F3F for ; Thu, 9 Feb 2017 11:26:31 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.31.76]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v19JQSoi006780; Thu, 9 Feb 2017 19:26:29 GMT X-Original-To: edk2-devel@ml01.01.org From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 9 Feb 2017 19:26:22 +0000 Message-Id: <20170209192623.262044-4-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170209192623.262044-1-evan.lloyd@arm.com> References: <20170209192623.262044-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 3/4] ArmPkg/GenericWatchdogDxe: Set Watchdog interrupt type X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Harkin , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Utilise the new HardwareInterrupt2 protocol to adjust the Edje/Level characteristics of the Watchdog interrupt. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf | 4 +-- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 27 ++++++++++++= -------- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/Arm= Pkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf index fece14cc18315cd15510680c438288687b60c018..51d5c0042d84333b9fe66547c99= a8d8ed987f175 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -47,7 +47,7 @@ [Pcd.common] =20 [Protocols] gEfiWatchdogTimerArchProtocolGuid - gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid =20 [Depex] - gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPk= g/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 54a1625a32137556b58fa93ddf7fbe4d0f22c786..9ba9bf79c961b52dc9b448039a9= 186e069fc29f7 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -25,7 +25,8 @@ #include =20 #include -#include + +#include =20 #include "GenericWatchdog.h" =20 @@ -41,7 +42,7 @@ UINTN mTimerFrequencyHz =3D 0; // It is therefore stored here. 0 means the timer is not running. UINT64 mNumTimerTicks =3D 0; =20 -EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol; +EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; =20 EFI_STATUS WatchdogWriteOffsetRegister ( @@ -320,7 +321,7 @@ GenericWatchdogEntry ( if (!EFI_ERROR (Status)) { // Install interrupt handler Status =3D gBS->LocateProtocol ( - &gHardwareInterruptProtocolGuid, + &gHardwareInterrupt2ProtocolGuid, NULL, (VOID **)&mInterruptProtocol ); @@ -331,13 +332,19 @@ GenericWatchdogEntry ( WatchdogInterruptHandler ); if (!EFI_ERROR (Status)) { - // Install the Timer Architectural Protocol onto a new handle - Handle =3D NULL; - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTime= r, - NULL - ); + Status =3D mInterruptProtocol->SetTriggerType ( + mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2In= trNum), + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_R= ISING); + if (!EFI_ERROR (Status)) { + // Install the Timer Architectural Protocol onto a new handle + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTi= mer, + NULL + ); + } } } } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Nov 2 14:36:41 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486668402306337.32364508602984; Thu, 9 Feb 2017 11:26:42 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DF72182001; Thu, 9 Feb 2017 11:26:34 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 063FA81F4B for ; Thu, 9 Feb 2017 11:26:31 -0800 (PST) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.31.76]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v19JQSoj006780; Thu, 9 Feb 2017 19:26:30 GMT X-Original-To: edk2-devel@ml01.01.org From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Date: Thu, 9 Feb 2017 19:26:23 +0000 Message-Id: <20170209192623.262044-5-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170209192623.262044-1-evan.lloyd@arm.com> References: <20170209192623.262044-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 4/4] ArmPkg:Provide GetTriggerType/SetTriggerType functions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Harkin , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change implements GetTriggerType and SetTriggerType functions in ArmGicV2Dxe (GicV2GetTriggerType/GicV2SetTriggerType) and ArmGicV3Dxe (GicV3GetTriggerType/GicV3SetTriggerType) SetTriggerType configures the interrupt mode of an interrupt as edge sensitive or level sensitive. GetTriggerType function returns the mode of an interrupt. The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic relevance. NOTE: At this point the GICv3 code is not tested. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- ArmPkg/Include/Library/ArmGicLib.h | 4 + ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 165 ++++++++++++++++++-- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 159 +++++++++++++++++-- 3 files changed, 308 insertions(+), 20 deletions(-) diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/Ar= mGicLib.h index 4364f3ffef464596f64cf59881d703cf54cf0ddd..6610f356c20e73d84ff3ba51995= 6b426d97ef1eb 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -51,6 +51,10 @@ #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) =20 +// GICD_ICDICFR bits +#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt +#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt + // // GIC Redistributor // diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV2/ArmGicV2Dxe.c index 8c4d66125e2e8c7af9898f336ee742ed0aebf058..1f47403c6cdc7e8c0f6ac65d3b9= 5a562da6a2d32 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -29,6 +29,7 @@ Abstract: #define ARM_GIC_DEFAULT_PRIORITY 0x80 =20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol; =20 STATIC UINT32 mGicInterruptInterfaceBase; STATIC UINT32 mGicDistributorBase; @@ -193,19 +194,95 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2P= rotocol =3D { GicV2EndOfInterrupt }; =20 +/** + Calculate GICD_ICFGRn base address and corresponding bit + field Int_config[1] of the GIC distributor register. + + @param Source Hardware source of the interrupt. + @param RegAddress Corresponding GICD_ICFGRn base address. + @param BitNumber Bit number in the register to set/reset. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ STATIC EFI_STATUS +GicGetDistributorIntrCfgBaseAndBitField ( + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT UINTN *RegAddress, + OUT UINTN *BitNumber + ) +{ + UINTN RegOffset; + UINTN Field; + + if (Source >=3D mGicNumInterrupts) { + ASSERT(Source < mGicNumInterrupts); + return EFI_UNSUPPORTED; + } + + RegOffset =3D Source / 16; + Field =3D Source % 16; + *RegAddress =3D PcdGet64 (PcdGicDistributorBase) + + ARM_GIC_ICDICFR + + (4 * RegOffset); + *BitNumber =3D (Field * 2) + 1; + + return EFI_SUCCESS; +} + +/** + Get interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Returns interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +EFI_STATUS EFIAPI GicV2GetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, - IN HARDWARE_INTERRUPT_SOURCE Source, + IN HARDWARE_INTERRUPT_SOURCE Source, OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType ) { + UINTN RegAddress; + UINTN BitNumber; + EFI_STATUS Status; + + RegAddress =3D 0; + BitNumber =3D 0; + + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( + Source, + &RegAddress, + &BitNumber + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + *TriggerType =3D (MmioBitFieldRead32 (RegAddress, BitNumber, BitNumber) = =3D=3D 0) + ? EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH + : EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; + return EFI_SUCCESS; } =20 -STATIC +/** + Set interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ EFI_STATUS EFIAPI GicV2SetTriggerType ( @@ -214,20 +291,83 @@ GicV2SetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType ) { + UINTN RegAddress =3D 0; + UINTN BitNumber =3D 0; + UINT32 Value; + EFI_STATUS Status; + BOOLEAN IntrSourceEnabled; + + if (TriggerType !=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING + && TriggerType !=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { + DEBUG ((EFI_D_ERROR, "Invalid interrupt trigger type: %d\n", \ + TriggerType)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( + Source, + &RegAddress, + &BitNumber + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D GicV2GetInterruptSourceState ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source, + &IntrSourceEnabled + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Value =3D (TriggerType =3D=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISIN= G) + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; + + // + // Before changing the value, we must disable the interrupt, + // otherwise GIC behavior is UNPREDICTABLE. + // + if (IntrSourceEnabled) { + GicV2DisableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + MmioAndThenOr32 ( + RegAddress, + ~(0x1 << BitNumber), + Value << BitNumber + ); + // + // Restore interrupt state + // + if (IntrSourceEnabled) { + GicV2EnableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + return EFI_SUCCESS; } =20 -STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol =3D { - (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, - (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource, - (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource, - (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState, - (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt, +EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol =3D { + (HARDWARE_INTERRUPT2_REGISTER) RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE) GicV2EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE) GicV2DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE) GicV2GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT) GicV2EndOfInterrupt, GicV2GetTriggerType, GicV2SetTriggerType }; =20 - /** Shutdown our hardware =20 @@ -346,8 +486,11 @@ GicV2DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV2Protocol, &gHardwareInterrupt2V2Protocol, - GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent); + &gHardwareInterruptV2Protocol, + &gHardwareInterrupt2V2Protocol, + GicV2IrqInterruptHandler, + GicV2ExitBootServicesEvent + ); =20 return Status; } diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV3/ArmGicV3Dxe.c index 02deeef78b6d7737172a5992c6decac43cfdd64a..a0383ecd7738750f73a22538114= 03d6ed0d2fd51 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -19,6 +19,7 @@ #define ARM_GIC_DEFAULT_PRIORITY 0x80 =20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol; +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol; =20 STATIC UINTN mGicDistributorBase; STATIC UINTN mGicRedistributorsBase; @@ -184,8 +185,54 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Pr= otocol =3D { GicV3EndOfInterrupt }; =20 +/** + Calculate GICD_ICFGRn base address and corresponding bit + field Int_config[1] in the GIC distributor register. + + @param Source Hardware source of the interrupt. + @param RegAddress Corresponding GICD_ICFGRn base address. + @param BitNumber Bit number in the register to set/reset. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ STATIC EFI_STATUS +GicGetDistributorIntrCfgBaseAndBitField ( + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT UINTN *RegAddress, + OUT UINTN *BitNumber + ) +{ + UINTN RegOffset; + UINTN Field; + + if (Source >=3D mGicNumInterrupts) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + + RegOffset =3D Source / 16; + Field =3D Source % 16; + *RegAddress =3D PcdGet64 (PcdGicDistributorBase) + + ARM_GIC_ICDICFR + + (4 * RegOffset); + *BitNumber =3D (Field * 2) + 1; + + return EFI_SUCCESS; +} + +/** + Get interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Returns interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +EFI_STATUS EFIAPI GicV3GetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, @@ -193,10 +240,37 @@ GicV3GetTriggerType ( OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType ) { + UINTN RegAddress =3D 0; + UINTN BitNumber =3D 0; + EFI_STATUS Status; + + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( + Source, + &RegAddress, + &BitNumber + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + *TriggerType =3D (MmioBitFieldRead32 (RegAddress, BitNumber, BitNumber) = =3D=3D 0) + ? EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH + : EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; + return EFI_SUCCESS; } =20 -STATIC +/** + Set interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ EFI_STATUS EFIAPI GicV3SetTriggerType ( @@ -205,15 +279,79 @@ GicV3SetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType ) { + UINTN RegAddress; + UINTN BitNumber; + UINT32 Value; + EFI_STATUS Status; + BOOLEAN IntrSourceEnabled; + + if (TriggerType !=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING + && TriggerType !=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { + DEBUG ((EFI_D_ERROR, "Invalid interrupt trigger type: %d\n", \ + TriggerType)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( + Source, + &RegAddress, + &BitNumber + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D GicV3GetInterruptSourceState ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source, + &IntrSourceEnabled + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Value =3D (TriggerType =3D=3D EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISIN= G) + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; + + // + // Before changing the value, we must disable the interrupt, + // otherwise GIC behavior is UNPREDICTABLE. + // + if (IntrSourceEnabled) { + GicV3DisableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + MmioAndThenOr32 ( + RegAddress, + ~(0x1 << BitNumber), + Value << BitNumber + ); + // + // Restore interrupt state + // + if (IntrSourceEnabled) { + GicV3EnableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + return EFI_SUCCESS; } =20 -STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol =3D { - (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, - (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource, - (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource, - (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState, - (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt, +EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol =3D { + (HARDWARE_INTERRUPT2_REGISTER) RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE) GicV3EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE) GicV3DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE) GicV3GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT) GicV3EndOfInterrupt, GicV3GetTriggerType, GicV3SetTriggerType }; @@ -365,8 +503,11 @@ GicV3DxeInitialize ( ArmGicEnableDistributor (mGicDistributorBase); =20 Status =3D InstallAndRegisterInterruptService ( - &gHardwareInterruptV3Protocol, &gHardwareInterrupt2V3Protocol, - GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent); + &gHardwareInterruptV3Protocol, + &gHardwareInterrupt2V3Protocol, + GicV3IrqInterruptHandler, + GicV3ExitBootServicesEvent + ); =20 return Status; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel