From nobody Fri Mar 29 15:09:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+69798+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69798+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1609923868; cv=none; d=zohomail.com; s=zohoarc; b=ZP3qRPLkGaZfJB0g6paBJ2N+74MRCZmUQPsfWPAMJiucKVHxZnxqmWnbsdv0nvizW3RnoTZqsUAAb8AbCXrLpTm5KmkVBVsVWyMli3q3ZQg8CChrhE4iYEJNmFoCss0P3rqhNdMhUWv9LOzVV28diRFuYzCmv8plpy1e4bE7UzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609923868; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=Oh0EZut4wbAHd9PciP1g8HLavQcUTwpD5GEROrjsbF0=; b=QLb+umitNOOeFeURIit9VMAEuyOFb6Wq7upno+KwAqFU2WtN0qNuTmO95fjUyXo6Yku8R82zYuyBGhcJjzHxbRlsw460VJuVcnSqAEnhQs0AcZ4nbb0Vnhcvmv+u410L5NSEXyQcKMX/GONxYOnRxgQfxivXLotyRXTg6HpHLTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+69798+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1609923868632266.97913873877076; Wed, 6 Jan 2021 01:04:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZkxdYY1788612xDcevQlP8xa; Wed, 06 Jan 2021 01:04:28 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.5517.1609923862579226447 for ; Wed, 06 Jan 2021 01:04:22 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A24E1FB; Wed, 6 Jan 2021 01:04:21 -0800 (PST) X-Received: from usa.arm.com (a074939-lin.blr.arm.com [10.162.16.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1F9BF3F719; Wed, 6 Jan 2021 01:04:18 -0800 (PST) From: "Vijayenthiran Subramaniam" To: devel@edk2.groups.io, masahisa.kojima@linaro.org, Ard.Biesheuvel@arm.com, sami.mujawar@arm.com Cc: leif@nuviainc.com, thomas.abraham@arm.com Subject: [edk2-devel] [PATCH v5] ArmPlatformPkg: Enable support for flash in 64-bit address space Date: Wed, 6 Jan 2021 14:34:00 +0530 Message-Id: <1609923840-26526-1-git-send-email-vijayenthiran.subramaniam@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vijayenthiran.subramaniam@arm.com X-Gm-Message-State: 9ImYJ6YenfkivxwGio4jTFzwx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1609923868; bh=j8kIQILNtlZvFRG3tdMmj523A5juPybbuYKbivqo5hw=; h=Cc:Date:From:Reply-To:Subject:To; b=PWRZ5NM6K4SPx1bEEE+zAuhI80Uv9i0SPNDwGgLtVV6bHSJWIsom8bT0GXUbuNYL8gV OqZv4hGjF/q08joC2K6VEi57VS6/z02CTqlwp9JF9e6L1wNAY2qOnBx8xwfjzIlx33pYc diJZYPVOhKTqRGQ7fJus3vjQbx2UxnapeRk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The existing NOR Flash DXE and StandaloneMm driver supports NOR flash devices connected in the 32-bit address space. Extend these drivers to allow NOR flash devices connected to 64-bit address space to be usable as well. Also, convert the base address and size sanity check from ASSERT() to if condition so that even if the firmware is build in release mode, it can return error if the parameter(s) is/are invalid. Signed-off-by: Vijayenthiran Subramaniam Tested-by: Masahisa Kojima --- Changes since v4: - Update NorFlashStandaloneMm.c to be usable on 64-bit address space Changes since v3: - Add 64-bit PCDs to NorFlashStandaloneMm.inf to build for StandaloneMm Changes since v2: - Rebased to latest edk2 master branch and update copyright year - Retaining Sami's R-by from https://edk2.groups.io/g/devel/message/69214 ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf | 5 +- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf | 5 +- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c | 22 +++++-- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvb.c | 61 +++++++++= ++++++++--- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c | 22 +++++-- 5 files changed, 92 insertions(+), 23 deletions(-) diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf b/ArmPlatfo= rmPkg/Drivers/NorFlashDxe/NorFlashDxe.inf index 8b5078497fff..f8d4c2703143 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf @@ -2,7 +2,7 @@ # # Component description file for NorFlashDxe module # -# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -55,10 +55,13 @@ [Protocols] gEfiDiskIoProtocolGuid =20 [Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf b/= ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf index f788472406b7..b2f72fb4de20 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf @@ -2,7 +2,7 @@ # # Component description file for NorFlashStandaloneMm module # -# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
# Copyright (c) 2020, Linaro, Ltd. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,10 +50,13 @@ [Protocols] gEfiSmmFirmwareVolumeBlockProtocolGuid =20 [Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c b/ArmPlatform= Pkg/Drivers/NorFlashDxe/NorFlashDxe.c index 41cdd1cbd397..28dc8e125c78 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c @@ -1,6 +1,6 @@ /** @file NorFlashDxe.c =20 - Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
+ Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -343,9 +343,18 @@ NorFlashInitialise ( =20 for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { // Check if this NOR Flash device contain the variable storage region - ContainVariableStorage =3D - (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashN= vStorageVariableBase)) && - (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D NorFlashDevices[Index].RegionBaseAddress + NorFlash= Devices[Index].Size); + + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashNv= StorageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvS= torageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].= Size); + } else { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashNv= StorageVariableBase)) && + (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSto= rageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].= Size); + } =20 Status =3D NorFlashCreateInstance ( NorFlashDevices[Index].DeviceBaseAddress, @@ -413,10 +422,11 @@ NorFlashFvbInitialize ( EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); ASSERT_EFI_ERROR (Status); =20 - mFlashNvStorageVariableBase =3D PcdGet32 (PcdFlashNvStorageVariableBase); + mFlashNvStorageVariableBase =3D (FixedPcdGet64 (PcdFlashNvStorageVariabl= eBase64) !=3D 0) ? + FixedPcdGet64 (PcdFlashNvStorageVariableBase64) : FixedPcdGet32 (PcdFl= ashNvStorageVariableBase); =20 // Set the index of the first LBA for the FVB - Instance->StartLba =3D (PcdGet32 (PcdFlashNvStorageVariableBase) - Insta= nce->RegionBaseAddress) / Instance->Media.BlockSize; + Instance->StartLba =3D (mFlashNvStorageVariableBase - Instance->RegionBa= seAddress) / Instance->Media.BlockSize; =20 BootMode =3D GetBootModeHob (); if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvb.c b/ArmPlatform= Pkg/Drivers/NorFlashDxe/NorFlashFvb.c index a332b5e98be7..db8eb595f4b8 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvb.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvb.c @@ -1,6 +1,6 @@ /*++ @file NorFlashFvbDxe.c =20 - Copyright (c) 2011 - 2020, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -48,23 +48,66 @@ InitializeFvAndVariableStoreHeaders ( UINTN HeadersLength; EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; VARIABLE_STORE_HEADER *VariableStoreHeader; + UINT32 NvStorageFtwSpareSize; + UINT32 NvStorageFtwWorkingSize; + UINT32 NvStorageVariableSize; + UINT64 NvStorageFtwSpareBase; + UINT64 NvStorageFtwWorkingBase; + UINT64 NvStorageVariableBase; =20 HeadersLength =3D sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLO= CK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER); Headers =3D AllocateZeroPool(HeadersLength); =20 + NvStorageFtwWorkingSize =3D PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + NvStorageFtwSpareSize =3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + NvStorageVariableSize =3D PcdGet32 (PcdFlashNvStorageVariableSize); + + NvStorageFtwSpareBase =3D (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) != =3D 0) ? + PcdGet64 (PcdFlashNvStorageFtwSpareBase64) : PcdGet32 (PcdFlashNvStora= geFtwSpareBase); + NvStorageFtwWorkingBase =3D (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64= ) !=3D 0) ? + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) : PcdGet32 (PcdFlashNvSto= rageFtwWorkingBase); + NvStorageVariableBase =3D (PcdGet64 (PcdFlashNvStorageVariableBase64) != =3D 0) ? + PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32 (PcdFlashNvStora= geVariableBase); + // FirmwareVolumeHeader->FvLength is declared to have the Variable area = AND the FTW working area AND the FTW Spare contiguous. - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStor= ageVariableSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwWorkingBase)); - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvSt= orageFtwWorkingSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwSpareBase)); + if ((NvStorageVariableBase + NvStorageVariableSize) !=3D NvStorageFtwWor= kingBase) { + DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwWorkingBase is not contiguous wi= th NvStorageVariableBase region\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwWorkingBase + NvStorageFtwWorkingSize) !=3D NvStorageFt= wSpareBase) { + DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwSpareBase is not contiguous with= NvStorageFtwWorkingBase region\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } =20 // Check if the size of the area is at least one block size - ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && (PcdGet32(PcdFla= shNvStorageVariableSize) / Instance->Media.BlockSize > 0)); - ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32(PcdF= lashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0)); - ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32(PcdFla= shNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); + if ((NvStorageVariableSize <=3D 0) || (NvStorageVariableSize / Instance-= >Media.BlockSize <=3D 0)) { + DEBUG ((DEBUG_ERROR, "%a: NvStorageVariableSize is 0x%x, should be atl= east one block size\n", __FUNCTION__, + NvStorageVariableSize)); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwWorkingSize <=3D 0) || (NvStorageFtwWorkingSize / Insta= nce->Media.BlockSize <=3D 0)) { + DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwWorkingSize is 0x%x, should be a= tleast one block size\n", __FUNCTION__, + NvStorageFtwWorkingSize)); + return EFI_INVALID_PARAMETER; + } + + if ((NvStorageFtwSpareSize <=3D 0) || (NvStorageFtwSpareSize / Instance-= >Media.BlockSize <=3D 0)) { + DEBUG ((DEBUG_ERROR, "%a: NvStorageFtwSpareSize is 0x%x, should be atl= east one block size\n", __FUNCTION__, + NvStorageFtwSpareSize)); + return EFI_INVALID_PARAMETER; + } =20 // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSi= ze =3D=3D 0); - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.Block= Size =3D=3D 0); - ASSERT(PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSi= ze =3D=3D 0); + if ((NvStorageVariableBase % Instance->Media.BlockSize !=3D 0) || + (NvStorageFtwWorkingBase % Instance->Media.BlockSize !=3D 0) || + (NvStorageFtwSpareBase % Instance->Media.BlockSize !=3D 0)) { + DEBUG ((DEBUG_ERROR, "%a: NvStorage Base addresses must be aligned to = block size boundaries", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } =20 // // EFI_FIRMWARE_VOLUME_HEADER diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c b/Ar= mPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c index 1ebf6d6ba70b..8a4fb395d286 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c @@ -1,6 +1,6 @@ /** @file NorFlashStandaloneMm.c =20 - Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
+ Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
Copyright (c) 2020, Linaro, Ltd. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -298,9 +298,18 @@ NorFlashInitialise ( =20 for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { // Check if this NOR Flash device contain the variable storage region - ContainVariableStorage =3D - (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashN= vStorageVariableBase)) && - (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D NorFlashDevices[Index].RegionBaseAddress + NorFlash= Devices[Index].Size); + + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashNv= StorageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvS= torageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].= Size); + } else { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashNv= StorageVariableBase)) && + (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSto= rageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].= Size); + } =20 Status =3D NorFlashCreateInstance ( NorFlashDevices[Index].DeviceBaseAddress, @@ -330,10 +339,11 @@ NorFlashFvbInitialize ( =20 ASSERT((Instance !=3D NULL)); =20 - mFlashNvStorageVariableBase =3D PcdGet32 (PcdFlashNvStorageVariableBase); =20 + mFlashNvStorageVariableBase =3D (FixedPcdGet64 (PcdFlashNvStorageVariabl= eBase64) !=3D 0) ? + FixedPcdGet64 (PcdFlashNvStorageVariableBase64) : FixedPcdGet32 (PcdFl= ashNvStorageVariableBase); // Set the index of the first LBA for the FVB - Instance->StartLba =3D (PcdGet32 (PcdFlashNvStorageVariableBase) - Insta= nce->RegionBaseAddress) / Instance->Media.BlockSize; + Instance->StartLba =3D (mFlashNvStorageVariableBase - Instance->RegionBa= seAddress) / Instance->Media.BlockSize; =20 // Determine if there is a valid header at the beginning of the NorFlash Status =3D ValidateFvHeader (Instance); --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#69798): https://edk2.groups.io/g/devel/message/69798 Mute This Topic: https://groups.io/mt/79471264/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-