From nobody Sun May 5 17:59:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+67973+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67973+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1606311006; cv=none; d=zohomail.com; s=zohoarc; b=TpvgdlJ6SwYfX6Csof9Gv9PJX+sDo182Ubjy1niguEuUZHw8W/P6fdT8qbL0Bljbr0FK6vrPkomMq+uuy04dLGgqQwEfCuLEoL4kPmNwhsT2ylhpyISyVlbp96CFia2CkCzSlqd+cA7Vd3/EE32pnFk6I58MgSS1WxNL/9pY+5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606311006; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=N3f0/7fvL+BpHgo5BtPThEMgP4pfmEcfRl4GxDWG1Go=; b=D0zp7SxEUiWrT8AhzZQ10hoIUtskJrfHMOySRUCJL3FR1qKWAgORAWGxTxuHIZ0yqsiNaxpJ1osG+ap4yEYU1i6AI7OF8GBqElAW+GTiZGm+rpBhtp4WslbdGp89QNuC71w7ovtSE0xgZM8P0P6neU7p1jUI6lXdthB+ZiaqhBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+67973+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1606311006798620.37974459094; Wed, 25 Nov 2020 05:30:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PsYIYY1788612x8bulHEYnCZ; Wed, 25 Nov 2020 05:30:06 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.6732.1606311005503465118 for ; Wed, 25 Nov 2020 05:30:05 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F49431B; Wed, 25 Nov 2020 05:30:05 -0800 (PST) X-Received: from usa.arm.com (a074939-lin.blr.arm.com [10.162.16.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 240B83F70D; Wed, 25 Nov 2020 05:30:02 -0800 (PST) From: "Vijayenthiran Subramaniam" To: devel@edk2.groups.io, leif@nuviainc.com, Ard.Biesheuvel@arm.com Cc: thomas.abraham@arm.com, Aditya.Angadi@arm.com Subject: [edk2-devel] [PATCH] ArmPlatformPkg: Enable support for flash in 64-bit address space Date: Wed, 25 Nov 2020 18:59:48 +0530 Message-Id: <1606310988-10772-1-git-send-email-vijayenthiran.subramaniam@arm.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vijayenthiran.subramaniam@arm.com X-Gm-Message-State: DWvlj4lCpCX5zCtLZp5fOugWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1606311006; bh=rycevS8m5BFthHVErfHca8yC1WhZVJAdzM/HuVm+GOo=; h=Cc:Date:From:Reply-To:Subject:To; b=b+QonuXkeKf/4z2BAwAc0XZS+7QU+x1yUUJzpnXlf+MNY6A/EvJf+2k1GVimCOpLBSd D+0YPwzPfbFxnO95DrP6tmf4WJEQr9Zb6GEYELamlsQXuiF5fMNKWeTE4OPgDrbwGaihu Q/M6Rg/QM+Gf8PxWFj3LrUkLmJDZvOm6Y+E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The existing NOR flash Dxe driver supports NOR flash devices connected in the 32-bit address space. Extend this driver to allow NOR flash devices connected to 64-bit address space to be usable as well. Signed-off-by: Vijayenthiran Subramaniam --- .../Drivers/NorFlashDxe/NorFlashDxe.c | 13 ++++++-- .../Drivers/NorFlashDxe/NorFlashDxe.inf | 3 ++ .../Drivers/NorFlashDxe/NorFlashFvbDxe.c | 31 ++++++++++++++----- 3 files changed, 37 insertions(+), 10 deletions(-) diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c b/ArmPlatform= Pkg/Drivers/NorFlashDxe/NorFlashDxe.c index d9e196cbf1..f3fbbafb7d 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c @@ -1298,9 +1298,16 @@ NorFlashInitialise ( =20 for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { // Check if this NOR Flash device contain the variable storage region - ContainVariableStorage =3D - (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashN= vStorageVariableBase)) && - (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D NorFlashDevices[Index].RegionBaseAddress + NorFlash= Devices[Index].Size); + + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashNv= StorageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvS= torageVariableSize) <=3D NorFlashDevices[Index].RegionBaseAddress + NorFlas= hDevices[Index].Size); + } else { + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet32 (PcdFlashNv= StorageVariableBase)) && + (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvSto= rageVariableSize) <=3D NorFlashDevices[Index].RegionBaseAddress + NorFlashD= evices[Index].Size); + } =20 Status =3D NorFlashCreateInstance ( NorFlashDevices[Index].DeviceBaseAddress, diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf b/ArmPlatfo= rmPkg/Drivers/NorFlashDxe/NorFlashDxe.inf index a647c01687..b2a941d672 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf @@ -54,10 +54,13 @@ gEfiDiskIoProtocolGuid =20 [Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/ArmPlatf= ormPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c index 9cdd85096a..ecbe009495 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c @@ -58,8 +58,17 @@ InitializeFvAndVariableStoreHeaders ( Headers =3D AllocateZeroPool(HeadersLength); =20 // FirmwareVolumeHeader->FvLength is declared to have the Variable area = AND the FTW working area AND the FTW Spare contiguous. - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStor= ageVariableSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwWorkingBase)); - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvSt= orageFtwWorkingSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwSpareBase)); + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNv= StorageVariableSize) =3D=3D PcdGet64(PcdFlashNvStorageFtwWorkingBase64)); + } else { + ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvSt= orageVariableSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwWorkingBase)); + } + + if (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) !=3D 0) { + ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlash= NvStorageFtwWorkingSize) =3D=3D PcdGet64(PcdFlashNvStorageFtwSpareBase64)); + } else { + ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNv= StorageFtwWorkingSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwSpareBase)); + } =20 // Check if the size of the area is at least one block size ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && (PcdGet32(PcdFla= shNvStorageVariableSize) / Instance->Media.BlockSize > 0)); @@ -67,9 +76,16 @@ InitializeFvAndVariableStoreHeaders ( ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32(PcdFla= shNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); =20 // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSi= ze =3D=3D 0); - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.Block= Size =3D=3D 0); - ASSERT(PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSi= ze =3D=3D 0); + if (PcdGet64 (PcdFlashNvStorageVariableBase64) !=3D 0) { + ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.B= lockSize =3D=3D 0); + ASSERT(PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + } + else { + ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.Block= Size =3D=3D 0); + ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.Blo= ckSize =3D=3D 0); + ASSERT(PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.Block= Size =3D=3D 0); + } =20 // // EFI_FIRMWARE_VOLUME_HEADER @@ -736,10 +752,11 @@ NorFlashFvbInitialize ( EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); ASSERT_EFI_ERROR (Status); =20 - mFlashNvStorageVariableBase =3D PcdGet32 (PcdFlashNvStorageVariableBase); + mFlashNvStorageVariableBase =3D (FixedPcdGet64 (PcdFlashNvStorageVariabl= eBase64) !=3D 0) ? + FixedPcdGet64 (PcdFlashNvStorageVariableBase64) : FixedPcdGet32 (PcdFl= ashNvStorageVariableBase); =20 // Set the index of the first LBA for the FVB - Instance->StartLba =3D (PcdGet32 (PcdFlashNvStorageVariableBase) - Insta= nce->RegionBaseAddress) / Instance->Media.BlockSize; + Instance->StartLba =3D (mFlashNvStorageVariableBase - Instance->RegionBa= seAddress) / Instance->Media.BlockSize; =20 BootMode =3D GetBootModeHob (); if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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