From nobody Tue Feb 10 07:22:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+65973+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65973+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1602066950; cv=none; d=zohomail.com; s=zohoarc; b=VhR9RCHx+1EPP0cgs8Uc5EQcaWiPkjtG2h2pn0RDKX6lyc19YtZ35w3NnGou+MWAz/beU99beaMTDQ20qgdtkyZ+kJ5u4+b7xseXr1rNSubKWEJusJfGWiwsZHdqw9kV9ANkWTodJi9L3CDhmlz4r5PMd2ywwLgfnPazT4Rzbkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602066950; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=p5F8wV7zxwl0VHP4Roqb3cZ3awDHkySiXf6nCw9azjM=; b=R3Wnr12zGpvHXB46+KHO3RMIUehb9VI/4YRQYY1p/z4QxFWcvHUgqRCDK5vEusuxgf9Y15mEt18CmZpIkXfpmeuwYMlS4ScDL9tWoRRMClwdu25JkFzS56SlSH89htEapaO4ppgl+/Ezh4321GYsuUMh5ASIGiBbtY785ZuzDnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65973+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1602066950255412.45236421120285; Wed, 7 Oct 2020 03:35:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZRx5YY1788612xeCuz5xb3Cz; Wed, 07 Oct 2020 03:35:49 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web10.10064.1602066568664743904 for ; Wed, 07 Oct 2020 03:29:29 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2725D1A1515; Wed, 7 Oct 2020 12:29:27 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BF4A51A151D; Wed, 7 Oct 2020 12:29:26 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 785E232D; Wed, 7 Oct 2020 15:59:25 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms v2 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds Date: Wed, 7 Oct 2020 21:40:40 +0530 Message-Id: <1602087041-8009-6-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1602087041-8009-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1602087041-8009-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: U5LWOgzXTq0DqDzKa6ntvAtEx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1602066949; bh=JYX7XqcsFywJ3BeksbAEePjvyUrMkvRK88oDZDC0OYA=; h=Cc:Date:From:Reply-To:Subject:To; b=QSGbdylsrCyvdfn/ndWt3eSI7uFmwBZzWJGTgkW+MRLXQ6HPF+DX1/N7dDMeU4Snb+p W/7dUqguhtIOW2yGYtVjkoQCWdbMIzmtx+pvJS9xubajgXj4w/e8HbH35q/VInqjWAN6l np0yqXHdruVXPiN6165acOISRMw2qy0GCic= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Apply USB errata workarounds for LS1046A SoC and make SATA, USB and SEC snoopable. Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 + Silicon/NXP/LS1046A/Include/Soc.h | 2 + Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++++++++++++++++= ++++ 4 files changed, 71 insertions(+) diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10= 46A.dsc.inc index db110553605f..4e1d6a7ae7a2 100644 --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc @@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common] =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE =20 ##########################################################################= ###### diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1046A/Library/SocLib/SocLib.inf index 01ed0f6592d2..e2336bb18f29 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf @@ -14,6 +14,7 @@ [Defines] LIBRARY_CLASS =3D SocLib =20 [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1046A/LS1046A.dec @@ -25,3 +26,4 @@ [LibraryClasses] =20 [Sources.common] SocLib.c + diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Includ= e/Soc.h index 84f433d5cb94..e1d97e531263 100644 --- a/Silicon/NXP/LS1046A/Include/Soc.h +++ b/Silicon/NXP/LS1046A/Include/Soc.h @@ -25,6 +25,7 @@ #define LS1046A_QSPI0_SIZE (SIZE_512MB) =20 #define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS +#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS =20 /** Reset Control Word (RCW) Bits @@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Not= es/comments #define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 =20 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG; +typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_C= ONFIG; =20 #endif // SOC_H__ diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10= 46A/Library/SocLib/SocLib.c index 3b15aee6ecae..80342d7230e4 100644 --- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c +++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c @@ -11,6 +11,8 @@ #include #include #include + +#include #include =20 /** @@ -65,6 +67,47 @@ SocGetClock ( } =20 /** + Function to select pins depending upon pcd using supplemental + configuration unit(SCFG) extended RCW controlled pinmux control + register which contains the bits to provide pin multiplexing control. + This register is reset on HRESET. + **/ +STATIC +VOID +ConfigScfgMux (VOID) +{ + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + UINT32 UsbPwrFault; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB); + + ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1); + UsbPwrFault =3D (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHI= FT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT= ) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); + ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); +} + +STATIC +VOID +ApplyErrata ( + VOID + ) +{ + ErratumA009008 (); + ErratumA009798 (); + ErratumA008997 (); + ErratumA009007 (); +} + + + +/** Function to initialize SoC specific constructs **/ VOID @@ -72,7 +115,30 @@ SocInit ( VOID ) { + LS1046A_SUPPLEMENTAL_CONFIG *Scfg; + + Scfg =3D (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS; + + /* Make SEC, SATA and USB reads and writes snoopable */ + ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); + + ApplyErrata (); ChassisInit (); =20 + // + // Due to the extensive functionality present on the chip and the limite= d number of external + // signals available, several functional blocks share signal resources t= hrough multiplexing. + // In this case when there is alternate functionality between multiple f= unctional blocks, + // the signal's function is determined at the chip level (rather than at= the block level) + // typically by a reset configuration word (RCW) option. Some of the sig= nals' function are + // determined externel to RCW at Power-on Reset Sequence. + // + ConfigScfgMux (); + return; } --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65973): https://edk2.groups.io/g/devel/message/65973 Mute This Topic: https://groups.io/mt/77359495/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-