From nobody Tue Feb 10 07:22:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+65266+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65266+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1600167043; cv=none; d=zohomail.com; s=zohoarc; b=EAmurI6HY2ZgOC4I/0nQiRj5O9kSvV2N012ECxmnjJ0bUS8/5uy4mrW6tD7tchIE0/QwW36G5SYNhtlDyieWvJzvmSjUy5UA8lzpltH9UOQBH1stW+sv3TCMap0Q1uJaxn/s7jPHp4nnYDTr7Z9fTW/b7zRRLJ5Y4GdW7P3p7DA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600167043; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=DCYyyRnYIBaQMfYJvrC+a4IawxgY1e2vbRQSsu00myc=; b=F37bEx2fMA2FzYhVxqCcqTiOXRrn/ibAaAOxsMJa6Czj6RDbrtSsHTYHKfwOncqkqQbuovLimJs+x17+1udF9x1iQmds5L4tDWR5ZaUZydLVQg9vC1Lc2cqL56ZKhIRCt69lFvOzdbBLk3PJQr2n97/yHgeiaE1xaH5nk4ZXfL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+65266+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1600167043468485.41356109730737; Tue, 15 Sep 2020 03:50:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id zClrYY1788612xZhBawGAD3w; Tue, 15 Sep 2020 03:50:43 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.10730.1600166866226521850 for ; Tue, 15 Sep 2020 03:47:46 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C48CD1A08A1; Tue, 15 Sep 2020 12:47:44 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6A9E41A0886; Tue, 15 Sep 2020 12:47:44 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (unknown [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 2BE1E344; Tue, 15 Sep 2020 16:17:43 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Pramod Kumar , Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms 1/4] Silicon/NXP: Add GPIO driver support. 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charset="utf-8" Signed-off-by: Pramod Kumar Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 +++++ Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++++++ Silicon/NXP/Library/GpioLib/GpioLib.c | 242 ++++++++++++++++++++++++++++= ++++ 3 files changed, 391 insertions(+) create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf create mode 100644 Silicon/NXP/Include/Library/GpioLib.h create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/= GpioLib/GpioLib.inf new file mode 100644 index 000000000000..7878d1d03db2 --- /dev/null +++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf @@ -0,0 +1,39 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D GpioLib + FILE_GUID =3D addec2b8-d2e0-43c0-a277-41a8d42f3f4f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioLib + +[Sources.common] + GpioLib.c + +[LibraryClasses] + ArmLib + BaseMemoryLib + BaseLib + IoAccessLib + IoLib + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController + gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Li= brary/GpioLib.h new file mode 100644 index 000000000000..5821806226ee --- /dev/null +++ b/Silicon/NXP/Include/Library/GpioLib.h @@ -0,0 +1,110 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef GPIO_H__ +#define GPIO_H__ + +#include + +/* enum for GPIO number */ +typedef enum _GPIO_BLOCK { + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO_MAX +} GPIO_BLOCK; + +/* enum for GPIO direction */ +typedef enum _GPIO_DIRECTION { + INPUT, + OUTPUT +} GPIO_DIRECTION; + +/* enum for GPIO state */ +typedef enum _GPIO_STATE { + LOW, + HIGH +} GPIO_VAL; + +/** + SetDir Set GPIO direction as INPUT or OUTPUT + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Dir GPIO Direction as INPUT or OUTPUT + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetDir ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Dir + ); + +/** + GetDir Retrieve GPIO direction + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO Direction as INPUT or OUTPUT + **/ +UINT32 +GetDir ( + IN UINT8 Id, + IN UINT32 Bit + ); + + /** + GetData Retrieve GPIO Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO value as HIGH or LOW + **/ +UINT32 +GetData ( + IN UINT8 Id, + IN UINT32 Bit + ); + +/** + SetData Set GPIO data Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Data GPIO data value to set + + @retval GPIO value as HIGH or LOW + **/ +EFI_STATUS +SetData ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Data + ); + +/** + SetOpenDrain Set GPIO as Open drain + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] OpenDrain Set as open drain + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetOpenDrain ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN OpenDrain + ); + +#endif diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/Gp= ioLib/GpioLib.c new file mode 100644 index 000000000000..33cc45c2152b --- /dev/null +++ b/Silicon/NXP/Library/GpioLib/GpioLib.c @@ -0,0 +1,242 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +STATIC MMIO_OPERATIONS *mGpioOps; + +/* Structure for GPIO Regsters */ +typedef struct GpioRegs { + UINT32 GpDir; + UINT32 GpOdr; + UINT32 GpData; + UINT32 GpIer; + UINT32 GpImr; + UINT32 GpIcr; +} GPIO_REGS; + +/** + GetBaseAddr GPIO controller Base Address + + @param[in] Id GPIO controller number + + @retval GPIO controller Base Address, if found + @retval NULL, if not a valid controller number + + **/ +STATIC +VOID * +GetBaseAddr ( + IN UINT8 Id + ) +{ + + UINTN GpioBaseAddr; + UINTN MaxGpioController; + + mGpioOps =3D GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndia= n)); + + MaxGpioController =3D PcdGet32 (PcdNumGpioController); + + if (Id < MaxGpioController) { + GpioBaseAddr =3D PcdGet64 (PcdGpioModuleBaseAddress) + + (Id * PcdGet64 (PcdGpioControllerOffset)); + return (VOID *) GpioBaseAddr; + } + else { + DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d= -%d", + Id, GPIO1, MaxGpioController)); + return NULL; + } +} + +/** + GetBitMask: Return Bit Mask + + @param[in] Bit Bit to create bitmask + @retval Bitmask + + **/ + +STATIC +UINT32 +GetBitMask ( + IN UINT32 Bit + ) +{ + + if (!FeaturePcdGet (PcdGpioControllerBigEndian)) { + return (1 << Bit); + } else { + return (1 << (31 - Bit)); + } +} + + +/** + SetDir Set GPIO direction as INPUT or OUTPUT + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Dir GPIO Direction as INPUT or OUTPUT + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetDir ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Dir + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr(Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpDir); + + if (Dir) { + mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value | BitMask)); + } + else { + mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} + +/** + GetDir Retrieve GPIO direction + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO Direction as INPUT or OUTPUT + **/ +UINT32 +GetDir ( + IN UINT8 Id, + IN UINT32 Bit + ) +{ + GPIO_REGS *Regs; + UINT32 Value; + UINT32 BitMask; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpDir); + + return (Value & BitMask); +} + +/** + GetData Retrieve GPIO Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + + @retval GPIO value as HIGH or LOW + **/ +UINT32 +GetData ( + IN UINT8 Id, + IN UINT32 Bit + ) +{ + GPIO_REGS *Regs; + UINT32 Value; + UINT32 BitMask; + + Regs =3D (VOID *)GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpData); + + if (Value & BitMask) { + return 1; + } else { + return 0; + } +} + +/** + SetData Set GPIO data Value + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] Data GPIO data value to set + + @retval GPIO value as HIGH or LOW + **/ +EFI_STATUS +SetData ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN Data + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpData); + + if (Data) { + mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value | BitMask)); + } else { + mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} + +/** + SetOpenDrain Set GPIO as Open drain + + @param[in] Id GPIO controller number + @param[in] Bit GPIO number + @param[in] OpenDrain Set as open drain + + @retval EFI_SUCCESS + **/ +EFI_STATUS +SetOpenDrain ( + IN UINT8 Id, + IN UINT32 Bit, + IN BOOLEAN OpenDrain + ) +{ + GPIO_REGS *Regs; + UINT32 BitMask; + UINT32 Value; + + Regs =3D GetBaseAddr (Id); + BitMask =3D GetBitMask(Bit); + + Value =3D mGpioOps->Read32 ((UINTN)&Regs->GpOdr); + if (OpenDrain) { + mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value | BitMask)); + } + else { + mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value & (~BitMask))); + } + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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