From nobody Tue Feb 10 01:34:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63125+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63125+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1595431555; cv=none; d=zohomail.com; s=zohoarc; b=TuNRxnCo86lBRRQPv63fjqAyEslJLXjjYzzh8wPuPft7wpznzsHjKzhw0QyoD12WopkqdCmzALWvduak7RDb+uJ/bNI9okGk2FBXvBwScaxYY2h30FWvbCKkjcfPke5tXz3H+ZyAQXKeTmG+buHWX507MDFe0S4kkiXnYrYWUzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595431555; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qz/eWzZ7bsu00Wvp0acNctz0Nu02a9WDpMCsyf6qryU=; b=WbTVAhg0e4x8V7ncVrh0PEBeYuXv7bt6fG2+XxZEqCNJlrL5AaR/vzNT3UqVMvz8XAId2HGd5nxJ5u0WRf5eelrlalUuAStlni+b08Fe6P9RmWIZM+SSf20JB5c+tCBRBnJCA1ksMjiWRei/+81tAswsaRyHA/yZAc/23Y6hT4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63125+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1595431555160989.1850333198648; Wed, 22 Jul 2020 08:25:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id uGPFYY1788612x5Eh1raiQKQ; Wed, 22 Jul 2020 08:25:54 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.21437.1595431553509759979 for ; Wed, 22 Jul 2020 08:25:53 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 693DA31B; Wed, 22 Jul 2020 08:25:52 -0700 (PDT) X-Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.17.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 427A63F66E; Wed, 22 Jul 2020 08:25:51 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm Subject: [edk2-devel] [edk2-platforms][PATCH v5 3/5] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Date: Wed, 22 Jul 2020 20:55:22 +0530 Message-Id: <1595431524-13782-4-git-send-email-pranav.madhu@arm.com> In-Reply-To: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> References: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 7vZAriqyUmPtNtqlDyv1rsmpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1595431554; bh=2Ml7PenkjINWGXSyO5M5boTiDZTUeyWhPhSex4NhU9U=; h=Cc:Date:From:Reply-To:Subject:To; b=b1GMI0tXwNLyAK1uqPxfqgK2puBjT4twenpka3+6Mk0u6rblZIGVhRzfwUQqGbHXtUA ge2iKujRIxmu2NdDGsWaX5s2ShefhvF6ZbTLLTX+RPQO5Tvvted2gvNIuX35vyGIPBIyN OIwB0UFjQ0q+SJx9Jq91lNruO67j60JRQg0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Deepak Pandey Neoverse N1 SoC includes a PCIe root complex to which a AHCI, GbE and USB controllers are attached as an endpoint. So implement the PciHostBridgeLib glue layer and enable support for PCIe controller and all the devices connected over the PCIe bus. Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Pranav Madhu --- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | = 15 ++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf | = 49 ++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | = 11 ++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | = 184 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | = 28 ++- 5 files changed, 286 insertions(+), 1 deletion(-) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index 491806b81be9..54b793a937ff 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -29,3 +29,18 @@ [PcdsFixedAtBuild] #PCIe gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000= 000|UINT32|0x00000002 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000= |UINT32|0x00000003 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x000= 00008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x000000= 09 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0= x0000000A + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x00= 00000B + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0= x0000000C + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x00= 00000D + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x00= 00000E + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|0x= 0000000F + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64= |0x00000010 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x= 00000011 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00= 000012 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBrid= geLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridg= eLib.inf new file mode 100644 index 000000000000..3ff1c592f2a7 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf @@ -0,0 +1,49 @@ +## @file +# PCI Host Bridge Library instance for ARM Neoverse N1 platform. +# +# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D daa340e1-89dd-4bd2-b645-ebe75e541f8b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +[Sources] + PciHostBridgeLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index e4d720bd36f5..166c9e044483 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -29,11 +29,22 @@ [Sources.AARCH64] AArch64/Helper.S | GCC =20 [FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCoreMask =20 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base =20 [Guids] diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBrid= geLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.c new file mode 100644 index 000000000000..9332939f63eb --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,184 @@ +/** @file +* PCI Host Bridge Library instance for ARM Neoverse N1 platform +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack (1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D { + // PCIe + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpa= ce + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPcieBusMin), + FixedPcdGet32 (PcdPcieBusMax) + }, { + // Io + FixedPcdGet64 (PcdPcieIoBase), + FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPcieMmio32Base), + FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Size= ) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPcieMmio64Base), + FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Size= ) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + } +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count =3D ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL= .\ + SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happened!\n")); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 096832be96da..f9b3d037537d 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -13,7 +13,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 =20 /** Returns the Virtual Memory Map of the platform. @@ -88,6 +88,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_NON_SECURE_S= RAM_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; =20 + // PCIe RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieRootPortC= onfigBaseSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPcieBus= Max) - + FixedPcdGet32 (PcdPcieBusMi= n) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieMmio32Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieMmio32Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieMmio32Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieMmio64Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPcieMmio64Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BASE; VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BASE; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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