From nobody Tue Feb 10 00:23:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61749+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61749+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1593190636; cv=none; d=zohomail.com; s=zohoarc; b=B7GCE2Vj2Ih20F7hozwEK3HedR3XKYEVf4WJIvTZHA2q7YjhjluxFT4XsjFam00JKEPrvJA//Jh4+ujBjURXk6ztwEnfEhJSgbBTgffeWyBVfyHB0vRb2JxOEgtW0YtoYH1tWYtsgTzSk6ZNbOcakwhMz8yje5xZ3jq0UyL2d6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593190636; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GjgTM9MuG6QoZJFI/sAEeDZf6FyajmpL1a6HAPb0F+o=; b=Zh2B8nyIVxqjT+YjHRpfBCsrbjcCRrkKMLX9QnEnVnNTKw4r6lL9+iXGIJcBDjW4VHsMNjsSyYdM9MXKU2WRUwAHSJLm6Wi0h7hH10I9TNE2/SMYTz/lGaLxG9ExYOaLumFAsGGRPpcCPOH8p9IPJhR4dvw/EQ96ihjTCN4KPSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61749+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1593190636409792.0651440849946; Fri, 26 Jun 2020 09:57:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UIeKYY1788612xedqS1KbhXX; Fri, 26 Jun 2020 09:57:16 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.199.1593190521010150685 for ; Fri, 26 Jun 2020 09:55:21 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD16ED6E for ; Fri, 26 Jun 2020 09:55:20 -0700 (PDT) X-Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F0B7E3F71E for ; Fri, 26 Jun 2020 09:55:19 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Subject: [edk2-devel] [edk2-platforms][PATCH v2 3/4] Silicon/ARM/N1SDP: Implement the PciHostBridgeLib library Date: Fri, 26 Jun 2020 22:24:52 +0530 Message-Id: <1593190493-17450-4-git-send-email-pranav.madhu@arm.com> In-Reply-To: <1593190493-17450-1-git-send-email-pranav.madhu@arm.com> References: <1593190493-17450-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 9MmyFYqBS7gQUo3JtQMqbQV6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1593190636; bh=k4nUq1yoQ8r5uFSs2q7qtltE1SjUz+Grv8hQbXNjHtE=; h=Date:From:Reply-To:Subject:To; b=v6DOhdEBIYZMiW+vt4Znq4dnxw4tohiYYcVusc6363JZqwjMYShmxZlOSF2XyCM0/8E Cl/kCgTUJIAJQ3ReOgKdZNiB3rCGvbrqO+0wAyq4+DpkVcHhxgf4RAqk7UzP3SH9qwQJA jrt4ySdJveWwioCV1IWmT5HF1Lb7nDFAKcI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Deepak Pandey N1SDP platform includes a PCIe root complex to which a AHCI, GbE and USB controllers are attached as an endpoint. So implement the PciHostBridgeLib glue layer and enable support for PCIe controller and all the devices connected over the PCIe bus. Signed-off-by: Pranav Madhu diff --git a/Silicon/ARM/N1Sdp/N1SdpPlatform.dec b/Silicon/ARM/N1Sdp/N1SdpP= latform.dec index 2edd6b17be91..222d800b8888 100644 --- a/Silicon/ARM/N1Sdp/N1SdpPlatform.dec +++ b/Silicon/ARM/N1Sdp/N1SdpPlatform.dec @@ -23,6 +23,25 @@ [Guids.common] gArmN1SdpTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, = 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } =20 [PcdsFixedAtBuild] + # PCIe + gArmN1SdpTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000003 + gArmN1SdpTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000004 + gArmN1SdpTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000005 + gArmN1SdpTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000006 + gArmN1SdpTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000007 + gArmN1SdpTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000008 + gArmN1SdpTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x00000009 + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000A + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000B + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x0000000C + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x0000000D + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|0x0000000E + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000= 00F + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000010 + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000011 + gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT= 32|0x00000012 + gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|= 0x00000013 + # Secondary DDR memory gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 =20 diff --git a/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.in= f b/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.inf new file mode 100644 index 000000000000..736154fdfd14 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -0,0 +1,49 @@ +## @file +# PCI Host Bridge Library instance for ARM N1SDP platform. +# +# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D daa340e1-89dd-4bd2-b645-ebe75e541f8b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +[Sources] + PciHostBridgeLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/N1Sdp/N1SdpPlatform.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[FixedPcd] + gArmN1SdpTokenSpaceGuid.PcdPcieBusMin + gArmN1SdpTokenSpaceGuid.PcdPcieBusMax + gArmN1SdpTokenSpaceGuid.PcdPcieIoBase + gArmN1SdpTokenSpaceGuid.PcdPcieIoSize + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf b/Silico= n/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf index 28a12f4dd3c3..d7516be561ec 100644 --- a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf @@ -29,12 +29,25 @@ [Sources.AARCH64] AArch64/Helper.S | GCC =20 [FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCoreMask =20 + gArmN1SdpTokenSpaceGuid.PcdPcieBusMax + gArmN1SdpTokenSpaceGuid.PcdPcieBusMin + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base + gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base + gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size + gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base + gArmN1SdpTokenSpaceGuid.PcdExtMemorySpace =20 [Guids] gEfiHobListGuid ## CONSUMES ## SystemTable diff --git a/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.c = b/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.c new file mode 100644 index 000000000000..9c83b688ce35 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,187 @@ +/** @file +* PCI Host Bridge Library instance for ARM N1SDP platform +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack (1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D { + // PCIe + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpa= ce + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPcieBusMin), + FixedPcdGet32 (PcdPcieBusMax) + }, { + // Io + FixedPcdGet64 (PcdPcieIoBase), + FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPcieMmio32Base), + FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Size= ) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPcieMmio64Base), + FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Size= ) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + } +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count =3D ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL= .\ + SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex =3D 0; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happened!\n")); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c b/Silic= on/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c index f545cbd6de94..d39ff3b24bc7 100644 --- a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c @@ -13,7 +13,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 =20 /** Returns the Virtual Memory Map of the platform. @@ -88,6 +88,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D N1SDP_NON_SECURE_SRAM_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; =20 + // PCIe RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieRootPortC= onfigBaseSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPcieBus= Max) - + FixedPcdGet32 (PcdPcieBusMi= n) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieMmio32Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieMmio32Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieMmio32Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // PCIe MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieMmio64Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPcieMmio64Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_UART0_BASE; VirtualMemoryTable[Index].VirtualBase =3D N1SDP_UART0_BASE; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61749): https://edk2.groups.io/g/devel/message/61749 Mute This Topic: https://groups.io/mt/75128456/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-