From nobody Tue Feb 10 10:54:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61748+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61748+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1593190634; cv=none; d=zohomail.com; s=zohoarc; b=Nu8HlEHL0qFmPp/EnWD2GZpNsJ3ym4a5VkvJkcgOVjOkhhbicvaB3Lp/RMYqhiNvWU54VWV5M1vkGqoK5GKYjfBwn5/hJ5riQswI9wi7VcfoqbbaV2Eecn4UxDwDH3hHB7A6AlkeLvEpzXEVX9ohAgvE5D7hmU8Gsu5VtBrWjgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593190634; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=grECHuTlWT8PSGdo05taqOt1wKszUYPCVhd1C5AtrfE=; b=el9f4obLYatWxEQ24Mo+57h4ZOcaUJGJPMvyh/vfu7LSsCTBIUnrOj0QmI4XeI+iOqnJKYw3sBODcdugAAZhssNlLeTf7CK/yp6cTbdQV0FMcqAo5R1YxLRm90m5i/XOwwHdPVR369QPX5Ed7Fpge7netnXAQ39ilwB65KqHYEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61748+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1593190634030250.49737253450246; Fri, 26 Jun 2020 09:57:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id otj1YY1788612xqqhFTd171N; Fri, 26 Jun 2020 09:57:13 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.3.1593190519512464011 for ; Fri, 26 Jun 2020 09:55:19 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21573D6E for ; Fri, 26 Jun 2020 09:55:18 -0700 (PDT) X-Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 643543F71E for ; Fri, 26 Jun 2020 09:55:17 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Subject: [edk2-devel] [edk2-platforms][PATCH v2 1/4] Silicon/ARM/N1SDP: Add platform library implementation Date: Fri, 26 Jun 2020 22:24:50 +0530 Message-Id: <1593190493-17450-2-git-send-email-pranav.madhu@arm.com> In-Reply-To: <1593190493-17450-1-git-send-email-pranav.madhu@arm.com> References: <1593190493-17450-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: YJf9q7rolG7eqsSoHjfkxUaBx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1593190633; bh=1/ztOfrk66RLDbPBBqPiI5qRKsnIhwz9OTwnEtcazT8=; h=Date:From:Reply-To:Subject:To; b=kWHPrJVpG7s15UV/IqWoW3lbOiqN2jpJDqKaIjNuWjRMrxJ2R/MwvBHnf+/NNnL+IIO AKv6HzZsN2XXh9Y1VA0ytiMsut6OQAQWGurG7RZlHgcYlHbVcPajzBhURh8N1UWq664jB ZUFSj7YOgPU4QPBDpz01zrWYiy9ROFRcjZM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Deepak Pandey Add the initial N1SDP (Neoverse N1 System Development Platform) platform library support. This includes the virtual memory map and helper functions for platform initialization. Signed-off-by: Pranav Madhu diff --git a/Silicon/ARM/N1Sdp/N1SdpPlatform.dec b/Silicon/ARM/N1Sdp/N1SdpP= latform.dec new file mode 100644 index 000000000000..2edd6b17be91 Reviewed-by: Thomas Abraham --- /dev/null +++ b/Silicon/ARM/N1Sdp/N1SdpPlatform.dec @@ -0,0 +1,30 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D N1SdpPkg + PACKAGE_GUID =3D b6d2d197-76d0-401f-a3e0-826a26f350c9 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmN1SdpTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, = 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + +[PcdsFixedAtBuild] + # Secondary DDR memory + gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 + + # External memory + gArmN1SdpTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000002 diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf b/Silico= n/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..28a12f4dd3c3 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmN1SdpLib + FILE_GUID =3D 3d0eafcf-abc1-43d8-9269-709bb24f9d21 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/N1Sdp/N1SdpPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + + gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Silicon/ARM/N1Sdp/Include/N1SdpPlatform.h b/Silicon/ARM/N1Sdp/= Include/N1SdpPlatform.h new file mode 100644 index 000000000000..0cfc68a5f383 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Include/N1SdpPlatform.h @@ -0,0 +1,68 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __N1SDP_PLATFORM_H__ +#define __N1SDP_PLATFORM_H__ + +#define N1SDP_DRAM_BLOCK1_SIZE SIZE_2GB + +//************************************************************************= ****** +// Platform Memory Map +//************************************************************************= ****** + +// SubSystem Peripherals - UART0 +#define N1SDP_UART0_BASE 0x2A400000 +#define N1SDP_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define N1SDP_UART1_BASE 0x2A410000 +#define N1SDP_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define N1SDP_GENERIC_WDOG_BASE 0x2A440000 +#define N1SDP_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define N1SDP_GIC_BASE 0x30000000 +#define N1SDP_GICR_BASE 0x300C0000 +#define N1SDP_GIC_SZ SIZE_256KB +#define N1SDP_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define N1SDP_NON_SECURE_SRAM_BASE 0x06000000 +#define N1SDP_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define N1SDP_EXP_PERIPH_BASE0 0x1C000000 +#define N1SDP_EXP_PERIPH_BASE0_SZ 0x1300000 + +// Base address to a structure of type N1SDP_PLAT_INFO which is pre-popula= ted +// by a earlier boot stage +#define N1SDP_PLAT_INFO_STRUCT_BASE (N1SDP_NON_SECURE_SRAM_BASE += \ + 0x00008000) + +/* + * Platform information structure stored in non secure SRAM. Platform + * information are passed from the trusted firmware with the below structu= re + * format. The elements of N1SDP_PLAT_INFO should be always in sync with t= he + * lower level firmware. + */ +#pragma pack(1) +typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + BOOLEAN MultichipMode; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; +} N1SDP_PLAT_INFO; +#pragma pack() + +#endif diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.c b/Silicon/= ARM/N1Sdp/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..6cb699b29716 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable =3D mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { + PrePeiCoreGetMpCoreInfo +}; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c b/Silic= on/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..f545cbd6de94 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,125 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" des= criptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing + a Physical-to-Virtual Memory mapping. This = array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + N1SDP_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + + PlatInfo =3D (N1SDP_PLAT_INFO *)N1SDP_PLAT_INFO_STRUCT_BASE; + DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - N1SDP_DRAM_BLOCK1_= SIZE / SIZE_1GB) * + (UINT64)SIZE_1GB); + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + + ASSERT (VirtualMemoryMap !=3D NULL); + Index =3D 0; + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCR= IPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase =3D N1SDP_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length =3D N1SDP_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_GIC_BASE; + VirtualMemoryTable[Index].Length =3D N1SDP_GIC_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_GICR_BASE; + VirtualMemoryTable[Index].Length =3D N1SDP_GICR_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length =3D N1SDP_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_UART0_BASE; + VirtualMemoryTable[Index].Length =3D N1SDP_UART0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // DDR Primary (2GB) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_WRITE_BACK; + + // DDR Secondary (14GB) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].Length =3D DramBlock2Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_WRITE_BACK; + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D N1SDP_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].VirtualBase =3D N1SDP_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].Length =3D N1SDP_EXP_PERIPH_BASE0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Silicon/ARM/N1Sdp/Library/PlatformLib/AArch64/Helper.S b/Silic= on/ARM/N1Sdp/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..8d2069dea837 --- /dev/null +++ b/Silicon/ARM/N1Sdp/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,84 @@ +/** @file +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processo= r. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary cor= e. +// Primary core is the core responsible to initialize hardware and run UEF= I. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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