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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: 2svQLoN3BFQ29Ju5GCu576bxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591643476; bh=W/bebJVEJC3NwYUy/Hsao9PvaxrAuH9K0Q5QIWrvIqg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VDy5taIn2s7e0fdU7ppCYin0w15l/0A6rFD6VIJ4R2SOSgbyZM7Z/RjOiJ5DX8dI994 quXFQBbuGV6CKGvTR9k+8T8tpmhgVWGhjswf451Ir6eHK6qlPzPezOzmKpP94pf+9V3Js RHQn7k/2hQa+yjrkl753O1C0Z6S26SObYOU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Implement SerDesHelperLib to provide helper functions which can be used for SoC specific SerDes configuration. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm --- Notes: Changes in V5: - No Change =20 Changes in V4: - No Change =20 Changes in V3: - Change variable name LanePrtc to LaneProtocol =20 Changes in V2: - Addressed review comments for structure, variable and function names - Using BIT0 instead of 0x1u Silicon/NXP/NxpQoriqLs.dec | 1 + Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28 ++++ Silicon/NXP/Include/Library/SerDesHelperLib.h | 64 ++++++++ Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 164 ++++++++++++= ++++++++ 4 files changed, 257 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index d4d3057af509..d09a1ae194be 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -35,6 +35,7 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x00000501 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x0|UINT8|0x00000504 =20 [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf b/Sili= con/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf new file mode 100644 index 000000000000..7a781620e449 --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf @@ -0,0 +1,28 @@ +## @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SerDesHelperLib + FILE_GUID =3D 2930e932-a700-41e8-80f9-f1a2dedd2c4f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerDesHelperLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + PcdLib + +[Sources.common] + SerDesHelperLib.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes diff --git a/Silicon/NXP/Include/Library/SerDesHelperLib.h b/Silicon/NXP/In= clude/Library/SerDesHelperLib.h new file mode 100644 index 000000000000..377f020e0b3a --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDesHelperLib.h @@ -0,0 +1,64 @@ +/** SerDesHelperLib.h + The Header file for SerDesHelperLib + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_HELPER_LIB_H +#define SERDES_HELPER_LIB_H + +#include +#include + +typedef struct { + UINT16 Protocol; + UINT8 SerDesLane[FixedPcdGet8 (PcdSerDesLanes)]; +} SERDES_CONFIG; + +typedef enum { + SERDES_1 =3D 0, + SERDES_2, + SERDES_3, + SERDES_MAX +} SERDES_NUMBER; + +UINT32 +GetSerDesProtocol ( + IN INTN SerDes, + IN INTN SerDesProtocol, + IN INTN Lane, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +IsSerDesProtocolValid ( + IN INTN SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +GetSerDesMap ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesProtocolMap + ); + +VOID +SerDesInstanceProbeLanes ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c b/Silico= n/NXP/Library/SerDesHelperLib/SerDesHelperLib.c new file mode 100644 index 000000000000..ddefcc2fac98 --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c @@ -0,0 +1,164 @@ +/** SerDes.c + Provides SoC specific SerDes interface + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Function to get SerDes Lane protocol corresponding to + SerDes protocol. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param Lane SerDes Lane number. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + + @return SerDes Lane protocol. + +**/ +UINT32 +GetSerDesProtocol ( + IN INTN SerDes, + IN INTN SerDesProtocol, + IN INTN Lane, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config + ) +{ + while (Config->Protocol) { + if (Config->Protocol =3D=3D SerDesProtocol) { + return Config->SerDesLane[Lane]; + } + Config++; + } + + return SerDesMaxProtocol; +} + +/** + Function to validate input SerDes protocol. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param Config SerDes Configuration. + + @return EFI_NOT_FOUND SerDes Protocol not a valid protocol. + @return EFI_SUCCESS SerDes Protocol is a valid protocol. + +**/ +EFI_STATUS +IsSerDesProtocolValid ( + IN INTN SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN SERDES_CONFIG *Config + ) +{ + UINT8 Count; + + while (Config->Protocol) { + if (Config->Protocol =3D=3D SerDesProtocol) { + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", = SerDesProtocol)); + break; + } + Config++; + } + + if (!Config->Protocol) { + return EFI_NOT_FOUND; + } + + for (Count =3D 0; Count < SerDesNumLanes; Count++) { + if (Config->SerDesLane[Count] !=3D 0) { + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Get Lane protocol on provided SerDes Lane and execute callback function. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. +**/ +VOID +SerDesInstanceProbeLanes ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + INT8 Lane; + UINT32 LaneProtocol; + + // Invoke callback for all lanes in the SerDes instance: + for (Lane =3D 0; Lane < SerDesNumLanes; Lane++) { + LaneProtocol =3D GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerD= esMaxProtocol, Config); + ASSERT (LaneProtocol < SerDesMaxProtocol); + if (LaneProtocol !=3D 0x0) { + SerDesLaneProbeCallback (LaneProtocol, Arg); + } + } +} + +/** + Function to fill SerDes map information. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + @param SerDesProtocolMap Output SerDes protocol map of enabled device= s. + +**/ +EFI_STATUS +GetSerDesMap ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesProtocolMap + ) +{ + INTN Lane; + EFI_STATUS Status; + UINT32 LaneProtocol; + + Status =3D IsSerDesProtocolValid (SerDes, SerDesProtocol, SerDesNumLanes= , Config); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: SERDES%d[PRTCL] =3D 0x%x is not valid, Statu= s =3D %r \n", + __FUNCTION__, SerDes + 1, SerDesProtocol, Status)); + return Status; + } + + for (Lane =3D 0; Lane < SerDesNumLanes; Lane++) { + LaneProtocol =3D GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerD= esMaxProtocol, Config); + if (LaneProtocol >=3D SerDesMaxProtocol) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LaneProtoc= ol)); + return EFI_NO_MAPPING; + } + *SerDesProtocolMap |=3D (BIT0 << (LaneProtocol)); + } + + return EFI_SUCCESS; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 8 Jun 2020 18:52:59 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com CC: Wasim Khan Subject: [edk2-devel] [PATCH edk2-platforms v5 2/3] Silicon/NXP: LS1043A: Add SerDes Support Date: Tue, 9 Jun 2020 00:22:34 +0530 Message-ID: <1591642355-26470-3-git-send-email-wasim.khan@oss.nxp.com> In-Reply-To: <1591642355-26470-1-git-send-email-wasim.khan@oss.nxp.com> References: <1591642355-26470-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: PN1PR01CA0078.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::18) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from wasimk-VirtualBox.nxp.com (157.37.163.9) by PN1PR01CA0078.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3066.18 via Frontend Transport; Mon, 8 Jun 2020 18:52:56 +0000 X-Originating-IP: [157.37.163.9] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 78c1d994-4974-4fe0-7b73-08d80bdd29c2 X-MS-TrafficTypeDiagnostic: VE1PR04MB6606: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: rb4OxxW4QPGEbYzUJC7woIM1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591643476; bh=w0J3jrRWkjHkSzWBXc4MwX71jQTU6F/PBbOwlhI6n2M=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=B6RnFr3XmUYAKX+cT2+++B00xWk4yWX9WJsOAfakEFfnVDPH6dyQtanMQxjAGyx7yi8 MknlmnuR4HNY6otoU42xIhPRYuJapuzz6H0hYjHy64fEuSzi/3sW+eMK37kLwGS2mabkg gdmej66x1W+Jg43C7t9oEIazH+8Zd37Xx1M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Based on SerDes protocol value in reset configuration word (RCW) different IP blocks gets enabled in HW. Add SoC specific SerDes configuration for LS1043A, which can be used by different IPs to know the enabled interfaces and perform the required initialization. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm --- Notes: Changes in V5: - Corrected enum value and CheckPatch fix =20 Changes in V4: - Include SocSerDes.h =20 Changes in V3: - Indentation changes - Moved enum to header file. =20 Changes in V2: - Addressed review comments for structure, variable and function names - Removed SocSerDes.h and moved data definitions to SerDes.c Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 + Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 + Silicon/NXP/Include/Library/SerDes.h | 28 +++++ Silicon/NXP/LS1043A/Include/SocSerDes.h | 33 ++++++ Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 119 ++++++++++++++++++++ 5 files changed, 188 insertions(+) diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index e023bfbc7c04..1ac7c6da7092 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -12,6 +12,7 @@ [LibraryClasses.common] SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf =20 ##########################################################################= ###### # @@ -37,4 +38,5 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x4 ## diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1043A/Library/SocLib/SocLib.inf index 3d0f988e1c67..728e8f0c8ee1 100644 --- a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf @@ -22,6 +22,12 @@ [Packages] [LibraryClasses] ChassisLib DebugLib + PcdLib + SerDesHelperLib =20 [Sources.common] + SerDes.c SocLib.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes diff --git a/Silicon/NXP/Include/Library/SerDes.h b/Silicon/NXP/Include/Lib= rary/SerDes.h new file mode 100644 index 000000000000..f015b40403c5 --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDes.h @@ -0,0 +1,28 @@ +/** SerDes.h + Header file for SoC specific SerDes routines + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_H +#define SERDES_H + +VOID +GetSerDesProtocolMap ( + OUT UINT64 *SerDesProtocolMap + ); + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN UINT32 LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/= Include/SocSerDes.h new file mode 100644 index 000000000000..2fc5651c004c --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h @@ -0,0 +1,33 @@ +/** SocSerDes.h + SoC Specific header file for SerDes + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SOC_SERDES_H +#define SOC_SERDES_H + +typedef enum { + NONE =3D 0, + PCIE1, + PCIE2, + PCIE3, + SATA, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + QSGMII_FM1_A, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SERDES_PROTOCOL_COUNT +} SERDES_PROTOCOL; +#endif diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c b/Silicon/NXP/LS10= 43A/Library/SocLib/SerDes.c new file mode 100644 index 000000000000..b34da76eeac9 --- /dev/null +++ b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c @@ -0,0 +1,119 @@ +/** SerDes.c + Provides SoC specific SerDes interface + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register +#define SERDES1_PROTOCOL_MASK 0xffff0000 + +// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register +#define SERDES1_PROTOCOL_SHIFT 16 + +SERDES_CONFIG gSerDes1ConfigTable[] =3D { + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } = }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM= 1_DTSEC6 } }, + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGM= II_FM1_DTSEC6 } }, + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSE= C6 } }, + {} +}; + +SERDES_CONFIG *gSerDesConfig[] =3D { + gSerDes1ConfigTable +}; + +/** + Probe all SerDes for lane protocol and execute provided callback functio= n. + + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + UINT32 SerDesProtocol; + LS1043A_DEVICE_CONFIG *DeviceConfig; + + DeviceConfig =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SerDesProtocol =3D DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1= _PROTOCOL_MASK; + SerDesProtocol >>=3D SERDES1_PROTOCOL_SHIFT; + + SerDesInstanceProbeLanes ( + SERDES_1, + SerDesProtocol, + FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, + gSerDesConfig[SERDES_1], + SerDesLaneProbeCallback, + Arg + ); +} + +/** + Function to return SerDes protocol map for all SerDes available on board. + + @param SerDesProtocolMap Pointer to SerDes protocl map. + +**/ +VOID +GetSerDesProtocolMap ( + OUT UINT64 *SerDesProtocolMap + ) +{ + UINT32 SerDesProtocol; + LS1043A_DEVICE_CONFIG *DeviceConfig; + EFI_STATUS Status; + + *SerDesProtocolMap =3D 0; + DeviceConfig =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SerDesProtocol =3D DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1= _PROTOCOL_MASK; + SerDesProtocol >>=3D SERDES1_PROTOCOL_SHIFT; + + Status =3D GetSerDesMap ( + SERDES_1, + SerDesProtocol, + FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, + gSerDesConfig[SERDES_1], + SerDesProtocolMap + ); + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); + *SerDesProtocolMap =3D 0; + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 8 Jun 2020 18:53:02 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com CC: Wasim Khan Subject: [edk2-devel] [PATCH edk2-platforms v5 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Date: Tue, 9 Jun 2020 00:22:35 +0530 Message-ID: <1591642355-26470-4-git-send-email-wasim.khan@oss.nxp.com> In-Reply-To: <1591642355-26470-1-git-send-email-wasim.khan@oss.nxp.com> References: <1591642355-26470-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: PN1PR01CA0078.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::18) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from wasimk-VirtualBox.nxp.com (157.37.163.9) by PN1PR01CA0078.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3066.18 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: C3uwrx7PyBt5cxTrMgEMoFGmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591643475; bh=k3BN7FqNMS2uUk52yAtGse62P5NXuGuWB+03ZW08+5M=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=dkk3D6bDwnhjTy0Xa5Z7ZPOpbT5j8ZZJWOw+C7g+/lzKg6ngBGhD/jOQSQtErvOQTVp xovlNji9N+LPAVMtw9J5QruQkjg//aMYbVxnJ5Zx2taMjHtqxHkV/1ACZFvslV74SeuRT mF6D4X+ZzT9NjlrB7itCLQtF30he8mDTTIc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get SerDes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm --- Notes: Changes in V5: - No Change =20 Changes in V4: - No Change =20 Changes in V3: - No Change =20 Changes in V2: - Addressed review comments for structure, variable and function names - Using BIT0 instead of 0x1u Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++= ++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index aa5a9dec7c34..6003da708698 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -28,6 +28,7 @@ [LibraryClasses] IoAccessLib MemoryAllocationLib PcdLib + SocLib =20 [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index e5309a4f4248..8bbbaaa6e24d 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -721,6 +722,32 @@ PcieSetupCntrl ( } =20 /** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDesProtocolMap; + + SerDesProtocolMap =3D 0; + + // Reading serdes protocol map + GetSerDesProtocolMap (&SerDesProtocolMap); + + return (SerDesProtocolMap & (BIT0 << (PcieNum))) !=3D 0; +} + +/** Return all the root bridge instances in an array. =20 @param Count Return the count of root bridge instances. @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges ( PciPhyIoAddr [Idx] =3D PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); Regs[Idx] =3D PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); =20 + // Check is the PCIe controller is enabled + if (IsPcieNumEnabled (Idx + 1) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Re= gs[Idx])); + continue; + } + // Check PCIe Link LinkUp =3D PcieLinkUp(Regs[Idx], Idx); =20 if (!LinkUp) { continue; } - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx += 1, Regs[Idx])); // Set up PCIe Controller and ATU windows PcieSetupCntrl (Regs[Idx], PciPhyCfg0Addr[Idx], --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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