From nobody Tue Feb 10 13:36:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+60759+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60759+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1591357488; cv=none; d=zohomail.com; s=zohoarc; b=MaDbYDHNfVA6kxVL4MVWYd8m8xYQXE/MwVOb5oDXR12MyAR6V9PwipDAUwWHeO7bm1SbLiQC0SdyQxuzM8mx6HyckioAzTfGcZ2aVUKNl3D7pjLPrn/8yPWI2bwKr++bPTzIcMAR9JOY4ipMGlH8BdmaTNb//zNbzyEw8QrYKT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591357488; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=003P2ruHkhZViawKu0rRQEGtq+VOISA5GsYyKPmvHVA=; b=YMPZ5ktgGqozQBnWbgQB7/9WdUa/lkKN+1Kx2aRxFWuQjDcvN75qijOOuu9e+P19BgyG7qnIM1qJwURTU2pQ+knSzQAZTrH3Nbzpz1A9lc5Ne/l58aA56DMN3axvw9AZpnwx+z93vmBmHBe48Q5LukCF3S2dE3g51RpA4A6ldSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60759+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1591357488805903.5451705786664; Fri, 5 Jun 2020 04:44:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PmtvYY1788612xSDLFo5EUnY; Fri, 05 Jun 2020 04:44:48 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.7945.1591352444408790423 for ; Fri, 05 Jun 2020 03:20:44 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E80371A1F65; Fri, 5 Jun 2020 12:20:42 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8EBC61A047D; Fri, 5 Jun 2020 12:20:42 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 688D833B; Fri, 5 Jun 2020 15:50:41 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal , Meenakshi Aggarwal Subject: [edk2-devel] [PATCH edk2-platforms 1/2] Silicon/NXP: Add SATA controller initialization driver Date: Fri, 5 Jun 2020 21:32:53 +0530 Message-Id: <1591372974-7860-2-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1591372974-7860-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1591372974-7860-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: Mj6JOiaB3VaalaDKa2wbbRkMx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591357488; bh=l5M13P2ZxTXVn0UrIKV1fb4IXmkH2V5eDa7pdERg3kg=; h=Cc:Date:From:Reply-To:Subject:To; b=BRWMBxngj4Cwt0FxQJ1bQPqxk4GiGEdr3/tH/bQZwupewvstzI6E6gziUUAAbJEfQrm cJJYQ14b2SXoDqhz8BgH5h6YarWAgfKB0QEe6wrGdTwGOFmJvRDqPRwwxw8ghqAJ7chUW BAp0Y2twHLHKZEbaFeDQLgSV3dJ3wgkH1e8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support of SATA controller driver which performs controller initialization and register itself as NonDiscoverableMmioDevice Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/NxpQoriqLs.dec | 6 + Silicon/NXP/NxpQoriqLs.dsc.inc | 10 ++ Silicon/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 46 ++++++++ Silicon/NXP/Drivers/SataInitDxe/SataInit.h | 27 +++++ Silicon/NXP/Drivers/SataInitDxe/SataInit.c | 116 ++++++++++++++++++++ 5 files changed, 205 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 72c1744fc934..e83f282ace4e 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -28,6 +28,7 @@ [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315 gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316 gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318 =20 [PcdsFixedAtBuild.common] # Pcds for PCI Express @@ -41,6 +42,11 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000511 gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000512 =20 + # Pcds for SATA + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT64|0x00000350 + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351 + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352 + [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601 diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 1f0f272da6c7..399ac5de9176 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -101,6 +101,7 @@ [LibraryClasses.common] =20 PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.i= nf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf =20 [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf @@ -378,6 +379,15 @@ [Components.common] MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf =20 # + # AHCI Support + # + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + # # Bds # MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf diff --git a/Silicon/NXP/Drivers/SataInitDxe/SataInitDxe.inf b/Silicon/NXP/= Drivers/SataInitDxe/SataInitDxe.inf new file mode 100644 index 000000000000..06b6c2ac6ff9 --- /dev/null +++ b/Silicon/NXP/Drivers/SataInitDxe/SataInitDxe.inf @@ -0,0 +1,46 @@ +## @file +# Component description file for the Sata Controller initialization driver +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SataInit + FILE_GUID =3D 021722D8-522B-4079-852A-FE44C2C13F49 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeSataController + +[Sources] + SataInit.c + SataInit.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdSataSize + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Silicon/NXP/Drivers/SataInitDxe/SataInit.h b/Silicon/NXP/Drive= rs/SataInitDxe/SataInit.h new file mode 100644 index 000000000000..edaf0bdda72c --- /dev/null +++ b/Silicon/NXP/Drivers/SataInitDxe/SataInit.h @@ -0,0 +1,27 @@ +/** @file + Header file for Sata Controller initialization driver. + + Copyright 2017-2018, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#ifndef SATA_INIT_H_ +#define SATA_INIT_H_ + +// +// Offset for AHCI base address in PCI Header +// +#define PCI_AHCI_BASE_ADDRESS 0x24 + +#define SATA_PPCFG 0xA8 +#define SATA_PTC 0xC8 +#define SATA_PAXIC 0xC0 + +#define PORT_PHYSICAL 0xA003FFFE +#define PORT_TRANSPORT 0x08000025 +#define PORT_RXWM 0x08000029 +#define ENABLE_NONZERO_4MB_PRD 0x10000000 + +#endif diff --git a/Silicon/NXP/Drivers/SataInitDxe/SataInit.c b/Silicon/NXP/Drive= rs/SataInitDxe/SataInit.c new file mode 100644 index 000000000000..c678b63652e7 --- /dev/null +++ b/Silicon/NXP/Drivers/SataInitDxe/SataInit.c @@ -0,0 +1,116 @@ +/** @file + This driver module adds SATA controller support. + + Copyright 2017-2018, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include +#include + +#include "SataInit.h" + +/** + This function gets registered as a callback to perform USB controller in= tialization + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +VOID +EFIAPI +SataEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINT32 NumSataController; + UINT32 Index; + UINT32 Data; + UINTN ControllerAddr; + + NumSataController =3D PcdGet32 (PcdNumSataController); + + for (Index =3D 0; Index < NumSataController; Index++) { + ControllerAddr =3D PcdGet64 (PcdSataBaseAddr) + + (Index * PcdGet32 (PcdSataSize)); + + // + // configuring Physical Control Layer parameters for Port 0 + // + MmioWrite32 ((UINTN)(ControllerAddr + SATA_PPCFG), PORT_PHYSICAL); + + // + // This register controls the configuration of the + // Transport Layer for Port 0 + // Errata Description : The default Rx watermark value may be insuffic= ient + // for some hard drives and result in a false CRC or internal errors. + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do not c= hange + // the other reserved fields of the register. + // + + Data =3D MmioRead32 ((UINTN)(ControllerAddr + SATA_PTC)); + if (PcdGetBool (PcdSataErratumA009185)) { + Data |=3D PORT_RXWM; + } else { + Data |=3D PORT_TRANSPORT; + } + MmioWrite32 ((UINTN)(ControllerAddr + SATA_PTC), Data); + + // + // Enable Non-Zero 4 MB PRD entries. + // + MmioOr32 ((UINTN)(ControllerAddr + SATA_PAXIC), ENABLE_NONZERO_4MB_PRD= ); + + Status =3D RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeAhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + ControllerAddr, PcdGet32 (PcdSataSize) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register SATA device 0x%x, error 0x%= r \n", + ControllerAddr, Status)); + } + } +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI i= mage. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval Other Some error occurs when executing this entry= point + +**/ +EFI_STATUS +EFIAPI +InitializeSataController ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SataEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + return Status; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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