From nobody Fri May 3 06:38:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+60656+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60656+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1591181182; cv=none; d=zohomail.com; s=zohoarc; b=DKMtatuQ5tx+LAojmoVRPZGgZbnLDa5knOBonwrZztK4zWBzGf3z9Ln7SqvochYYhkk5fPKlIfSrgZIBwVXoPv+lxC53dHo+JuLrOLW2in7MEknFwYG4DZDWtTDmTDE450DTVznUWVmvKFIXrHgxFhR8A4HuYCiRB00pz1O+bNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591181182; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=roZJkj31BHvdPcPfkk5UTx3Il7daH+Dsq47hbKuQj3Y=; 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Wed, 3 Jun 2020 12:19:01 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5D0EE1A00F6; Wed, 3 Jun 2020 12:19:01 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id EACD4326; Wed, 3 Jun 2020 15:48:59 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [PATCH edk2-platforms V2 1/2] Silicon/NXP: Add DWC3 USB controller initialization driver Date: Wed, 3 Jun 2020 21:30:41 +0530 Message-Id: <1591200042-11232-2-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1591200042-11232-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1591105661-29757-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1591200042-11232-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: zia98SnWcXqWnUMqRb1yIDwkx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591181181; bh=R5ylxH7z2K7vqOeQjkJoMmCGSj/swcVHnxuCgHf5ado=; h=Cc:Date:From:Reply-To:Subject:To; b=p9knubyBW6C7ouw5O2kYaIsEtU6VVQ0zh/1NDpyQie+SFFZm368UbV5b+O9JV8OqVcS 5A2YdZdD/HQfOYPlPnbISk1QdFV1bFXRMJzk91B3zbB+sOJfJH7byw6B2JoXdCSO4fJ5D RKFSh2F2RydqZ/VGUYuWhP9kfF7g5BtoCm4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Add support of DWC3 controller driver which performs DWC3 controller initialization and register itself as NonDiscoverableMmioDevice Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/NxpQoriqLs.dec | 5 + Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 45 ++++ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 138 ++++++++++ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 281 ++++++++++++++++++++ 4 files changed, 469 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index d4d3057af509..72c1744fc934 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -36,6 +36,11 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 =20 + # Pcds for USB + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT64|0x00000510 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000511 + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000512 + [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601 diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Dri= vers/UsbHcdInitDxe/UsbHcd.inf new file mode 100644 index 000000000000..ea7532b4324b --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf @@ -0,0 +1,45 @@ +# UsbHcd.inf +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D UsbHcdDxe + FILE_GUID =3D 196e7c2a-37b2-4b85-8683-718588952449 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeUsbHcd + +[Sources.common] + UsbHcd.c + UsbHcd.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drive= rs/UsbHcdInitDxe/UsbHcd.h new file mode 100644 index 000000000000..cd9f9ad80125 --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h @@ -0,0 +1,138 @@ +/** @file + + Copyright 2017, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef USB_HCD_H_ +#define USB_HCD_H_ + +#include + +/* Global constants */ +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_SYNOPSYS_ID 0x55330000 +#define DWC3_RELEASE_MASK 0xffff +#define DWC3_REG_OFFSET 0xC100 +#define DWC3_RELEASE_190a 0x190a + +/* Global Configuration Register */ +#define DWC3_GCTL_U2RSTECN BIT16 +#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_CORESOFTRESET BIT11 +#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE BIT3 +#define DWC3_GCTL_DSBLCLKGTNG BIT0 + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31 + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31 + +/* Global Frame Length Adjustment Register */ +#define GFLADJ_30MHZ_REG_SEL BIT7 +#define GFLADJ_30MHZ(N) ((N) & 0x3f) +#define GFLADJ_30MHZ_DEFAULT 0x20 + +/* Default to the FSL XHCI defines */ +#define USB3_ENABLE_BEAT_BURST 0xF +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF +#define USB3_SET_BEAT_BURST_LIMIT 0xF00 + +typedef struct { + UINT32 GEvntAdrLo; + UINT32 GEvntAdrHi; + UINT32 GEvntSiz; + UINT32 GEvntCount; +} G_EVENT_BUFFER; + +typedef struct { + UINT32 DDepCmdPar2; + UINT32 DDepCmdPar1; + UINT32 DDepCmdPar0; + UINT32 DDepCmd; +} D_PHYSICAL_EP; + +typedef struct { + UINT32 GSBusCfg0; + UINT32 GSBusCfg1; + UINT32 GTxThrCfg; + UINT32 GRxThrCfg; + UINT32 GCtl; + UINT32 Res1; + UINT32 GSts; + UINT32 Res2; + UINT32 GSnpsId; + UINT32 GGpio; + UINT32 GUid; + UINT32 GUctl; + UINT64 GBusErrAddr; + UINT64 GPrtbImap; + UINT32 GHwParams0; + UINT32 GHwParams1; + UINT32 GHwParams2; + UINT32 GHwParams3; + UINT32 GHwParams4; + UINT32 GHwParams5; + UINT32 GHwParams6; + UINT32 GHwParams7; + UINT32 GDbgFifoSpace; + UINT32 GDbgLtssm; + UINT32 GDbgLnmcc; + UINT32 GDbgBmu; + UINT32 GDbgLspMux; + UINT32 GDbgLsp; + UINT32 GDbgEpInfo0; + UINT32 GDbgEpInfo1; + UINT64 GPrtbImapHs; + UINT64 GPrtbImapFs; + UINT32 Res3[28]; + UINT32 GUsb2PhyCfg[16]; + UINT32 GUsb2I2cCtl[16]; + UINT32 GUsb2PhyAcc[16]; + UINT32 GUsb3PipeCtl[16]; + UINT32 GTxFifoSiz[32]; + UINT32 GRxFifoSiz[32]; + G_EVENT_BUFFER GEvntBuf[32]; + UINT32 GHwParams8; + UINT32 Res4[11]; + UINT32 GFLAdj; + UINT32 Res5[51]; + UINT32 DCfg; + UINT32 DCtl; + UINT32 DEvten; + UINT32 DSts; + UINT32 DGCmdPar; + UINT32 DGCmd; + UINT32 Res6[2]; + UINT32 DAlepena; + UINT32 Res7[55]; + D_PHYSICAL_EP DPhyEpCmd[32]; + UINT32 Res8[128]; + UINT32 OCfg; + UINT32 OCtl; + UINT32 OEvt; + UINT32 OEvtEn; + UINT32 OSts; + UINT32 Res9[3]; + UINT32 AdpCfg; + UINT32 AdpCtl; + UINT32 AdpEvt; + UINT32 AdpEvten; + UINT32 BcCfg; + UINT32 Res10; + UINT32 BcEvt; + UINT32 BcEvten; +} DWC3; + +#endif diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drive= rs/UsbHcdInitDxe/UsbHcd.c new file mode 100644 index 000000000000..515853b86253 --- /dev/null +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c @@ -0,0 +1,281 @@ +/** @file + + Copyright 2017, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "UsbHcd.h" + +STATIC +VOID +XhciSetBeatBurstLength ( + IN UINTN UsbReg + ) +{ + DWC3 *Dwc3Reg; + + Dwc3Reg =3D (VOID *)(UsbReg + DWC3_REG_OFFSET); + + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MAS= K, + USB3_ENABLE_BEAT_BURST); + + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT); +} + +STATIC +VOID +Dwc3SetFladj ( + IN DWC3 *Dwc3Reg, + IN UINT32 Val + ) +{ + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL | + GFLADJ_30MHZ (Val)); +} + +STATIC +VOID +Dwc3SetMode ( + IN DWC3 *Dwc3Reg, + IN UINT32 Mode + ) +{ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl, + ~(DWC3_GCTL_PRTCAPDIR (DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR (Mode)); +} + +/** + This function issues phy reset and core soft reset + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +VOID +Dwc3CoreSoftReset ( + IN DWC3 *Dwc3Reg + ) +{ + // + // Put core in reset before resetting PHY + // + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET); + + // + // Assert USB2 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST= ); + + // + // Assert USB3 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Clear USB3 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTR= ST); + + // + // Clear USB2 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Take core out of reset, PHYs are stable now + // + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET); +} + +/** + This function performs low-level initialization of DWC3 Core + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +EFI_STATUS +Dwc3CoreInit ( + IN DWC3 *Dwc3Reg + ) +{ + UINT32 Revision; + UINT32 Reg; + UINTN Dwc3Hwparams1; + + Revision =3D MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId); + // + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revisio= n num + // + if ((Revision & DWC3_GSNPSID_MASK) !=3D DWC3_SYNOPSYS_ID) { + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n")); + return EFI_NOT_FOUND; + } + + Dwc3CoreSoftReset (Dwc3Reg); + + Reg =3D MmioRead32 ((UINTN)&Dwc3Reg->GCtl); + Reg &=3D ~DWC3_GCTL_SCALEDOWN_MASK; + Reg &=3D ~DWC3_GCTL_DISSCRAMBLE; + + Dwc3Hwparams1 =3D MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1); + + if (DWC3_GHWPARAMS1_EN_PWROPT (Dwc3Hwparams1) =3D=3D + DWC3_GHWPARAMS1_EN_PWROPT_CLK) { + Reg &=3D ~DWC3_GCTL_DSBLCLKGTNG; + } else { + DEBUG ((DEBUG_WARN,"No power optimization available.\n")); + } + + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) { + Reg |=3D DWC3_GCTL_U2RSTECN; + } + + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +XhciCoreInit ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + DWC3 *Dwc3Reg; + + Dwc3Reg =3D (VOID *)(UsbReg + DWC3_REG_OFFSET); + + Status =3D Dwc3CoreInit (Dwc3Reg); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%r) \= n", + UsbReg, Status)); + + return Status; + } + + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST); + + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + + Status =3D XhciCoreInit (UsbReg); + + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Change beat burst and outstanding pipelined transfers requests + // + XhciSetBeatBurstLength (UsbReg); + + return Status; +} + +/** + This function gets registered as a callback to perform USB controller in= tialization + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +VOID +EFIAPI +UsbEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINT32 NumUsbController; + UINT32 ControllerAddr; + UINT32 Index; + + gBS->CloseEvent (Event); + + NumUsbController =3D PcdGet32 (PcdNumUsbController); + + for (Index =3D 0; Index < NumUsbController; Index++) { + ControllerAddr =3D PcdGet64 (PcdUsbBaseAddr) + + (Index * PcdGet32 (PcdUsbSize)); + + Status =3D InitializeUsbController (ControllerAddr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USB Controller init Failed for %d (0x%r)\n", + ControllerAddr, Status)); + continue; + } + + Status =3D RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeXhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + ControllerAddr, PcdGet32 (PcdUsbSize) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register USB device 0x%x, error 0x%r= \n", + ControllerAddr, Status)); + } + } +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry poi= nt. + +**/ +EFI_STATUS +EFIAPI +InitializeUsbHcd ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + UsbEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + return Status; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60656): https://edk2.groups.io/g/devel/message/60656 Mute This Topic: https://groups.io/mt/74646954/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 06:38:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+60657+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60657+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=oss.nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1591181182; cv=none; d=zohomail.com; s=zohoarc; b=SGwUo8t+/fFo0fUaVkLNUownxnunzFQa1OQ3bFUW2288ia2Rq+hMxkYoeQMM809w1Sb00Y92spNau0Lz5kPXGQQHpTyCVQB0NDAC/skTKhN6mK8AEVmCOvHLurnrTB0GCeO/c8tJl6L0QP0qsD+q9ADyjdTqA3F+NYYFlHBCJEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591181182; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=q/bG7AYniHFSaJmtKNfeopXBq2ROqxkDdsIYxVHUgmw=; b=CGwb28gL7hb+rnW/Nq12c7lIzYa6iz/VEyA+kfbyjPb7VGmDIf4lalW+mfFpN9amE9+ZWYyhRT+pzrXXXPYdQqHXn259CMEYlubcfy7/tGDLB0dRIq9e6hqEXOmURPYo6Bwm7MUIMclPvk9ZT7lTxK8ul7ZYX8+4fK1pZtn1A3U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60657+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1591181182522995.1531006982088; Wed, 3 Jun 2020 03:46:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id e6ucYY1788612xciRO88VNGm; Wed, 03 Jun 2020 03:46:22 -0700 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.10585.1591179545723479457 for ; Wed, 03 Jun 2020 03:19:06 -0700 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 51D0F1A0FFB; Wed, 3 Jun 2020 12:19:04 +0200 (CEST) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id ECEFA1A1006; Wed, 3 Jun 2020 12:19:03 +0200 (CEST) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id B35D9326; Wed, 3 Jun 2020 15:49:02 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@arm.com, leif@nuviainc.com, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [PATCH edk2-platforms V2 2/2] Platform/NXP:LX2160: Enable support of USB controller Date: Wed, 3 Jun 2020 21:30:42 +0530 Message-Id: <1591200042-11232-3-git-send-email-meenakshi.aggarwal@oss.nxp.com> In-Reply-To: <1591200042-11232-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> References: <1591105661-29757-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1591200042-11232-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@oss.nxp.com X-Gm-Message-State: 6LaDaI95aj1UDXMMUT4sclUrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591181182; bh=fI4j0X0y9xjXGsRpudAPw/cwjltSKmAS++p45m0z5r0=; h=Cc:Date:From:Reply-To:Subject:To; b=EWaSMcawaXWM3jXaN0gmFZb8w0oJFUY1kJzIR3OSBozA41uFzJzcDFBTCGiyTKiAxwZ iTzJhMZpDC1ju2AJa40BU9OxpsPHQnqZM6eyT4T7W2m867xYvGNwlNllu/Yclv7FXfTqA h8n2jIIR4te7elzP5j75h5oWRa9099i2r2g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Meenakshi Aggarwal Enable support of USB drives on lx2160 RDB board. LX2160 has DWC3 controller Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/LX2160A/LX2160A.dsc.inc | 4 ++++ Silicon/NXP/NxpQoriqLs.dsc.inc | 12 ++++++++++++ Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 1 + Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 18 +++++++++++++++--- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX21= 60A.dsc.inc index af22b4dd973c..55dd3b5442eb 100644 --- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc @@ -36,6 +36,10 @@ [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 =20 + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2 + [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE =20 diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index ee639d552483..1f0f272da6c7 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -366,6 +366,18 @@ [Components.common] FatPkg/EnhancedFatDxe/Fat.inf =20 # + # USB + # + + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf + + # # Bds # MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.dsc index 9b3e0386c13e..ec27a1a219a5 100644 --- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc @@ -43,4 +43,5 @@ [Components.common] gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE } =20 + Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf ## diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.fdf index eec1c0774a86..5cb809e8b3a0 100644 --- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf @@ -23,10 +23,10 @@ =20 [FD.LX2160ARDB_EFI] BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. -Size =3D 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +Size =3D 0x00160000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D 0x10000 -NumBlocks =3D 0x14 +NumBlocks =3D 0x16 =20 ##########################################################################= ###### # @@ -43,7 +43,7 @@ [FD.LX2160ARDB_EFI] # RegionType # ##########################################################################= ###### -0x00000000|0x00140000 +0x00000000|0x00160000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV =3D FVMAIN_COMPACT =20 @@ -120,6 +120,18 @@ [FV.FvMain] INF FatPkg/EnhancedFatDxe/Fat.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf =20 + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf # # UEFI application (Shell Embedded Boot Loader) # --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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