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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: DimhzE8bScbAu8WcapkaUbtNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591039850; bh=RdfAsVQXQdNifcrVMUu6/gWmDwLmXj7NyUDPKQ15IlE=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=aIpHE0aNriPNIgjsST4w+2i6eSBarZpW34YYqN5uvfQpk91L4aXsqqPPrH19hqcBgU1 Qc6pQ4agkQouuKAY90phHTAro8ZXwk9L4N9lxAV31rnaDXvrfMs++zAC4K5eAlRTo19KB QJoUNu5ReMBLRrQxZtF0zfIYYJV7VQYEofM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Implement SerDesHelperLib to provide helper functions which can be used for SoC specific serdes configuration. Signed-off-by: Wasim Khan --- Silicon/NXP/NxpQoriqLs.dec | 1 + Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28 ++++ Silicon/NXP/Include/Library/SerDesHelperLib.h | 64 ++++++++ Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 165 ++++++++++++= ++++++++ 4 files changed, 258 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index d4d3057af509..720bb5794960 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -35,6 +35,7 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x00000501 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 + gNxpQoriqLsTokenSpaceGuid.PcdSerdesLanes|0x0|UINT8|0x00000504 =20 [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf b/Sili= con/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf new file mode 100644 index 000000000000..05814c986393 --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf @@ -0,0 +1,28 @@ +## @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocHelperLib + FILE_GUID =3D 2930e932-a700-41e8-80f9-f1a2dedd2c4f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerDesHelperLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + PcdLib + +[Sources.common] + SerDesHelperLib.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerdesLanes diff --git a/Silicon/NXP/Include/Library/SerDesHelperLib.h b/Silicon/NXP/In= clude/Library/SerDesHelperLib.h new file mode 100644 index 000000000000..ef08c3edc30a --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDesHelperLib.h @@ -0,0 +1,64 @@ +/** SerDesHelperLib.h + The Header file for SerdesHelperLib + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_HELPER_LIB_H +#define SERDES_HELPER_LIB_H + +#include +#include + +typedef struct { + UINT16 Protocol; + UINT8 SrdsLane[FixedPcdGet8 (PcdSerdesLanes)]; +} SERDES_CONFIG; + +typedef enum { + SRDS_1 =3D 0, + SRDS_2, + SRDS_3, + SRDS_MAX_NUM +} SERDES_NUMBER; + +UINT32 +GetSerDesPrtcl ( + IN INTN SerDes, + IN INTN Cfg, + IN INTN Lane, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +CheckSerDesPrtclValid ( + IN INTN SerDes, + IN UINT32 Prtcl, + IN UINT8 SerdesLanes, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +GetSerDesMap ( + IN UINT32 Srds, + IN UINT32 SrdsProt, + IN UINT8 SerdesLanes, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesPrtclMap + ); + +VOID +SerDesInstanceProbeLanes ( + IN UINT32 Srds, + IN UINT32 SrdsProt, + IN UINT8 SerdesLanes, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c b/Silico= n/NXP/Library/SerDesHelperLib/SerDesHelperLib.c new file mode 100644 index 000000000000..54d0a6181707 --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c @@ -0,0 +1,165 @@ +/** SerDes.c + Provides SoC specific serdes interface + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Function to get serdes Lane protocol corresponding to + serdes protocol. + + @param SerDes Serdes number. + @param Cfg Serdes Protocol. + @param Lane Serdes Lane number. + @param SerdesMaxProtocol Max Serdes protocol number. + @param Config Serdes Configuration. + + @return Serdes Lane protocol. + +**/ +UINT32 +GetSerDesPrtcl ( + IN INTN SerDes, + IN INTN Cfg, + IN INTN Lane, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config + ) +{ + while (Config->Protocol) { + if (Config->Protocol =3D=3D Cfg) { + return Config->SrdsLane[Lane]; + } + Config++; + } + + return SerdesMaxProtocol; +} + +/** + Function to validate input serdes protocol. + + @param SerDes Serdes number. + @param Prtcl Serdes Protocol to be verified. + @param SerdesLanes Number of Serdes Lanes + @param Config Serdes Configuration. + + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol. + @return EFI_SUCCESS Serdes Protocol is a valid protocol. + +**/ +EFI_STATUS +CheckSerDesPrtclValid ( + IN INTN SerDes, + IN UINT32 Prtcl, + IN UINT8 SerdesLanes, + IN SERDES_CONFIG *Config + ) +{ + UINT8 Cnt; + + while (Config->Protocol) { + if (Config->Protocol =3D=3D Prtcl) { + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", = Prtcl)); + break; + } + Config++; + } + + if (!Config->Protocol) { + return EFI_NOT_FOUND; + } + + for (Cnt =3D 0; Cnt < SerdesLanes; Cnt++) { + if (Config->SrdsLane[Cnt] !=3D 0) { + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Get lane protocol on provided serdes lane and execute callback function. + + @param Srds Serdes number. + @param SrdsProt Serdes protocol number. + @param SerdesLanes Number of Serdes Lanes + @param SerdesMaxProtocol Max Serdes protocol number. + @param Config Serdes Configuration. + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesInstanceProbeLanes ( + IN UINT32 Srds, + IN UINT32 SrdsProt, + IN UINT8 SerdesLanes, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + INT8 Lane; + UINT32 LanePrtcl; + + // Invoke callback for all lanes in the SerDes instance: + for (Lane =3D 0; Lane < SerdesLanes; Lane++) { + LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane, SerdesMaxProtocol,= Config); + ASSERT (LanePrtcl < SerdesMaxProtocol); + if (LanePrtcl !=3D 0x0) { + SerDesLaneProbeCallback (LanePrtcl, Arg); + } + } +} + +/** + Function to fill serdes map information. + + @param Srds Serdes number. + @param SrdsProt Serdes protocol number. + @param SerdesLanes Number of Serdes Lanes. + @param SerdesMaxProtocol Max Serdes protocol number. + @param Config Serdes Configuration. + @param SerDesPrtclMap Output Serdes protocol map of enabled device= s. + +**/ +EFI_STATUS +GetSerDesMap ( + IN UINT32 Srds, + IN UINT32 SrdsProt, + IN UINT8 SerdesLanes, + IN UINT32 SerdesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesPrtclMap + ) +{ + INTN Lane; + EFI_STATUS Status; + UINT32 LanePrtcl; + + Status =3D CheckSerDesPrtclValid (Srds, SrdsProt, SerdesLanes, Config); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: SERDES%d[PRTCL] =3D 0x%x is not valid, Statu= s =3D %r \n", + __FUNCTION__, Srds + 1, SrdsProt, Status)); + return Status; + } + + for (Lane =3D 0; Lane < SerdesLanes; Lane++) { + LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane, SerdesMaxProtocol,= Config); + if (LanePrtcl >=3D SerdesMaxProtocol) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); + return EFI_NO_MAPPING; + } + *SerDesPrtclMap |=3D (0x1u << (LanePrtcl)); + } + + return EFI_SUCCESS; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 1 Jun 2020 19:28:05 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com CC: Wasim Khan Subject: [edk2-devel] [PATCH edk2-platforms 2/3] Silicon/NXP: LS1043A: Add Serdes Support Date: Tue, 2 Jun 2020 00:57:37 +0530 Message-ID: <1591039658-18541-3-git-send-email-wasim.khan@oss.nxp.com> In-Reply-To: <1591039658-18541-1-git-send-email-wasim.khan@oss.nxp.com> References: <1591039658-18541-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: PN1PR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::22) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from wasimk-VirtualBox.nxp.com (157.37.140.9) by PN1PR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3045.18 via Frontend Transport; Mon, 1 Jun 2020 19:28:03 +0000 X-Originating-IP: [157.37.140.9] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c8dafbd8-f784-45d1-cad2-08d80661e876 X-MS-TrafficTypeDiagnostic: VE1PR04MB6768: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: b4dus6xSoemvIBTFwFZC8ZZzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591039851; bh=RFBR5o2NX2nnhB39hl5y9NDW0olBdXv/1APOBZxKp6k=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VTwjYVTPefBcUeuf4+1RC2oxI6xz/iUoliVaSQmjcNjWGP7rlDLGEbKqs31CNbrsun7 x1yRw3P9jZh1THiP68iTecWN5Ecpev5QKmX7OjoVddRo/fiod/t/fRmbX/kRLBbWkyd9L X9WEpwEKXKFJHdbPEyOCGudsvFicj6rAkZM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Based on serdes protocol value in reset configuration word (RCW) different IP blocks gets enabled in HW. Add SoC specific serdes configuration for LS1043A, which can be used by different IPs to know the enabled interfaces and perform the required initialization. Signed-off-by: Wasim Khan --- Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 + Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 ++ Silicon/NXP/Include/Library/SerDes.h | 28 ++++++++ Silicon/NXP/LS1043A/Include/SocSerDes.h | 68 ++++++++++++++++++ Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 75 ++++++++++++++++++++ 5 files changed, 179 insertions(+) diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index e023bfbc7c04..b598b5790b65 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -12,6 +12,7 @@ [LibraryClasses.common] SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf =20 ##########################################################################= ###### # @@ -37,4 +38,5 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC + gNxpQoriqLsTokenSpaceGuid.PcdSerdesLanes|0x4 ## diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS= 1043A/Library/SocLib/SocLib.inf index 3d0f988e1c67..4731bea8b92e 100644 --- a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf @@ -22,6 +22,12 @@ [Packages] [LibraryClasses] ChassisLib DebugLib + PcdLib + SerDesHelperLib =20 [Sources.common] SocLib.c + SerDes.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerdesLanes diff --git a/Silicon/NXP/Include/Library/SerDes.h b/Silicon/NXP/Include/Lib= rary/SerDes.h new file mode 100644 index 000000000000..d846589401c6 --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDes.h @@ -0,0 +1,28 @@ +/** SerDes.h + Header file for SoC specific Serdes routines + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_H +#define SERDES_H + +VOID +GetSerdesProtocolMaps ( + OUT UINT64 *SerDesPrtclMap + ); + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN UINT32 LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/= Include/SocSerDes.h new file mode 100644 index 000000000000..5bf93cb32df6 --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h @@ -0,0 +1,68 @@ +/** @file + SoC Specific header file for Serdes mapping + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SOC_SERDES_H +#define SOC_SERDES_H + +typedef enum { + NONE =3D 0, + PCIE1, + PCIE2, + PCIE3, + SATA, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + QSGMII_FM1_A, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SERDES_PRTCL_COUNT +} SERDES_PROTOCOL; + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + /* SerDes 1 */ + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } = }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM= 1_DTSEC6 } }, + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGM= II_FM1_DTSEC6 } }, + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSE= C6 } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl +}; +#endif diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c b/Silicon/NXP/LS10= 43A/Library/SocLib/SerDes.c new file mode 100644 index 000000000000..c27367621168 --- /dev/null +++ b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c @@ -0,0 +1,75 @@ +/** SerDes.c + Provides SoC specific serdes interface + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000 +#define RCWSR_SRDS1_PRTCL_SHIFT 16 + +/** + Probe all serdes lanes for lane protocol and execute provided callback f= unction. + + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + UINT32 SrdsProt; + LS1043A_DEVICE_CONFIG *Dcfg; + + Dcfg =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SrdsProt =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[4]) & RCWSR_SRDS1_PRTCL_MAS= K; + SrdsProt >>=3D RCWSR_SRDS1_PRTCL_SHIFT; + + SerDesInstanceProbeLanes (SRDS_1, SrdsProt, + FixedPcdGet8 (PcdSerdesLanes), + SERDES_PRTCL_COUNT, + SerDesConfigTbl[SRDS_1], + SerDesLaneProbeCallback, + Arg); +} + +/** + Function to return Serdes protocol map for all serdes available on board. + + @param SerDesPrtclMap Pointer to Serdes protocl map. + +**/ +VOID +GetSerdesProtocolMaps ( + OUT UINT64 *SerDesPrtclMap + ) +{ + UINT32 SrdsProt; + LS1043A_DEVICE_CONFIG *Dcfg; + EFI_STATUS Status; + + *SerDesPrtclMap =3D 0x0; + Dcfg =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SrdsProt =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[4]) & RCWSR_SRDS1_PRTCL_MAS= K; + SrdsProt >>=3D RCWSR_SRDS1_PRTCL_SHIFT; + + Status =3D GetSerDesMap (SRDS_1, SrdsProt, FixedPcdGet8 (PcdSerdesLanes), + SERDES_PRTCL_COUNT, SerDesConfigTbl[SRDS_1], + SerDesPrtclMap); + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: failed for Serdes1 \n",__FUNCTION__)); + *SerDesPrtclMap =3D 0x0; + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 1 Jun 2020 19:28:08 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com CC: Wasim Khan Subject: [edk2-devel] [PATCH edk2-platforms 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Date: Tue, 2 Jun 2020 00:57:38 +0530 Message-ID: <1591039658-18541-4-git-send-email-wasim.khan@oss.nxp.com> In-Reply-To: <1591039658-18541-1-git-send-email-wasim.khan@oss.nxp.com> References: <1591039658-18541-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: PN1PR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::22) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from wasimk-VirtualBox.nxp.com (157.37.140.9) by PN1PR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3045.18 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,wasim.khan@oss.nxp.com X-Gm-Message-State: d0BVsZ6dS1ApORoDjaLd5ZUKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591039851; bh=Ug6Uk3/L1RKO4OzZiwOlCmuvxoIGykk9pVFqtcUPMww=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=aUInrYvhGIcnUS5i7cc3CVAnHo3gXvMI9qRqCkX9LEzn2ufn6N3DMOT4MGUGCLlfJLy J4bkVdyWDa9QeG1KxpP91XVF71416m8yQwXlvfvYFQiEyQAUk5RVbod4XdCA8WCu1ZFQz SjIcIAO+YEgHRWjhfpt1DTYGp8i91tLlc9M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Wasim Khan Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get serdes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan --- Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++= ++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index aa5a9dec7c34..6003da708698 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -28,6 +28,7 @@ [LibraryClasses] IoAccessLib MemoryAllocationLib PcdLib + SocLib =20 [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 549f4fa133fb..323afc2015ae 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -719,6 +720,32 @@ PcieSetupCntrl ( } =20 /** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDesProtocolMap; + + SerDesProtocolMap =3D 0x0; + + // Reading serdes protocol map + GetSerdesProtocolMaps (&SerDesProtocolMap); + + return (SerDesProtocolMap & (0x1u << (PcieNum))) !=3D 0 ; +} + +/** Return all the root bridge instances in an array. =20 @param Count Return the count of root bridge instances. @@ -750,13 +777,19 @@ PciHostBridgeGetRootBridges ( PciPhyIoAddr [Idx] =3D PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); Regs[Idx] =3D PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); =20 + // Check is the PCIe controller is enabled + if (IsPcieNumEnabled (Idx + 1) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Re= gs[Idx])); + continue; + } + // Check PCIe Link LinkUp =3D PcieLinkUp(Regs[Idx], Idx); =20 if (!LinkUp) { continue; } - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx += 1, Regs[Idx])); // Set up PCIe Controller and ATU windows PcieSetupCntrl (Regs[Idx], PciPhyCfg0Addr[Idx], --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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