From nobody Wed Feb 11 00:55:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51037+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51037+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332905; cv=none; d=zoho.com; s=zohoarc; b=QPDpk9yokjATM1vRR5KhFiQrptNoe6+LgRQqoUbRo6Qp/mTgvjciwXKZF1nkWUNRcLNypp1Kabs4IMS3SH+kCdtC/7/Jg1XOw2HsAhRPd3HJ7KQolW5PzgWouSlos07r/vUDN8cF+YShdY7dbP0i5mEPQYj1dyxBMzUBl45G44o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332905; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=pGuhx+MDkaUZNscUpVsOIJpLWnIzh+5D8vNKqMuGm38=; b=DB51SjnmhJzNx3EjROH/wiDzIl/Hl7hzLPvtBN8DZWZg1vummT7BG2e19RbqzRHBwIYJef2zheUZhzHhkmsb5J8lKMN5DXAjPFNQIgW3dFF49j7CvPeDuPVavXtTUnlVIZWPkeIi4hwE0h9Rschf+Xh2tktRCnDB3+5JNNsowtw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51037+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332905316183.1454461138335; Thu, 21 Nov 2019 02:41:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:44 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web11.22089.1574332903321447818 for ; Thu, 21 Nov 2019 02:41:43 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D78A41A08C1; Thu, 21 Nov 2019 11:41:41 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3E7C81A0124; Thu, 21 Nov 2019 11:41:41 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 8209D341; Thu, 21 Nov 2019 16:11:40 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Date: Thu, 21 Nov 2019 21:55:07 +0530 Message-Id: <1574353514-23986-5-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332904; bh=R4P0Y02JMlDr6PGrIQUGlkNJwzXc8+OQANbWHUYjKQU=; h=Cc:Date:From:Reply-To:Subject:To; b=MKGUb6QwFTCqA2FzurP+791sHQYvO1x3wV8y2yBG08VYvruhwhY3ILSus9OB+nmmarF /o3kQOAI+zEthjYQxwi9q1VNmOaTIk9IoUwro4h0mqxarsHf0RZOuwby0823SOTnjKrGd BGo218koZL3zhnSLganQvG1GJPfeLmlZKR0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 ++ Silicon/NXP/Library/DUartPortLib/DUart.h | 122 +++++++ Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 ++++++++++++++++++= ++ 3 files changed, 520 insertions(+) diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NX= P/Library/DUartPortLib/DUartPortLib.inf new file mode 100644 index 000000000000..7a2fa619b027 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf @@ -0,0 +1,34 @@ +# DUartPortLib.inf +# +# Component description file for DUartPortLib module +# +# Copyright (c) 2013, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D DUartPortLib + FILE_GUID =3D c42dfe79-8de5-429e-a055-2d0a58591498 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Sources.common] + DUartPortLib.c + +[LibraryClasses] + PcdLib + SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library= /DUartPortLib/DUart.h new file mode 100644 index 000000000000..c71e2ce55d1d --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUart.h @@ -0,0 +1,122 @@ +/** DUart.h +* Header defining the DUART constants (Base addresses, sizes, flags) +* +* Based on Serial I/O Port library headers available in PL011Uart.h +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef DUART_H_ +#define DUART_H_ + +// FIFO Control Register +#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range= */ +#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +// Modem Control Register +#define DUART_MCR_DTR 0x01 /* Reserved */ +#define DUART_MCR_RTS 0x02 /* RTS */ +#define DUART_MCR_OUT1 0x04 /* Reserved */ +#define DUART_MCR_OUT2 0x08 /* Reserved */ +#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */ +#define DUART_MCR_DMA_EN 0x04 +#define DUART_MCR_TX_DFR 0x08 + +// Line Control Register +/* +* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting +* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. +*/ +#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define DUART_LCR_STB 0x04 /* # stop Bits, off=3D1, on=3D1.5 = or 2) */ +#define DUART_LCR_PEN 0x08 /* Parity eneble */ +#define DUART_LCR_EPS 0x10 /* Even Parity Select */ +#define DUART_LCR_STKP 0x20 /* Stick Parity */ +#define DUART_LCR_SBRK 0x40 /* Set Break */ +#define DUART_LCR_BKSE 0x80 /* Bank select enable */ +#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +// Line Status Register +#define DUART_LSR_DR 0x01 /* Data ready */ +#define DUART_LSR_OE 0x02 /* Overrun */ +#define DUART_LSR_PE 0x04 /* Parity error */ +#define DUART_LSR_FE 0x08 /* Framing error */ +#define DUART_LSR_BI 0x10 /* Break */ +#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define DUART_LSR_TEMT 0x40 /* Xmitter empty */ +#define DUART_LSR_ERR 0x80 /* Error */ + +// Modem Status Register +#define DUART_MSR_DCTS 0x01 /* Delta CTS */ +#define DUART_MSR_DDSR 0x02 /* Reserved */ +#define DUART_MSR_TERI 0x04 /* Reserved */ +#define DUART_MSR_DDCD 0x08 /* Reserved */ +#define DUART_MSR_CTS 0x10 /* Clear to Send */ +#define DUART_MSR_DSR 0x20 /* Reserved */ +#define DUART_MSR_RI 0x40 /* Reserved */ +#define DUART_MSR_DCD 0x80 /* Reserved */ + +// Interrupt Identification Register +#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define DUART_IIR_MSI 0x00 /* Modem status interrupt */ +#define DUART_IIR_THRI 0x02 /* Transmitter holding register em= pty */ +#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt = */ + +// Interrupt Enable Register +#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define DUART_IER_RLSI 0x04 /* Enable receiver line status int= errupt */ +#define DUART_IER_THRI 0x02 /* Enable Transmitter holding regi= ster int. */ +#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt = */ + +// LCR defaults +#define DUART_LCR_8N1 0x03 +#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 sto= p, no parity */ +#define DUART_MCRVAL (DUART_MCR_DTR | \ + DUART_MCR_RTS) /* RTS/DTR */ +#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \ + DUART_FCR_RXSR | \ + DUART_FCR_TXSR) /* Clear & enabl= e FIFOs */ + +#define URBR 0x0 +#define UTHR 0x0 +#define UDLB 0x0 +#define UDMB 0x1 +#define UIER 0x1 +#define UIIR 0x2 +#define UFCR 0x2 +#define UAFR 0x2 +#define ULCR 0x3 +#define UMCR 0x4 +#define ULSR 0x5 +#define UMSR 0x6 +#define USCR 0x7 +#define UDSR 0x10 + +extern +UINT64 +GetBusFrequency ( + VOID + ); + +#endif /* DUART_H_ */ diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/= Library/DUartPortLib/DUartPortLib.c new file mode 100644 index 000000000000..c3c738d3cca8 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c @@ -0,0 +1,364 @@ +/** DuartPortLib.c + DUART (NS16550) library functions + + Based on Serial I/O Port library functions available in PL011SerialPortL= ib.c + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#include "DUart.h" + +STATIC CONST UINT32 mInvalidControlBits =3D (EFI_SERIAL_SOFTWARE_LOOPBACK_= ENABLE | \ + EFI_SERIAL_DATA_TERMINAL_READY); + +/** + Assert or deassert the control signals on a serial port. + The following control signals are set according their bit settings : + . Request to Send + . Data Terminal Ready + + @param[in] Control The following bits are taken into account : + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert t= he + "Request To Send" control signal if this bit is + equal to one/zero. + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deasse= rt + the "Data Terminal Ready" control signal if th= is + bit is equal to one/zero. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/d= isable + the hardware loopback if this bit is equal to + one/zero. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supp= orted. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enab= le/ + disable the hardware flow control based on CTS= (Clear + To Send) and RTS (Ready To Send) control signa= ls. + + @retval EFI_SUCCESS The new control bits were set on the device. + @retval EFI_UNSUPPORTED The device does not support this operation. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINT32 McrBits; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + if (Control & (mInvalidControlBits)) { + return EFI_UNSUPPORTED; + } + + McrBits =3D MmioRead8 (UartBase + UMCR); + + if (Control & EFI_SERIAL_REQUEST_TO_SEND) { + McrBits |=3D DUART_MCR_RTS; + } else { + McrBits &=3D ~DUART_MCR_RTS; + } + + if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) { + McrBits |=3D DUART_MCR_LOOP; + } else { + McrBits &=3D ~DUART_MCR_LOOP; + } + + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) { + McrBits |=3D DUART_MCR_AFE; + } else { + McrBits &=3D ~DUART_MCR_AFE; + } + + MmioWrite32 (UartBase + UMCR, McrBits); + + return EFI_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param[out] Control Status of the control bits on a serial device : + + . EFI_SERIAL_DATA_CLEAR_TO_SEND, + EFI_SERIAL_DATA_SET_READY, + EFI_SERIAL_RING_INDICATE, + EFI_SERIAL_CARRIER_DETECT, + EFI_SERIAL_REQUEST_TO_SEND, + EFI_SERIAL_DATA_TERMINAL_READY + are all related to the DTE (Data Terminal Equip= ment) + and DCE (Data Communication Equipment) modes of + operation of the serial device. + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if= the + receive buffer is empty, 0 otherwise. + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one i= f the + transmit buffer is empty, 0 otherwise. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to = one if + the hardware loopback is enabled (the ouput fee= ds the + receive buffer), 0 otherwise. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to = one if + a loopback is accomplished by software, 0 other= wise. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal= to + one if the hardware flow control based on CTS (= Clear + To Send) and RTS (Ready To Send) control signal= s is + enabled, 0 otherwise. + + @retval EFI_SUCCESS The control bits were read from the serial devi= ce. + +**/ +EFI_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINT32 MsrRegister; + UINT32 McrRegister; + UINT32 LsrRegister; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + MsrRegister =3D MmioRead8 (UartBase + UMSR); + McrRegister =3D MmioRead8 (UartBase + UMCR); + LsrRegister =3D MmioRead8 (UartBase + ULSR); + + *Control =3D 0; + + if ((MsrRegister & DUART_MSR_CTS) =3D=3D DUART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((McrRegister & DUART_MCR_RTS) =3D=3D DUART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if ((LsrRegister & DUART_LSR_TEMT) =3D=3D DUART_LSR_TEMT) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((McrRegister & DUART_MCR_AFE) =3D=3D DUART_MCR_AFE) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + if ((McrRegister & DUART_MCR_LOOP) =3D=3D DUART_MCR_LOOP) { + *Control |=3D EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE; + } + + return EFI_SUCCESS; +} + +/* + * Return Baud divisor on basis of Baudrate + */ +UINT32 +CalculateBaudDivisor ( + IN UINT64 BaudRate + ) +{ + UINTN DUartClk; + UINTN FreqSystemBus; + + FreqSystemBus =3D GetBusFrequency (); + DUartClk =3D FreqSystemBus/PcdGet32(PcdPlatformFreqDiv); + + return ((DUartClk)/(BaudRate * 16)); +} + +/* + Initialise the serial port to the specified settings. + All unspecified settings will be set to the default values. + + @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER. + + **/ +VOID +EFIAPI +DuartInitializePort ( + IN UINT64 BaudRate + ) +{ + UINTN UartBase; + UINT32 BaudDivisor; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + BaudDivisor =3D CalculateBaudDivisor (BaudRate); + + + while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT)); + + // + // Enable and assert interrupt when new data is available on + // external device, + // setup data format, setup baud divisor + // + MmioWrite8 (UartBase + UIER, 0x1); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, 0); + MmioWrite8 (UartBase + UDMB, 0); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + MmioWrite8 (UartBase + UMCR, DUART_MCRVAL); + MmioWrite8 (UartBase + UFCR, DUART_FCRVAL); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff); + MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + + return; +} + +/** + Programmed hardware of Serial port. + + @return Always return EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINT64 BaudRate; + BaudRate =3D (UINTN)PcdGet64 (PcdUartDefaultBaudRate); + + + DuartInitializePort (BaudRate); + + return EFI_SUCCESS; +} + +/** + Write data to serial device. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes written to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINT8 *Final; + UINTN UartBase; + + Final =3D &Buffer[NumberOfBytes]; + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + while (Buffer < Final) { + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) =3D=3D 0); + MmioWrite8 (UartBase + UTHR, *Buffer++); + } + + return NumberOfBytes; +} + +/** + Read data from serial device and save the data in buffer. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed. + @retval !0 Actual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN Count; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + for (Count =3D 0; Count < NumberOfBytes; Count++, Buffer++) { + // Loop while waiting for a new char(s) to arrive in the + // RxFIFO + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) =3D=3D 0); + + *Buffer =3D MmioRead8 (UartBase + URBR); + } + + return NumberOfBytes; +} + +/** + Check to see if any data is available to be read from the debug device. + + @retval EFI_SUCCESS At least one byte of data is available to be r= ead + @retval EFI_NOT_READY No data is available to be read + @retval EFI_DEVICE_ERROR The serial device is not functioning properly + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) !=3D 0); +} + +/** + Set new attributes to LS1043a. + + @param BaudRate The baud rate of the serial device. If t= he baud rate is not supported, + the speed will be reduced down to the ne= arest supported one and the + variable's value will be updated accordi= ngly. + @param ReceiveFifoDepth The number of characters the device will= buffer on input. If the specified + value is not supported, the variable's v= alue will be reduced down to the + nearest supported one. + @param Timeout If applicable, the number of microsecond= s the device will wait + before timing out a Read or a Write oper= ation. + @param Parity If applicable, this is the EFI_PARITY_TY= PE that is computed or checked + as each character is transmitted or rece= ived. If the device does not + support parity, the value is the default= parity value. + @param DataBits The number of data bits in each character + @param StopBits If applicable, the EFI_STOP_BITS_TYPE nu= mber of stop bits per character. + If the device does not support stop bits= , the value is the default stop + bit value. + + @retval EFI_SUCCESS All attributes were set correctly on the= serial device. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + DuartInitializePort (*BaudRate); + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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