From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51035+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51035+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332903; cv=none; d=zoho.com; s=zohoarc; b=hyi/hU/KNZ3JtxTuangwnLw7pcdus8MsQbnmWEw3YPavbVHein0izCaE+DA01CNuN3l8shxGNJpeNeCZbAOLC7uPRj4LgTIN/RID1faE2GzcG00Nz7C2AE1RfslzkjzcsaSaE/k2JaawtRNJPkIV5/eIf5qnVYJcPzUdvz5RV6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332903; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=vuMR7mpNtBFBqUjN5QB0Yt1skPaDzW5uiYeOh6BOT/s=; b=ZY3tUg4X5dCY6lGdoWg2cmvzKHWCzoKc9d1Y2Nrvy6o+XMpquMUE27kEUMiqFG+tOxIMlcI2XSaq0QZFEqa7swL/kve2x/9xRqTDFvetfhsaIkWFqSG14L+hHaVV7tO8aMnhqQsE0ervPmYYvjzlOKQYWPWZKTj1cFLpc14AGh0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51035+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332903139112.60064165541428; Thu, 21 Nov 2019 02:41:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:42 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web12.22054.1574332901521801784 for ; Thu, 21 Nov 2019 02:41:42 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1D9FD1A07D7; Thu, 21 Nov 2019 11:41:40 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9B2EE1A0009; Thu, 21 Nov 2019 11:41:39 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 9111C341; Thu, 21 Nov 2019 16:11:38 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data. Date: Thu, 21 Nov 2019 21:55:04 +0530 Message-Id: <1574353514-23986-2-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332902; bh=s19pxcDGYB4isg1tKdV87wvCkzihZg0nnP2AX3R2hSg=; h=Cc:Date:From:Reply-To:Subject:To; b=F3O0ypWn8h8/7RmXPZO6WN+Qo9+opuN/PExWJ/bJKWwQHaDPK5rXmTTDGszu0ZnK5YO NkHUcDmK59vXW9aCGWj7u/LKByo1AeleXzWi31UigQWDe6WU2+zzTg4UH0k+QqFBwyDNt sK+jVtq4guPDd3cLdxugVPLDAwCIR0yzFz4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This library provided MMIO APIs for modules need swapping. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 ++ Silicon/NXP/Include/Library/IoAccessLib.h | 248 ++++++++++++++++ Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 302 ++++++++++++++++++++ 3 files changed, 576 insertions(+) diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf b/Silicon/NXP/= Library/IoAccessLib/IoAccessLib.inf new file mode 100644 index 000000000000..4f3af4647e95 --- /dev/null +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf @@ -0,0 +1,26 @@ +## @IoAccessLib.inf + +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D IoAccessLib + FILE_GUID =3D 28d77333-77eb-4faf-8735-130e5eb3e343 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IoAccessLib + +[Sources.common] + IoAccessLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + IoLib diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Includ= e/Library/IoAccessLib.h new file mode 100644 index 000000000000..b72e65c83091 --- /dev/null +++ b/Silicon/NXP/Include/Library/IoAccessLib.h @@ -0,0 +1,248 @@ +/** @file + * + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef IO_ACCESS_LIB_H_ +#define IO_ACCESS_LIB_H_ + +#include + +/** + MmioRead16 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +SwapMmioRead16 ( + IN UINTN Address + ); + +/** + MmioRead32 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +SwapMmioRead32 ( + IN UINTN Address + ); + +/** + MmioRead64 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +SwapMmioRead64 ( + IN UINTN Address + ); + +/** + MmioWrite16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + MmioWrite32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + MmioWrite64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + MmioAndThenOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + MmioAndThenOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + MmioAndThenOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + MmioOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + MmioOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + MmioOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ); + +/** + MmioAnd16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + MmioAnd32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + MmioAnd64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ); + +#endif /* IO_ACCESS_LIB_H_ */ diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Li= brary/IoAccessLib/IoAccessLib.c new file mode 100644 index 000000000000..e9e535fc2f85 --- /dev/null +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c @@ -0,0 +1,302 @@ +/** IoAccessLib.c + + Provide MMIO APIs for BE modules. + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + MmioRead16 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +SwapMmioRead16 ( + IN UINTN Address + ) +{ + return SwapBytes16 (MmioRead16 (Address)); +} + +/** + MmioRead32 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +SwapMmioRead32 ( + IN UINTN Address + ) +{ + return SwapBytes32 (MmioRead32 (Address)); +} + +/** + MmioRead64 for Big-Endian modules. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +SwapMmioRead64 ( + IN UINTN Address + ) +{ + return SwapBytes64 (MmioRead64 (Address)); +} + +/** + MmioWrite16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + return MmioWrite16 (Address, SwapBytes16 (Value)); +} + +/** + MmioWrite32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + return MmioWrite32 (Address, SwapBytes32 (Value)); +} + +/** + MmioWrite64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + return MmioWrite64 (Address, SwapBytes64 (Value)); +} + +/** + MmioAndThenOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + AndData =3D SwapBytes16 (AndData); + OrData =3D SwapBytes16 (OrData); + + return MmioAndThenOr16 (Address, AndData, OrData); +} + +/** + MmioAndThenOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + AndData =3D SwapBytes32 (AndData); + OrData =3D SwapBytes32 (OrData); + + return MmioAndThenOr32 (Address, AndData, OrData); +} + +/** + MmioAndThenOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ) +{ + AndData =3D SwapBytes64 (AndData); + OrData =3D SwapBytes64 (OrData); + + return MmioAndThenOr64 (Address, AndData, OrData); +} + +/** + MmioOr16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + return MmioOr16 (Address, SwapBytes16 (OrData)); +} + +/** + MmioOr32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + return MmioOr32 (Address, SwapBytes32 (OrData)); +} + +/** + MmioOr64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO regist= er. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ) +{ + return MmioOr64 (Address, SwapBytes64 (OrData)); +} + +/** + MmioAnd16 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +SwapMmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + return MmioAnd16 (Address, SwapBytes16 (AndData)); +} + +/** + MmioAnd32 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +SwapMmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + return MmioAnd32 (Address, SwapBytes32 (AndData)); +} + +/** + MmioAnd64 for Big-Endian modules. + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO regis= ter. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +SwapMmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ) +{ + return MmioAnd64 (Address, SwapBytes64 (AndData)); +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51035): https://edk2.groups.io/g/devel/message/51035 Mute This Topic: https://groups.io/mt/61076173/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51036+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51036+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332903; cv=none; d=zoho.com; s=zohoarc; b=ZiHjsa6WMa2xqbEgGEB0Csjm0Uxe8h9ApALfvkNKGD8JNogMm5GTQVvEkuwQ4HBPIzmRCLJXMVMboHm2UKhT59YNKNqgLSosamuox2wSOEc79n77xEHCMFRT+qhTAZdpIM85hQgYXAdoEHQfAry08M7zZ5lUFDBo+sUl7V7BMaU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332903; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=cj2KNtzlUIJjRGs1RwPW3vDItl9F8qVvrJOaJRqP38U=; b=MpzVgo04hG5zT9xReepmoTc9/9yjyNqObd199hP5fQKrEewaDL6fle4FDe2QsHgeHlaSv1PeOay7VKQHSZ0zhpR+CXHKgJTEvdxW7a/qtCi28JrlhkZVEUPGC1Bx/IV1d1U0ksZfWPOlUSgirPeJxBtusmIiqRCCNaXVcXoaD9M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51036+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332903509523.3701067260577; Thu, 21 Nov 2019 02:41:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:43 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web09.22248.1574332902254223416 for ; Thu, 21 Nov 2019 02:41:42 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 937401A05EE; Thu, 21 Nov 2019 11:41:40 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 404191A0009; Thu, 21 Nov 2019 11:41:40 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 40706364; Thu, 21 Nov 2019 16:11:39 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer Date: Thu, 21 Nov 2019 21:55:05 +0530 Message-Id: <1574353514-23986-3-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332903; bh=sZVNszP4NaUWsTRnJGWZArgqd8eAA990+pSKw+7mP1Y=; h=Cc:Date:From:Reply-To:Subject:To; b=xW4Zpw4EOwk3LYyXLXT9Z4ilSoknU/lEfJEbjNF0LF7y/Wvdr9mz/HXaJj4sO1f+S6h jcr5teAyk0p1fzu8r9nb46W48YqxhkrdZP3s/03OCIk2Ppbl4kQQJAU+ZTijwWo1ZGxoo VPhxrmlJw2qa7VKJtnRNMftJuND3op4GBt0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support to return pointer to MMIO APIs on basis of Swap flag. If Flag is True then MMIO APIs returned in which data swapped after reading from MMIO and before write using MMIO. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/Include/Library/IoAccessLib.h | 78 +++++++++++++++ Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 102 ++++++++++++++++++++ 2 files changed, 180 insertions(+) diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Includ= e/Library/IoAccessLib.h index b72e65c83091..0b708d544fa7 100644 --- a/Silicon/NXP/Include/Library/IoAccessLib.h +++ b/Silicon/NXP/Include/Library/IoAccessLib.h @@ -11,6 +11,84 @@ =20 #include =20 +/// +/// Structure to have pointer to R/W +/// Mmio operations for 16 bits. +/// +typedef struct _MMIO_OPERATIONS_16 { + UINT16 (*Read16) (UINTN Address); + UINT16 (*Write16) (UINTN Address, UINT16 Value); + UINT16 (*Or16) (UINTN Address, UINT16 OrData); + UINT16 (*And16) (UINTN Address, UINT16 AndData); + UINT16 (*AndThenOr16) (UINTN Address, UINT16 AndData, UINT16 OrData); +} MMIO_OPERATIONS_16; + +/// +/// Structure to have pointer to R/W +/// Mmio operations for 32 bits. +/// +typedef struct _MMIO_OPERATIONS_32 { + UINT32 (*Read32) (UINTN Address); + UINT32 (*Write32) (UINTN Address, UINT32 Value); + UINT32 (*Or32) (UINTN Address, UINT32 OrData); + UINT32 (*And32) (UINTN Address, UINT32 AndData); + UINT32 (*AndThenOr32) (UINTN Address, UINT32 AndData, UINT32 OrData); +} MMIO_OPERATIONS_32; + +/// +/// Structure to have pointer to R/W +/// Mmio operations for 64 bits. +/// +typedef struct _MMIO_OPERATIONS_64 { + UINT64 (*Read64) (UINTN Address); + UINT64 (*Write64) (UINTN Address, UINT64 Value); + UINT64 (*Or64) (UINTN Address, UINT64 OrData); + UINT64 (*And64) (UINTN Address, UINT64 AndData); + UINT64 (*AndThenOr64) (UINTN Address, UINT64 AndData, UINT64 OrData); +} MMIO_OPERATIONS_64; + +/** + Function to return pointer to 16 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_16 * +GetMmioOperations16 ( + IN BOOLEAN Swap + ); + +/** + Function to return pointer to 32 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_32 * +GetMmioOperations32 ( + IN BOOLEAN Swap + ); + +/** + Function to return pointer to 64 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_64 * +GetMmioOperations64 ( + IN BOOLEAN Swap + ); + /** MmioRead16 for Big-Endian modules. =20 diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Li= brary/IoAccessLib/IoAccessLib.c index e9e535fc2f85..6ed83d019a6e 100644 --- a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c @@ -300,3 +300,105 @@ SwapMmioAnd64 ( { return MmioAnd64 (Address, SwapBytes64 (AndData)); } + +STATIC MMIO_OPERATIONS_16 SwappingFunctions16 =3D { + SwapMmioRead16, + SwapMmioWrite16, + SwapMmioOr16, + SwapMmioAnd16, + SwapMmioAndThenOr16, +}; + +STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 =3D { + MmioRead16, + MmioWrite16, + MmioOr16, + MmioAnd16, + MmioAndThenOr16, +}; + +STATIC MMIO_OPERATIONS_32 SwappingFunctions32 =3D { + SwapMmioRead32, + SwapMmioWrite32, + SwapMmioOr32, + SwapMmioAnd32, + SwapMmioAndThenOr32, +}; + +STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 =3D { + MmioRead32, + MmioWrite32, + MmioOr32, + MmioAnd32, + MmioAndThenOr32, +}; + +STATIC MMIO_OPERATIONS_64 SwappingFunctions64 =3D { + SwapMmioRead64, + SwapMmioWrite64, + SwapMmioOr64, + SwapMmioAnd64, + SwapMmioAndThenOr64, +}; + +STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 =3D { + MmioRead64, + MmioWrite64, + MmioOr64, + MmioAnd64, + MmioAndThenOr64, +}; + +/** + Function to return pointer to 16 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_16 * +GetMmioOperations16 (BOOLEAN Swap) { + if (Swap) { + return &SwappingFunctions16; + } else { + return &NonSwappingFunctions16; + } +} + +/** + Function to return pointer to 32 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_32 * +GetMmioOperations32 (BOOLEAN Swap) { + if (Swap) { + return &SwappingFunctions32; + } else { + return &NonSwappingFunctions32; + } +} + +/** + Function to return pointer to 64 bit Mmio operations. + + @param Swap Flag to tell if Swap is needed or not + on Mmio Operations. + + @return Pointer to Mmio Operations. + +**/ +MMIO_OPERATIONS_64 * +GetMmioOperations64 (BOOLEAN Swap) { + if (Swap) { + return &SwappingFunctions64; + } else { + return &NonSwappingFunctions64; + } +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51036): https://edk2.groups.io/g/devel/message/51036 Mute This Topic: https://groups.io/mt/61076174/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51038+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51038+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332905; cv=none; d=zoho.com; s=zohoarc; b=MR9WCs5OMsHr4Cm/hyQrHm8nD4SixIzE92gXj65pGmcyiV2j6Jh2+WZ2nWuWq6JCFmWAVfxQK58N8+GFb4BUrFsEr8X/P+VAlBQhZV9K392FDEs8ZqKSp2tnOA0hOlHN0eSpUi9l4aoeCkkKk20ee+ybi7Wznd0Q+8xmtgglrtc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332905; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=N+HXFdNoWg54wVj7vbhVGtUnA6WzT3NBhbYhP39UPjg=; b=H4BtFy74+Ck3d0VIv1wglIyWoMnIECNTTWsd1/VMYiCZwF8m+Rk8XCWUgL9XAthVA1hlDn8aOTduhnD3o5lws2pbsDbnW4pJaOxJs0kpsyS724f0fjZPbEJq5S/pIyTO6r66nyMc47OWSmlVIgN0/8M9DnE1FU3v+mz/CTu8y5U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51038+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332905268565.8602201039718; Thu, 21 Nov 2019 02:41:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:44 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web10.22186.1574332903389786964 for ; Thu, 21 Nov 2019 02:41:44 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E2F0C1A061F; Thu, 21 Nov 2019 11:41:41 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id DCC0A1A0009; Thu, 21 Nov 2019 11:41:40 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id D9328316; Thu, 21 Nov 2019 16:11:39 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Date: Thu, 21 Nov 2019 21:55:06 +0530 Message-Id: <1574353514-23986-4-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332904; bh=46bCK3loo79fYqP+oKn9W22a9JqR98C9hYkURu1uuiQ=; h=Cc:Date:From:Reply-To:Subject:To; b=DNp1uFyzJbafnZVqEh4pduDnAAuBcfiKHHWrGWjmGnTvyzYNEWJeZfno0eJDu6mv7J5 F3Oyk4ww4cjTQLnXL49Y3Lym91BUIyGfUKUVA+rW4EPp/Clwiz1SzTweAnSYsmSMRwX8P RGa/I0HAYqx79AwNWki0HxQD8smIwjZpzqA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add SocInit function that initializes peripherals and print board and soc information. Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++ Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 +++ Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++++++ Silicon/NXP/Include/DramInfo.h | 38 ++ Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++ Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++++ Silicon/NXP/Library/SocLib/Chassis.c | 498 ++++++++++++++++++++ Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++++ Silicon/NXP/Library/SocLib/SerDes.c | 268 +++++++++++ 9 files changed, 1621 insertions(+) diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf new file mode 100644 index 000000000000..cb670a12797e --- /dev/null +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -0,0 +1,45 @@ +# @file +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D e868c5ca-9729-43ae-bff4-438c67de8c68 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/LS1043A/LS1043A.dec + +[LibraryClasses] + ArmSmcLib + BaseLib + DebugLib + IoAccessLib + SerialPortLib + +[Sources.common] + Chassis.c + Chassis2/Soc.c + SerDes.c + +[BuildOptions] + GCC:*_*_*_CC_FLAGS =3D -DCHASSIS2 + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/= Chassis2/LsSerDes.h new file mode 100644 index 000000000000..9afbc522398a --- /dev/null +++ b/Silicon/NXP/Include/Chassis2/LsSerDes.h @@ -0,0 +1,62 @@ +/** LsSerDes.h + The Header file of SerDes Module for Chassis 2 + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef LS_SERDES_H_ +#define LS_SERDES_H_ + +#include + +#define SRDS_MAX_LANES 4 + +typedef enum { + None =3D 0, + Pcie1, + Pcie2, + Pcie3, + Sata, + SgmiiFm1Dtsec1, + SgmiiFm1Dtsec2, + SgmiiFm1Dtsec5, + SgmiiFm1Dtsec6, + SgmiiFm1Dtsec9, + SgmiiFm1Dtsec10, + QsgmiiFm1A, + XfiFm1Mac9, + XfiFm1Mac10, + Sgmii2500Fm1Dtsec2, + Sgmii2500Fm1Dtsec5, + Sgmii2500Fm1Dtsec9, + Sgmii2500Fm1Dtsec10, + SerdesPrtclCount +} SERDES_PROTOCOL; + +typedef enum { + Srds1 =3D 0, + Srds2, + SrdsMaxNum +} SERDES_NUMBER; + +typedef struct { + UINT16 Protocol; + UINT8 SrdsLane[SRDS_MAX_LANES]; +} SERDES_CONFIG; + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN SERDES_PROTOCOL LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); + +#endif /* LS_SERDES_H_ */ diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h new file mode 100644 index 000000000000..f05a813750e8 --- /dev/null +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h @@ -0,0 +1,361 @@ +/** Soc.h +* Header defining the Base addresses, sizes, flags etc for chassis 1 +* +* Copyright 2017-2019 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef NXP_SOC_H_ +#define NXP_SOC_H_ + +#define HWA_CGA_M1_CLK_SEL 0xe0000000 +#define HWA_CGA_M1_CLK_SHIFT 29 + +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */ +#define NUM_CC_PLLS 2 +#define CLK_FREQ 100000000 +#define MAX_CPUS 4 +#define NUM_FMAN 1 +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) =3D=3D = 0x0) + +/* RCW SERDES MACRO */ +#define RCWSR_INDEX 4 +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000 +#define RCWSR_SRDS1_PRTCL_SHIFT 16 +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff +#define RCWSR_SRDS2_PRTCL_SHIFT 0 + +/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) + +#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 +#define IDR1_PAGESIZE_MASK 0x80000000 + +typedef struct { + UINTN FreqProcessor[MAX_CPUS]; + UINTN FreqSystemBus; + UINTN FreqDdrBus; + UINTN FreqLocalBus; + UINTN FreqSdhc; + UINTN FreqFman[NUM_FMAN]; + UINTN FreqQman; +} SYS_INFO; + +/* Device Configuration and Pin Control */ +typedef struct { + UINT32 PorSr1; /* POR status 1 */ +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 + UINT32 PorSr2; /* POR status 2 */ + UINT8 Res008[0x20-0x8]; + UINT32 GppOrCr1; /* General-purpose POR configuration */ + UINT32 GppOrCr2; + UINT32 DcfgFuseSr; /* Fuse status register */ + UINT8 Res02c[0x70-0x2c]; + UINT32 DevDisr; /* Device disable control */ + UINT32 DevDisr2; /* Device disable control 2 */ + UINT32 DevDisr3; /* Device disable control 3 */ + UINT32 DevDisr4; /* Device disable control 4 */ + UINT32 DevDisr5; /* Device disable control 5 */ + UINT32 DevDisr6; /* Device disable control 6 */ + UINT32 DevDisr7; /* Device disable control 7 */ + UINT8 Res08c[0x94-0x8c]; + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */ + UINT32 CoreDisrL; /* lower portion for support of 64 cores */ + UINT8 Res09c[0xa0-0x9c]; + UINT32 Pvr; /* Processor version */ + UINT32 Svr; /* System version */ + UINT32 Mvr; /* Manufacturing version */ + UINT8 Res0ac[0xb0-0xac]; + UINT32 RstCr; /* Reset control */ + UINT32 RstRqPblSr; /* Reset request preboot loader status */ + UINT8 Res0b8[0xc0-0xb8]; + UINT32 RstRqMr1; /* Reset request mask */ + UINT8 Res0c4[0xc8-0xc4]; + UINT32 RstRqSr1; /* Reset request status */ + UINT8 Res0cc[0xd4-0xcc]; + UINT32 RstRqWdTmrL; /* Reset request WDT mask */ + UINT8 Res0d8[0xdc-0xd8]; + UINT32 RstRqWdtSrL; /* Reset request WDT status */ + UINT8 Res0e0[0xe4-0xe0]; + UINT32 BrrL; /* Boot release */ + UINT8 Res0e8[0x100-0xe8]; + UINT32 RcwSr[16]; /* Reset control word status */ +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f + UINT8 Res140[0x200-0x140]; + UINT32 ScratchRw[4]; /* Scratch Read/Write */ + UINT8 Res210[0x300-0x210]; + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */ + UINT8 Res310[0x400-0x310]; + UINT32 CrstSr[12]; + UINT8 Res430[0x500-0x430]; + /* PCI Express n Logical I/O Device Number register */ + UINT32 DcfgCcsrPex1LiodNr; + UINT32 DcfgCcsrPex2LiodNr; + UINT32 DcfgCcsrPex3LiodNr; + UINT32 DcfgCcsrPex4LiodNr; + /* RIO n Logical I/O Device Number register */ + UINT32 DcfgCcsrRio1LiodNr; + UINT32 DcfgCcsrRio2LiodNr; + UINT32 DcfgCcsrRio3LiodNr; + UINT32 DcfgCcsrRio4LiodNr; + /* USB Logical I/O Device Number register */ + UINT32 DcfgCcsrUsb1LiodNr; + UINT32 DcfgCcsrUsb2LiodNr; + UINT32 DcfgCcsrUsb3LiodNr; + UINT32 DcfgCcsrUsb4LiodNr; + /* SD/MMC Logical I/O Device Number register */ + UINT32 DcfgCcsrSdMmc1LiodNr; + UINT32 DcfgCcsrSdMmc2LiodNr; + UINT32 DcfgCcsrSdMmc3LiodNr; + UINT32 DcfgCcsrSdMmc4LiodNr; + /* RIO Message Unit Logical I/O Device Number register */ + UINT32 DcfgCcsrRiomaintLiodNr; + UINT8 Res544[0x550-0x544]; + UINT32 SataLiodNr[4]; + UINT8 Res560[0x570-0x560]; + UINT32 DcfgCcsrMisc1LiodNr; + UINT32 DcfgCcsrMisc2LiodNr; + UINT32 DcfgCcsrMisc3LiodNr; + UINT32 DcfgCcsrMisc4LiodNr; + UINT32 DcfgCcsrDma1LiodNr; + UINT32 DcfgCcsrDma2LiodNr; + UINT32 DcfgCcsrDma3LiodNr; + UINT32 DcfgCcsrDma4LiodNr; + UINT32 DcfgCcsrSpare1LiodNr; + UINT32 DcfgCcsrSpare2LiodNr; + UINT32 DcfgCcsrSpare3LiodNr; + UINT32 DcfgCcsrSpare4LiodNr; + UINT8 Res5a0[0x600-0x5a0]; + UINT32 DcfgCcsrPblSr; + UINT32 PamuBypENr; + UINT32 DmaCr1; + UINT8 Res60c[0x610-0x60c]; + UINT32 DcfgCcsrGenSr1; + UINT32 DcfgCcsrGenSr2; + UINT32 DcfgCcsrGenSr3; + UINT32 DcfgCcsrGenSr4; + UINT32 DcfgCcsrGenCr1; + UINT32 DcfgCcsrGenCr2; + UINT32 DcfgCcsrGenCr3; + UINT32 DcfgCcsrGenCr4; + UINT32 DcfgCcsrGenCr5; + UINT32 DcfgCcsrGenCr6; + UINT32 DcfgCcsrGenCr7; + UINT8 Res63c[0x658-0x63c]; + UINT32 DcfgCcsrcGenSr1; + UINT32 DcfgCcsrcGenSr0; + UINT8 Res660[0x678-0x660]; + UINT32 DcfgCcsrcGenCr1; + UINT32 DcfgCcsrcGenCr0; + UINT8 Res680[0x700-0x680]; + UINT32 DcfgCcsrSrIoPstecr; + UINT32 DcfgCcsrDcsrCr; + UINT8 Res708[0x740-0x708]; /* add more registers when needed */ + UINT32 TpItyp[64]; /* Topology Initiator Type Register */ + struct { + UINT32 Upper; + UINT32 Lower; + } TpCluster[16]; + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */ + UINT32 DcfgCcsrQmBmWarmRst; + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */ + UINT32 DcfgCcsrReserved0; + UINT32 DcfgCcsrReserved1; +} CCSR_GUR; + +/* Supplemental Configuration Unit */ +typedef struct { + UINT8 Res000[0x070-0x000]; + UINT32 Usb1Prm1Cr; + UINT32 Usb1Prm2Cr; + UINT32 Usb1Prm3Cr; + UINT32 Usb2Prm1Cr; + UINT32 Usb2Prm2Cr; + UINT32 Usb2Prm3Cr; + UINT32 Usb3Prm1Cr; + UINT32 Usb3Prm2Cr; + UINT32 Usb3Prm3Cr; + UINT8 Res094[0x100-0x094]; + UINT32 Usb2Icid; + UINT32 Usb3Icid; + UINT8 Res108[0x114-0x108]; + UINT32 DmaIcid; + UINT32 SataIcid; + UINT32 Usb1Icid; + UINT32 QeIcid; + UINT32 SdhcIcid; + UINT32 EdmaIcid; + UINT32 EtrIcid; + UINT32 Core0SftRst; + UINT32 Core1SftRst; + UINT32 Core2SftRst; + UINT32 Core3SftRst; + UINT8 Res140[0x158-0x140]; + UINT32 AltCBar; + UINT32 QspiCfg; + UINT8 Res160[0x180-0x160]; + UINT32 DmaMcr; + UINT8 Res184[0x188-0x184]; + UINT32 GicAlign; + UINT32 DebugIcid; + UINT8 Res190[0x1a4-0x190]; + UINT32 SnpCnfGcr; +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31 +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30 +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23 +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22 +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21 +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20 +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15 +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16 +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13 +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14 + UINT8 Res1a8[0x1ac-0x1a8]; + UINT32 IntpCr; + UINT8 Res1b0[0x204-0x1b0]; + UINT32 CoreSrEnCr; + UINT8 Res208[0x220-0x208]; + UINT32 RvBar00; + UINT32 RvBar01; + UINT32 RvBar10; + UINT32 RvBar11; + UINT32 RvBar20; + UINT32 RvBar21; + UINT32 RvBar30; + UINT32 RvBar31; + UINT32 LpmCsr; + UINT8 Res244[0x400-0x244]; + UINT32 QspIdQScr; + UINT32 EcgTxcMcr; + UINT32 SdhcIoVSelCr; + UINT32 RcwPMuxCr0; + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/ +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333 + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/ +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 + UINT32 UsbDrvVBusSelCr; +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 + UINT32 UsbPwrFaultSelCr; +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001 +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0 + UINT32 UsbRefclkSelcr1; + UINT32 UsbRefclkSelcr2; + UINT32 UsbRefclkSelcr3; + UINT8 Res424[0x600-0x424]; + UINT32 ScratchRw[4]; + UINT8 Res610[0x680-0x610]; + UINT32 CoreBCr; + UINT8 Res684[0x1000-0x684]; + UINT32 Pex1MsiIr; + UINT32 Pex1MsiR; + UINT8 Res1008[0x2000-0x1008]; + UINT32 Pex2; + UINT32 Pex2MsiR; + UINT8 Res2008[0x3000-0x2008]; + UINT32 Pex3MsiIr; + UINT32 Pex3MsiR; +} CCSR_SCFG; + +#define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8003 +#define USB_PHY_RX_EQ_VAL_4 0x800b + +/*USB_PHY_SS memory map*/ +typedef struct { + UINT16 IpIdcodeLo; + UINT16 SupIdcodeHi; + UINT8 Res4[0x0006-0x0004]; + UINT16 RtuneDebug; + UINT16 RtuneStat; + UINT16 SupSsPhase; + UINT16 SsFreq; + UINT8 ResE[0x0020-0x000e]; + UINT16 Ateovrd; + UINT16 MpllOvrdInLo; + UINT8 Res24[0x0026-0x0024]; + UINT16 SscOvrdIn; + UINT8 Res28[0x002A-0x0028]; + UINT16 LevelOvrdIn; + UINT8 Res2C[0x0044-0x002C]; + UINT16 ScopeCount; + UINT8 Res46[0x0060-0x0046]; + UINT16 MpllLoopCtl; + UINT8 Res62[0x006C-0x0062]; + UINT16 SscClkCntrl; + UINT8 Res6E[0x2002-0x006E]; + UINT16 Lane0TxOvrdInHi; + UINT16 Lane0TxOvrdDrvLo; + UINT8 Res2006[0x200C-0x2006]; + UINT16 Lane0RxOvrdInHi; + UINT8 Res200E[0x2022-0x200E]; + UINT16 Lane0TxCmWaitTimeOvrd; + UINT8 Res2024[0x202A-0x2024]; + UINT16 Lane0TxLbertCtl; + UINT16 Lane0RxLbertCtl; + UINT16 Lane0RxLbertErr; + UINT8 Res2030[0x205A-0x2030]; + UINT16 Lane0TxAltBlock; +} CCSR_USB_PHY; + +/* Clocking */ +typedef struct { + struct { + UINT32 ClkCnCSr; /* core cluster n clock control status */ + UINT8 Res004[0x0c]; + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */ + UINT8 Res014[0x0c]; + } ClkcSr[4]; + UINT8 Res040[0x780]; /* 0x100 */ + struct { + UINT32 PllCnGSr; + UINT8 Res804[0x1c]; + } PllCgSr[NUM_CC_PLLS]; + UINT8 Res840[0x1c0]; + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */ + UINT8 Resa04[0x1fc]; + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */ + UINT8 Resc04[0x1c]; + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */ + UINT8 Resc24[0x3dc]; +} CCSR_CLOCK; + +VOID +GetSysInfo ( + OUT SYS_INFO * + ); + +UINT32 +EFIAPI +GurRead ( + IN UINTN Address + ); + +#endif /* NXP_SOC_H_ */ diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h new file mode 100644 index 000000000000..a934aaeff1f5 --- /dev/null +++ b/Silicon/NXP/Include/DramInfo.h @@ -0,0 +1,38 @@ +/** @file +* Header defining the structure for Dram Information +* +* Copyright 2019 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef DRAM_INFO_H_ +#define DRAM_INFO_H_ + +#include + +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +typedef struct { + UINTN BaseAddress; + UINTN Size; +} DRAM_REGION_INFO; + +typedef struct { + UINT32 NumOfDrams; + UINT32 Reserved; + DRAM_REGION_INFO DramRegion[3]; +} DRAM_INFO; + +EFI_STATUS +GetDramBankInfo ( + IN OUT DRAM_INFO *DramInfo + ); + +VOID +UpdateDpaaDram ( + IN OUT DRAM_INFO *DramInfo + ); + +#endif /* DRAM_INFO_H_ */ diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/= Include/SocSerDes.h new file mode 100644 index 000000000000..2d1c6f10f932 --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h @@ -0,0 +1,51 @@ +/** @file + The Header file of SerDes Module for LS1043A + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SOC_SERDES_H_ +#define SOC_SERDES_H_ + +#ifdef CHASSIS2 +#include +#endif + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + /* SerDes 1 */ + {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } }, + {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, + {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } }, + {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } }, + {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, + {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, + {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } }, + {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, + {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } }, + {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, + {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } }, + {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } }, + {0x9998, {Pcie1, Pcie2, Pcie3, Sata } }, + {0x6058, {Pcie1, Pcie1, Pcie2, Sata } }, + {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } }, + {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, + {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } }, + {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6= } }, + {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } }, + {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, + {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, + {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, + {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } }, + {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dt= sec6 }}, + {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl +}; + +#endif /* SOC_SERDES_H_ */ diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h new file mode 100644 index 000000000000..99f6439d8f35 --- /dev/null +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h @@ -0,0 +1,136 @@ +/** @file +* Header defining the Base addresses, sizes, flags etc for chassis 1 +* +* Copyright 2017-2019 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef NXP_CHASSIS_H_ +#define NXP_CHASSIS_H_ + +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Versi= on */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +#define TY_ITYP_VERSION_A7 0x1 +#define TY_ITYP_VERSION_A53 0x2 +#define TY_ITYP_VERSION_A57 0x3 +#define TY_ITYP_VERSION_A72 0x4 + +#define CPU_TYPE_ENTRY(N, V, NC) { .Name =3D #N, .SocVer =3D SVR_##V, .N= umCores =3D (NC)} + +#define SVR_WO_E 0xFFFFFE +#define SVR_LS1043A 0x879200 +#define SVR_LS1046A 0x870700 +#define SVR_LS2088A 0x870901 + +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) + +#define MHZ 1000000 + +typedef struct { + CHAR8 *Name; + UINT32 SocVer; + UINT32 NumCores; +} CPU_TYPE; + +typedef struct { + UINTN CpuClk; /* CPU clock in Hz! */ + UINTN BusClk; + UINTN MemClk; + UINTN PciClk; + UINTN SdhcClk; +} SOC_CLOCK_INFO; + +/* + * Print Soc information + */ +VOID +PrintSoc ( + VOID + ); + +/* + * Initialize Clock structure + */ +VOID +ClockInit ( + VOID + ); + +/* + * Setup SMMU in bypass mode + * and also set its pagesize + */ +VOID +SmmuInit ( + VOID + ); + +/* + * Print CPU information + */ +VOID +PrintCpuInfo ( + VOID + ); + +/* + * Dump RCW (Reset Control Word) on console + */ +VOID +PrintRCW ( + VOID + ); + +UINT32 +InitiatorType ( + IN UINT32 Cluster, + IN UINTN InitId + ); + +/* + * Return the mask for number of cores on this SOC. + */ +UINT32 +CpuMask ( + VOID + ); + +/* + * Return the number of cores on this SOC. + */ +UINTN +CpuNumCores ( + VOID + ); + +/* + * Return the type of initiator for core/hardware accelerator for given co= re index. + */ +UINTN +QoriqCoreToType ( + IN UINTN Core + ); + +/* + * Return the cluster of initiator for core/hardware accelerator for give= n core index. + */ +INT32 +QoriqCoreToCluster ( + IN UINTN Core + ); + +#endif /* NXP_CHASSIS_H_ */ diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c new file mode 100644 index 000000000000..5dda6f8c2662 --- /dev/null +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -0,0 +1,498 @@ +/** @file + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#ifdef CHASSIS2 +#include +#elif CHASSIS3 +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "NxpChassis.h" + +/* + * Structure to list available SOCs. + * Name, Soc Version, Number of Cores + */ +STATIC CPU_TYPE mCpuTypeList[] =3D { + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8), +}; + +UINT32 +EFIAPI +GurRead ( + IN UINTN Address + ) +{ + if (FixedPcdGetBool (PcdGurBigEndian)) { + return SwapMmioRead32 (Address); + } else { + return MmioRead32 (Address); + } +} + +/* + * Return the type of initiator (core or hardware accelerator) + */ +UINT32 +InitiatorType ( + IN UINT32 Cluster, + IN UINTN InitId + ) +{ + CCSR_GUR *GurBase; + UINT32 Idx; + UINT32 Type; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + Idx =3D (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK; + Type =3D GurRead ((UINTN)&GurBase->TpItyp[Idx]); + + if (Type & TP_ITYP_AV_MASK) { + return Type; + } + + return 0; +} + +/* + * Return the mask for number of cores on this SOC. + */ +UINT32 +CpuMask ( + VOID + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINT32 Mask; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + Mask =3D 0; + + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (TP_ITYP_TYPE_MASK (Type) =3D=3D TP_ITYP_TYPE_ARM) { + Mask |=3D 1 << Count; + } + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return Mask; +} + +/* + * Return the number of cores on this SOC. + */ +UINTN +CpuNumCores ( + VOID + ) +{ + UINTN Count; + UINTN Num; + + Count =3D 0; + Num =3D CpuMask (); + + while (Num) { + Count +=3D Num & 1; + Num >>=3D 1; + } + + return Count; +} + +/* + * Return core's cluster + */ +INT32 +QoriqCoreToCluster ( + IN UINTN Core + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (Count =3D=3D Core) { + return ClusterIndex; + } + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return -1; // cannot identify the cluster +} + +/* + * Return the type of core i.e. A53, A57 etc of inputted + * core number. + */ +UINTN +QoriqCoreToType ( + IN UINTN Core + ) +{ + CCSR_GUR *GurBase; + UINTN ClusterIndex; + UINTN Count; + UINT32 Cluster; + UINT32 Type; + UINTN InitiatorIndex; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClusterIndex =3D 0; + Count =3D 0; + + do { + Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); + for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { + Type =3D InitiatorType (Cluster, InitiatorIndex); + if (Type) { + if (Count =3D=3D Core) { + return Type; + } + Count++; + } + } + ClusterIndex++; + } while (CHECK_CLUSTER (Cluster)); + + return EFI_NOT_FOUND; /* cannot identify the cluster */ +} + +STATIC +UINTN +CpuMaskNext ( + IN UINTN Cpu, + IN UINTN Mask + ) +{ + for (Cpu++; !((1 << Cpu) & Mask); Cpu++); + + return Cpu; +} + +/* + * Print CPU information + */ +VOID +PrintCpuInfo ( + VOID + ) +{ + SYS_INFO SysInfo; + UINTN CoreIndex; + UINTN Core; + UINT32 Type; + UINT32 NumCpus; + UINT32 Mask; + CHAR8 *CoreName; + + GetSysInfo (&SysInfo); + DEBUG ((DEBUG_INIT, "Clock Configuration:")); + + NumCpus =3D CpuNumCores (); + Mask =3D CpuMask (); + + for (CoreIndex =3D 0, Core =3D CpuMaskNext(-1, Mask); + CoreIndex < NumCpus; + CoreIndex++, Core =3D CpuMaskNext(Core, Mask)) + { + if (!(CoreIndex % 3)) { + DEBUG ((DEBUG_INIT, "\n ")); + } + + Type =3D TP_ITYP_VERSION (QoriqCoreToType (Core)); + switch (Type) { + case TY_ITYP_VERSION_A7: + CoreName =3D "A7"; + break; + case TY_ITYP_VERSION_A53: + CoreName =3D "A53"; + break; + case TY_ITYP_VERSION_A57: + CoreName =3D "A57"; + break; + case TY_ITYP_VERSION_A72: + CoreName =3D "A72"; + break; + default: + CoreName =3D " Unknown Core "; + } + DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", + Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); + } + + DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBu= s / MHZ)); + DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); + + if (SysInfo.FreqFman[0] !=3D 0) { + DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[= 0] / MHZ)); + } + + DEBUG ((DEBUG_INIT, "\n")); +} + +/* + * Return system bus frequency + */ +UINT64 +GetBusFrequency ( + VOID + ) +{ + SYS_INFO SocSysInfo; + + GetSysInfo (&SocSysInfo); + + return SocSysInfo.FreqSystemBus; +} + +/* + * Return SDXC bus frequency + */ +UINT64 +GetSdxcFrequency ( + VOID + ) +{ + SYS_INFO SocSysInfo; + + GetSysInfo (&SocSysInfo); + + return SocSysInfo.FreqSdhc; +} + +/* + * Print Soc information + */ +VOID +PrintSoc ( + VOID + ) +{ + CHAR8 Buf[20]; + CCSR_GUR *GurBase; + UINTN Count; + // + // Svr : System Version Register + // + UINTN Svr; + UINTN Ver; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + Svr =3D GurRead ((UINTN)&GurBase->Svr); + Ver =3D SVR_SOC_VER (Svr); + + for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { + if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { + AsciiStrCpyS (Buf, AsciiStrnLenS (mCpuTypeList[Count].Name, 7) + 1, + (CONST CHAR8 *)mCpuTypeList[Count].Name); + + if (IS_E_PROCESSOR (Svr)) { + AsciiStrCatS (Buf, + (AsciiStrLen (Buf) + AsciiStrLen ((CONST CHAR8 *)"E") + 1), + (CONST CHAR8 *)"E"); + } + break; + } + } + + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); + + return; +} + +/* + * Dump RCW (Reset Control Word) on console + */ +VOID +PrintRCW ( + VOID + ) +{ + CCSR_GUR *Base; + UINTN Count; + + Base =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + + DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); + for (Count =3D 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { + UINT32 Rcw =3D SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); + + if ((Count % 4) =3D=3D 0) { + DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); + } + + DEBUG ((DEBUG_INIT, " %08x", Rcw)); + } + + DEBUG ((DEBUG_INIT, "\n")); +} + +/* + * Setup SMMU in bypass mode + * and also set its pagesize + */ +VOID +SmmuInit ( + VOID + ) +{ + UINT32 Value; + + /* set pagesize as 64K and ssmu-500 in bypass mode */ + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK); + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SC= R0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~S= CR0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); +} + +/* + * Return current Soc Name form mCpuTypeList + */ +CHAR8 * +GetSocName ( + VOID + ) +{ + UINT8 Count; + UINTN Svr; + UINTN Ver; + CCSR_GUR *GurBase; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + + Svr =3D GurRead ((UINTN)&GurBase->Svr); + Ver =3D SVR_SOC_VER (Svr); + + for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { + if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { + return (CHAR8 *)mCpuTypeList[Count].Name; + } + } + + return NULL; +} + +UINTN +GetDramSize ( + IN VOID + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D -1; + + ArmCallSmc (&ArmSmcArgs); + + if (ArmSmcArgs.Arg0) { + return 0; + } else { + return ArmSmcArgs.Arg1; + } +} + +EFI_STATUS +GetDramBankInfo ( + IN OUT DRAM_INFO *DramInfo + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + UINT32 I; + UINTN DramSize; + + DramSize =3D GetDramSize (); + DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize)); + + // Ensure DramSize has been set + ASSERT (DramSize !=3D 0); + + I =3D 0; + + do { + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D I; + + ArmCallSmc (&ArmSmcArgs); + if (ArmSmcArgs.Arg0) { + if (I > 0) { + break; + } else { + ASSERT (ArmSmcArgs.Arg0 =3D=3D 0); + } + } + + DramInfo->DramRegion[I].BaseAddress =3D ArmSmcArgs.Arg1; + DramInfo->DramRegion[I].Size =3D ArmSmcArgs.Arg2; + + DramSize -=3D DramInfo->DramRegion[I].Size; + + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", + I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size= )); + + I++; + } while (DramSize); + + DramInfo->NumOfDrams =3D I; + + DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDra= ms)); + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c new file mode 100644 index 000000000000..bfb8b8cb339a --- /dev/null +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -0,0 +1,162 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Calculate the frequency of various controllers and + populate the passed structure with frequuencies. + + @param PtrSysInfo Input structure to populate with + frequencies. +**/ +VOID +GetSysInfo ( + OUT SYS_INFO *PtrSysInfo + ) +{ + CCSR_GUR *GurBase; + CCSR_CLOCK *ClkBase; + UINTN CpuIndex; + UINT32 TempRcw; + UINT32 CPllSel; + UINT32 CplxPll; + CONST UINT8 CoreCplxPll[8] =3D { + [0] =3D 0, /* CC1 PPL / 1 */ + [1] =3D 0, /* CC1 PPL / 2 */ + [4] =3D 1, /* CC2 PPL / 1 */ + [5] =3D 1, /* CC2 PPL / 2 */ + }; + + CONST UINT8 CoreCplxPllDivisor[8] =3D { + [0] =3D 1, /* CC1 PPL / 1 */ + [1] =3D 2, /* CC1 PPL / 2 */ + [4] =3D 1, /* CC2 PPL / 1 */ + [5] =3D 2, /* CC2 PPL / 2 */ + }; + + UINTN PllCount; + UINTN FreqCPll[NUM_CC_PLLS]; + UINTN PllRatio[NUM_CC_PLLS]; + UINTN SysClk; + + GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + ClkBase =3D (VOID *)PcdGet64 (PcdClkBaseAddr); + SysClk =3D CLK_FREQ; + + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); + + PtrSysInfo->FreqSystemBus =3D SysClk; + PtrSysInfo->FreqDdrBus =3D SysClk; + + // + // selects the platform clock:SYSCLK ratio and calculate + // system frequency + // + PtrSysInfo->FreqSystemBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + // + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency + // + PtrSysInfo->FreqDdrBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> + CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & + CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; + + for (PllCount =3D 0; PllCount < NUM_CC_PLLS; PllCount++) { + PllRatio[PllCount] =3D (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].Pl= lCnGSr) >> 1) & 0xff; + if (PllRatio[PllCount] > 4) { + FreqCPll[PllCount] =3D SysClk * PllRatio[PllCount]; + } else { + FreqCPll[PllCount] =3D PtrSysInfo->FreqSystemBus * PllRatio[PllCount= ]; + } + } + + // + // Calculate Core frequency + // + for (CpuIndex =3D 0; CpuIndex < MAX_CPUS; CpuIndex++) { + CPllSel =3D (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 2= 7) & 0xf; + CplxPll =3D CoreCplxPll[CPllSel]; + + PtrSysInfo->FreqProcessor[CpuIndex] =3D FreqCPll[CplxPll] / CoreCplxPl= lDivisor[CPllSel]; + } + + // + // Calculate FMAN frequency + // + TempRcw =3D GurRead ((UINTN)&GurBase->RcwSr[7]); + switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { + case 2: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 2; + break; + case 3: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 3; + break; + case 4: + PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 4; + break; + case 5: + PtrSysInfo->FreqFman[0] =3D PtrSysInfo->FreqSystemBus; + break; + case 6: + PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 2; + break; + case 7: + PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 3; + break; + default: + DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n")); + break; + } + PtrSysInfo->FreqSdhc =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); + PtrSysInfo->FreqQman =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); +} + +/** + Function to initialize SoC specific constructs + CPU Info + SoC Personality + Board Personality + RCW prints + **/ +VOID +SocInit ( + VOID + ) +{ + SmmuInit (); + + // + // Early init serial Port to get board information. + // + SerialPortInitialize (); + DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE_= _)); + + PrintCpuInfo (); + + // + // Print Reset control Word + // + PrintRCW (); + PrintSoc (); + + return; +} diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocL= ib/SerDes.c new file mode 100644 index 000000000000..b9909d922138 --- /dev/null +++ b/Silicon/NXP/Library/SocLib/SerDes.c @@ -0,0 +1,268 @@ +/** SerDes.c + Provides the basic interfaces for SerDes Module + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifdef CHASSIS2 +#include +#include +#elif CHASSIS3 +#include +#include +#endif +#include +#include +#include + +/** + Function to get serdes Lane protocol corresponding to + serdes protocol. + + @param SerDes Serdes number. + @param Cfg Serdes Protocol. + @param Lane Serdes Lane number. + + @return Serdes Lane protocol. + +**/ +STATIC +SERDES_PROTOCOL +GetSerDesPrtcl ( + IN INTN SerDes, + IN INTN Cfg, + IN INTN Lane + ) +{ + SERDES_CONFIG *Config; + + if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { + return 0; + } + + Config =3D SerDesConfigTbl[SerDes]; + while (Config->Protocol) { + if (Config->Protocol =3D=3D Cfg) { + return Config->SrdsLane[Lane]; + } + Config++; + } + + return EFI_SUCCESS; +} + +/** + Function to check if inputted protocol is a valid serdes protocol. + + @param SerDes Serdes number. + @param Prtcl Serdes Protocol to be verified. + + @return EFI_INVALID_PARAMETER Input parameter in invalid. + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol. + @return EFI_SUCCESS Serdes Protocol is a valid protocol. + +**/ +STATIC +EFI_STATUS +CheckSerDesPrtclValid ( + IN INTN SerDes, + IN UINT32 Prtcl + ) +{ + SERDES_CONFIG *Config; + INTN Cnt; + + if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { + return EFI_INVALID_PARAMETER; + } + + Config =3D SerDesConfigTbl[SerDes]; + while (Config->Protocol) { + if (Config->Protocol =3D=3D Prtcl) { + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", = Prtcl)); + break; + } + Config++; + } + + if (!Config->Protocol) { + return EFI_NOT_FOUND; + } + + for (Cnt =3D 0; Cnt < SRDS_MAX_LANES; Cnt++) { + if (Config->SrdsLane[Cnt] !=3D None) { + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Function to fill serdes map information. + + @param Srds Serdes number. + @param SerdesProtocolMask Serdes Protocol Mask. + @param SerdesProtocolShift Serdes Protocol shift value. + @param SerDesPrtclMap Pointer to Serdes Protocol map. + +**/ +STATIC +VOID +LSSerDesMap ( + IN UINT32 Srds, + IN UINT32 SerdesProtocolMask, + IN UINT32 SerdesProtocolShift, + OUT UINT64 *SerDesPrtclMap + ) +{ + CCSR_GUR *Gur; + UINT32 SrdsProt; + INTN Lane; + UINT32 Flag; + + Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + *SerDesPrtclMap =3D 0x0; + Flag =3D 0; + + SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; + SrdsProt >>=3D SerdesProtocolShift; + + DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n", + Srds + 1, SrdsProt, SrdsProt)); + + if (EFI_SUCCESS !=3D CheckSerDesPrtclValid (Srds, SrdsProt)) { + DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] =3D 0x%x is not valid\n", + Srds + 1, SrdsProt)); + Flag++; + } + + for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { + SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); + if (LanePrtcl >=3D SerdesPrtclCount) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); + Flag++; + } else { + *SerDesPrtclMap |=3D (1u << LanePrtcl); + } + } + + if (Flag) { + DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n")); + } else { + DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n")); + } +} + +/** + Get lane protocol on provided serdes lane and execute callback function. + + @param Srds Serdes number. + @param SerdesProtocolMask Mask to get Serdes Protocol for Srds + @param SerdesProtocolShift Shift value to get Serdes Protocol for S= rds. + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +STATIC +VOID +SerDesInstanceProbeLanes ( + IN UINT32 Srds, + IN UINT32 SerdesProtocolMask, + IN UINT32 SerdesProtocolShift, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + + CCSR_GUR *Gur; + UINT32 SrdsProt; + INTN Lane; + + Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr);; + + SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; + SrdsProt >>=3D SerdesProtocolShift; + + /* + * Invoke callback for all lanes in the SerDes instance: + */ + for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { + SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); + if ((LanePrtcl >=3D SerdesPrtclCount) || (LanePrtcl < None)) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); + } else if (LanePrtcl !=3D None) { + SerDesLaneProbeCallback (LanePrtcl, Arg); + } + } +} + +/** + Probe all serdes lanes for lane protocol and execute provided callback f= unction. + + @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol + @param Arg Pointer to Arguments to be passed to cal= lback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + SerDesInstanceProbeLanes (Srds1, + RCWSR_SRDS1_PRTCL_MASK, + RCWSR_SRDS1_PRTCL_SHIFT, + SerDesLaneProbeCallback, + Arg); + + if (PcdGetBool (PcdSerdes2Enabled)) { + SerDesInstanceProbeLanes (Srds2, + RCWSR_SRDS2_PRTCL_MASK, + RCWSR_SRDS2_PRTCL_SHIFT, + SerDesLaneProbeCallback, + Arg); + } +} + +/** + Function to return Serdes protocol map for all serdes available on board. + + @param SerDesPrtclMap Pointer to Serdes protocl map. + +**/ +VOID +GetSerdesProtocolMaps ( + OUT UINT64 *SerDesPrtclMap + ) +{ + LSSerDesMap (Srds1, + RCWSR_SRDS1_PRTCL_MASK, + RCWSR_SRDS1_PRTCL_SHIFT, + SerDesPrtclMap); + + if (PcdGetBool (PcdSerdes2Enabled)) { + LSSerDesMap (Srds2, + RCWSR_SRDS2_PRTCL_MASK, + RCWSR_SRDS2_PRTCL_SHIFT, + SerDesPrtclMap); + } + +} + +BOOLEAN +IsSerDesLaneProtocolConfigured ( + IN UINT64 SerDesPrtclMap, + IN SERDES_PROTOCOL Device + ) +{ + if ((Device >=3D SerdesPrtclCount) || (Device < None)) { + ASSERT ((Device > None) && (Device < SerdesPrtclCount)); + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Devic= e)); + } + + return (SerDesPrtclMap & (1u << Device)) !=3D 0 ; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51038): https://edk2.groups.io/g/devel/message/51038 Mute This Topic: https://groups.io/mt/61076176/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51037+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51037+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332905; cv=none; d=zoho.com; s=zohoarc; b=QPDpk9yokjATM1vRR5KhFiQrptNoe6+LgRQqoUbRo6Qp/mTgvjciwXKZF1nkWUNRcLNypp1Kabs4IMS3SH+kCdtC/7/Jg1XOw2HsAhRPd3HJ7KQolW5PzgWouSlos07r/vUDN8cF+YShdY7dbP0i5mEPQYj1dyxBMzUBl45G44o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332905; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=pGuhx+MDkaUZNscUpVsOIJpLWnIzh+5D8vNKqMuGm38=; b=DB51SjnmhJzNx3EjROH/wiDzIl/Hl7hzLPvtBN8DZWZg1vummT7BG2e19RbqzRHBwIYJef2zheUZhzHhkmsb5J8lKMN5DXAjPFNQIgW3dFF49j7CvPeDuPVavXtTUnlVIZWPkeIi4hwE0h9Rschf+Xh2tktRCnDB3+5JNNsowtw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51037+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332905316183.1454461138335; Thu, 21 Nov 2019 02:41:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:44 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web11.22089.1574332903321447818 for ; Thu, 21 Nov 2019 02:41:43 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D78A41A08C1; Thu, 21 Nov 2019 11:41:41 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3E7C81A0124; Thu, 21 Nov 2019 11:41:41 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 8209D341; Thu, 21 Nov 2019 16:11:40 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Date: Thu, 21 Nov 2019 21:55:07 +0530 Message-Id: <1574353514-23986-5-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332904; bh=R4P0Y02JMlDr6PGrIQUGlkNJwzXc8+OQANbWHUYjKQU=; h=Cc:Date:From:Reply-To:Subject:To; b=MKGUb6QwFTCqA2FzurP+791sHQYvO1x3wV8y2yBG08VYvruhwhY3ILSus9OB+nmmarF /o3kQOAI+zEthjYQxwi9q1VNmOaTIk9IoUwro4h0mqxarsHf0RZOuwby0823SOTnjKrGd BGo218koZL3zhnSLganQvG1GJPfeLmlZKR0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 ++ Silicon/NXP/Library/DUartPortLib/DUart.h | 122 +++++++ Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 ++++++++++++++++++= ++ 3 files changed, 520 insertions(+) diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NX= P/Library/DUartPortLib/DUartPortLib.inf new file mode 100644 index 000000000000..7a2fa619b027 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf @@ -0,0 +1,34 @@ +# DUartPortLib.inf +# +# Component description file for DUartPortLib module +# +# Copyright (c) 2013, Freescale Ltd. All rights reserved. +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D DUartPortLib + FILE_GUID =3D c42dfe79-8de5-429e-a055-2d0a58591498 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Sources.common] + DUartPortLib.c + +[LibraryClasses] + PcdLib + SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library= /DUartPortLib/DUart.h new file mode 100644 index 000000000000..c71e2ce55d1d --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUart.h @@ -0,0 +1,122 @@ +/** DUart.h +* Header defining the DUART constants (Base addresses, sizes, flags) +* +* Based on Serial I/O Port library headers available in PL011Uart.h +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef DUART_H_ +#define DUART_H_ + +// FIFO Control Register +#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range= */ +#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +// Modem Control Register +#define DUART_MCR_DTR 0x01 /* Reserved */ +#define DUART_MCR_RTS 0x02 /* RTS */ +#define DUART_MCR_OUT1 0x04 /* Reserved */ +#define DUART_MCR_OUT2 0x08 /* Reserved */ +#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */ +#define DUART_MCR_DMA_EN 0x04 +#define DUART_MCR_TX_DFR 0x08 + +// Line Control Register +/* +* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting +* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. +*/ +#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define DUART_LCR_STB 0x04 /* # stop Bits, off=3D1, on=3D1.5 = or 2) */ +#define DUART_LCR_PEN 0x08 /* Parity eneble */ +#define DUART_LCR_EPS 0x10 /* Even Parity Select */ +#define DUART_LCR_STKP 0x20 /* Stick Parity */ +#define DUART_LCR_SBRK 0x40 /* Set Break */ +#define DUART_LCR_BKSE 0x80 /* Bank select enable */ +#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +// Line Status Register +#define DUART_LSR_DR 0x01 /* Data ready */ +#define DUART_LSR_OE 0x02 /* Overrun */ +#define DUART_LSR_PE 0x04 /* Parity error */ +#define DUART_LSR_FE 0x08 /* Framing error */ +#define DUART_LSR_BI 0x10 /* Break */ +#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define DUART_LSR_TEMT 0x40 /* Xmitter empty */ +#define DUART_LSR_ERR 0x80 /* Error */ + +// Modem Status Register +#define DUART_MSR_DCTS 0x01 /* Delta CTS */ +#define DUART_MSR_DDSR 0x02 /* Reserved */ +#define DUART_MSR_TERI 0x04 /* Reserved */ +#define DUART_MSR_DDCD 0x08 /* Reserved */ +#define DUART_MSR_CTS 0x10 /* Clear to Send */ +#define DUART_MSR_DSR 0x20 /* Reserved */ +#define DUART_MSR_RI 0x40 /* Reserved */ +#define DUART_MSR_DCD 0x80 /* Reserved */ + +// Interrupt Identification Register +#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define DUART_IIR_MSI 0x00 /* Modem status interrupt */ +#define DUART_IIR_THRI 0x02 /* Transmitter holding register em= pty */ +#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt = */ + +// Interrupt Enable Register +#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define DUART_IER_RLSI 0x04 /* Enable receiver line status int= errupt */ +#define DUART_IER_THRI 0x02 /* Enable Transmitter holding regi= ster int. */ +#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt = */ + +// LCR defaults +#define DUART_LCR_8N1 0x03 +#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 sto= p, no parity */ +#define DUART_MCRVAL (DUART_MCR_DTR | \ + DUART_MCR_RTS) /* RTS/DTR */ +#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \ + DUART_FCR_RXSR | \ + DUART_FCR_TXSR) /* Clear & enabl= e FIFOs */ + +#define URBR 0x0 +#define UTHR 0x0 +#define UDLB 0x0 +#define UDMB 0x1 +#define UIER 0x1 +#define UIIR 0x2 +#define UFCR 0x2 +#define UAFR 0x2 +#define ULCR 0x3 +#define UMCR 0x4 +#define ULSR 0x5 +#define UMSR 0x6 +#define USCR 0x7 +#define UDSR 0x10 + +extern +UINT64 +GetBusFrequency ( + VOID + ); + +#endif /* DUART_H_ */ diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/= Library/DUartPortLib/DUartPortLib.c new file mode 100644 index 000000000000..c3c738d3cca8 --- /dev/null +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c @@ -0,0 +1,364 @@ +/** DuartPortLib.c + DUART (NS16550) library functions + + Based on Serial I/O Port library functions available in PL011SerialPortL= ib.c + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#include "DUart.h" + +STATIC CONST UINT32 mInvalidControlBits =3D (EFI_SERIAL_SOFTWARE_LOOPBACK_= ENABLE | \ + EFI_SERIAL_DATA_TERMINAL_READY); + +/** + Assert or deassert the control signals on a serial port. + The following control signals are set according their bit settings : + . Request to Send + . Data Terminal Ready + + @param[in] Control The following bits are taken into account : + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert t= he + "Request To Send" control signal if this bit is + equal to one/zero. + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deasse= rt + the "Data Terminal Ready" control signal if th= is + bit is equal to one/zero. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/d= isable + the hardware loopback if this bit is equal to + one/zero. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supp= orted. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enab= le/ + disable the hardware flow control based on CTS= (Clear + To Send) and RTS (Ready To Send) control signa= ls. + + @retval EFI_SUCCESS The new control bits were set on the device. + @retval EFI_UNSUPPORTED The device does not support this operation. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINT32 McrBits; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + if (Control & (mInvalidControlBits)) { + return EFI_UNSUPPORTED; + } + + McrBits =3D MmioRead8 (UartBase + UMCR); + + if (Control & EFI_SERIAL_REQUEST_TO_SEND) { + McrBits |=3D DUART_MCR_RTS; + } else { + McrBits &=3D ~DUART_MCR_RTS; + } + + if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) { + McrBits |=3D DUART_MCR_LOOP; + } else { + McrBits &=3D ~DUART_MCR_LOOP; + } + + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) { + McrBits |=3D DUART_MCR_AFE; + } else { + McrBits &=3D ~DUART_MCR_AFE; + } + + MmioWrite32 (UartBase + UMCR, McrBits); + + return EFI_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param[out] Control Status of the control bits on a serial device : + + . EFI_SERIAL_DATA_CLEAR_TO_SEND, + EFI_SERIAL_DATA_SET_READY, + EFI_SERIAL_RING_INDICATE, + EFI_SERIAL_CARRIER_DETECT, + EFI_SERIAL_REQUEST_TO_SEND, + EFI_SERIAL_DATA_TERMINAL_READY + are all related to the DTE (Data Terminal Equip= ment) + and DCE (Data Communication Equipment) modes of + operation of the serial device. + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if= the + receive buffer is empty, 0 otherwise. + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one i= f the + transmit buffer is empty, 0 otherwise. + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to = one if + the hardware loopback is enabled (the ouput fee= ds the + receive buffer), 0 otherwise. + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to = one if + a loopback is accomplished by software, 0 other= wise. + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal= to + one if the hardware flow control based on CTS (= Clear + To Send) and RTS (Ready To Send) control signal= s is + enabled, 0 otherwise. + + @retval EFI_SUCCESS The control bits were read from the serial devi= ce. + +**/ +EFI_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINT32 MsrRegister; + UINT32 McrRegister; + UINT32 LsrRegister; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + MsrRegister =3D MmioRead8 (UartBase + UMSR); + McrRegister =3D MmioRead8 (UartBase + UMCR); + LsrRegister =3D MmioRead8 (UartBase + ULSR); + + *Control =3D 0; + + if ((MsrRegister & DUART_MSR_CTS) =3D=3D DUART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((McrRegister & DUART_MCR_RTS) =3D=3D DUART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if ((LsrRegister & DUART_LSR_TEMT) =3D=3D DUART_LSR_TEMT) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((McrRegister & DUART_MCR_AFE) =3D=3D DUART_MCR_AFE) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + if ((McrRegister & DUART_MCR_LOOP) =3D=3D DUART_MCR_LOOP) { + *Control |=3D EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE; + } + + return EFI_SUCCESS; +} + +/* + * Return Baud divisor on basis of Baudrate + */ +UINT32 +CalculateBaudDivisor ( + IN UINT64 BaudRate + ) +{ + UINTN DUartClk; + UINTN FreqSystemBus; + + FreqSystemBus =3D GetBusFrequency (); + DUartClk =3D FreqSystemBus/PcdGet32(PcdPlatformFreqDiv); + + return ((DUartClk)/(BaudRate * 16)); +} + +/* + Initialise the serial port to the specified settings. + All unspecified settings will be set to the default values. + + @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER. + + **/ +VOID +EFIAPI +DuartInitializePort ( + IN UINT64 BaudRate + ) +{ + UINTN UartBase; + UINT32 BaudDivisor; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + BaudDivisor =3D CalculateBaudDivisor (BaudRate); + + + while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT)); + + // + // Enable and assert interrupt when new data is available on + // external device, + // setup data format, setup baud divisor + // + MmioWrite8 (UartBase + UIER, 0x1); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, 0); + MmioWrite8 (UartBase + UDMB, 0); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + MmioWrite8 (UartBase + UMCR, DUART_MCRVAL); + MmioWrite8 (UartBase + UFCR, DUART_FCRVAL); + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL); + MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff); + MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff); + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL); + + return; +} + +/** + Programmed hardware of Serial port. + + @return Always return EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINT64 BaudRate; + BaudRate =3D (UINTN)PcdGet64 (PcdUartDefaultBaudRate); + + + DuartInitializePort (BaudRate); + + return EFI_SUCCESS; +} + +/** + Write data to serial device. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes written to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINT8 *Final; + UINTN UartBase; + + Final =3D &Buffer[NumberOfBytes]; + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + while (Buffer < Final) { + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) =3D=3D 0); + MmioWrite8 (UartBase + UTHR, *Buffer++); + } + + return NumberOfBytes; +} + +/** + Read data from serial device and save the data in buffer. + + @param Buffer Point of data buffer which need to be written. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed. + @retval !0 Actual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN Count; + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + for (Count =3D 0; Count < NumberOfBytes; Count++, Buffer++) { + // Loop while waiting for a new char(s) to arrive in the + // RxFIFO + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) =3D=3D 0); + + *Buffer =3D MmioRead8 (UartBase + URBR); + } + + return NumberOfBytes; +} + +/** + Check to see if any data is available to be read from the debug device. + + @retval EFI_SUCCESS At least one byte of data is available to be r= ead + @retval EFI_NOT_READY No data is available to be read + @retval EFI_DEVICE_ERROR The serial device is not functioning properly + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN UartBase; + + UartBase =3D (UINTN)PcdGet64 (PcdSerialRegisterBase); + + return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) !=3D 0); +} + +/** + Set new attributes to LS1043a. + + @param BaudRate The baud rate of the serial device. If t= he baud rate is not supported, + the speed will be reduced down to the ne= arest supported one and the + variable's value will be updated accordi= ngly. + @param ReceiveFifoDepth The number of characters the device will= buffer on input. If the specified + value is not supported, the variable's v= alue will be reduced down to the + nearest supported one. + @param Timeout If applicable, the number of microsecond= s the device will wait + before timing out a Read or a Write oper= ation. + @param Parity If applicable, this is the EFI_PARITY_TY= PE that is computed or checked + as each character is transmitted or rece= ived. If the device does not + support parity, the value is the default= parity value. + @param DataBits The number of data bits in each character + @param StopBits If applicable, the EFI_STOP_BITS_TYPE nu= mber of stop bits per character. + If the device does not support stop bits= , the value is the default stop + bit value. + + @retval EFI_SUCCESS All attributes were set correctly on the= serial device. + +**/ +EFI_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + DuartInitializePort (*BaudRate); + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51037): https://edk2.groups.io/g/devel/message/51037 Mute This Topic: https://groups.io/mt/61076175/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51039+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51039+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332906; cv=none; d=zoho.com; s=zohoarc; b=hgG/eCc9PKRd03uO7ZKmI0EqRj1tosRJXly6bTaA50rDHFAHs+HRm8zMZivOEFF4oSQNNE+pjq9H57euFBcCTJ6XxFIKS/uJgct7p64aBF40rhv7APfNQmM8PptlXQAp91IgM6wpIOYDcKX+tlrjlyKqnZJFQ+/1h/gaBFK1XTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332906; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qctz+9JVU2HxlGIlmaTuY4i4WZBQtT52tBkEGE3yOcY=; b=YGnN2ncwk98PmPJal6/SCVS8pJ1t1StRHsBbffHlnPJz/WrsSr4s61iMsM/rCmK6bpC/fM3IVkvd0uj7Cs4VvT8oOfce1xRThYo1vWL88JpoFDVvHpPpH0Y2RqJLWZvUiZGzTJqjNecs9alxEP5VW5L2vV1LyMJBxkg4xm8zQKs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51039+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332906366411.78532582225455; Thu, 21 Nov 2019 02:41:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:45 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web09.22249.1574332904340370532 for ; Thu, 21 Nov 2019 02:41:45 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D69551A0009; Thu, 21 Nov 2019 11:41:42 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 354021A08B3; Thu, 21 Nov 2019 11:41:42 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 282F7364; Thu, 21 Nov 2019 16:11:41 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Date: Thu, 21 Nov 2019 21:55:08 +0530 Message-Id: <1574353514-23986-6-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332905; bh=AFjUuoEQKp3adLBAjZSfQyhTryXyB3U01xrl/wn7MHo=; h=Cc:Date:From:Reply-To:Subject:To; b=V4UtIfhjjHyOfVZnznBw2fe8LG64xzNa2spm21WqdgSW5AAOCb+x1Gi6KKc8zQZn9Ak Ft/d7oYbag2GTgPpMYlldKr2Ztv5tB0h6mNo7z/+lu6ZHovKpxz9/SY8sP4NKRDEM/hkJ jVQ3wFa5epza1hfwEf+eSMPm96adWVx5+pU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" I2C driver produces gEfiI2cMasterProtocolGuid which can be used by other modules. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Notes: v2: - indentation correction - STATIC variable with 'm' prefix Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++ Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++ Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 +++++ Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++ Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 ++++++++++++++++++++ 5 files changed, 1262 insertions(+) diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2= cDxe/I2cDxe.inf new file mode 100644 index 000000000000..0c0bf63bb2e2 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -0,0 +1,58 @@ +# @file +# +# Component description file for I2c driver +# +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D I2cDxe + FILE_GUID =3D 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D I2cDxeEntryPoint + UNLOAD =3D I2cDxeUnload + +[Sources.common] + ComponentName.c + DriverBinding.c + I2cDxe.c + +[LibraryClasses] + ArmLib + BaseMemoryLib + DevicePathLib + IoLib + MemoryAllocationLib + PcdLib + SocLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Guids] + gNxpNonDiscoverableI2cMasterGuid + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START + gEfiI2cMasterProtocolGuid ## BY_START + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController + +[Depex] + TRUE diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.h new file mode 100644 index 000000000000..02a29a5cf2b9 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h @@ -0,0 +1,100 @@ +/** I2cDxe.h + Header defining the constant, base address amd function for I2C controll= er + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef I2C_DXE_H_ +#define I2C_DXE_H_ + +#include +#include + +#include +#include + +#define I2C_CR_IIEN (1 << 6) +#define I2C_CR_MSTA (1 << 5) +#define I2C_CR_MTX (1 << 4) +#define I2C_CR_TX_NO_AK (1 << 3) +#define I2C_CR_RSTA (1 << 2) + +#define I2C_SR_ICF (1 << 7) +#define I2C_SR_IBB (1 << 5) +#define I2C_SR_IAL (1 << 4) +#define I2C_SR_IIF (1 << 1) +#define I2C_SR_RX_NO_AK (1 << 0) + +#define I2C_CR_IEN (0 << 7) +#define I2C_CR_IDIS (1 << 7) +#define I2C_SR_IIF_CLEAR (1 << 1) + +#define BUS_IDLE (0 | (I2C_SR_IBB << 8)) +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8)) +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8)) + +#define I2C_FLAG_WRITE 0x0 + +#define I2C_STATE_RETRIES 50000 + +#define RETRY_COUNT 3 + +#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C') +#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \ + I2cMaster, NXP_I2C_SIGNATURE) + +extern EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2; + +#pragma pack(1) +typedef struct { + VENDOR_DEVICE_PATH Vendor; + UINT64 MmioBase; + EFI_DEVICE_PATH_PROTOCOL End; +} NXP_I2C_DEVICE_PATH; +#pragma pack() + +typedef struct { + UINT32 Signature; + EFI_I2C_MASTER_PROTOCOL I2cMaster; + NXP_I2C_DEVICE_PATH DevicePath; + NON_DISCOVERABLE_DEVICE *Dev; +} NXP_I2C_MASTER; + +/** + Record defining i2c registers +**/ +typedef struct { + UINT8 I2cAdr; + UINT8 I2cFdr; + UINT8 I2cCr; + UINT8 I2cSr; + UINT8 I2cDr; +} I2C_REGS; + +typedef struct { + UINT16 SCLDivider; + UINT16 BusClockRate; +} CLK_DIV; + +extern +UINT64 +GetBusFrequency ( + VOID + ); + +EFI_STATUS +NxpI2cInit ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle + ); + +EFI_STATUS +NxpI2cRelease ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle + ); + +#endif //I2C_DXE_H_ diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c b/Silicon/NXP/Drive= rs/I2cDxe/ComponentName.c new file mode 100644 index 000000000000..a71d75c2913a --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c @@ -0,0 +1,179 @@ +/** @file + + Copyright 2018-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "I2cDxe.h" + +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] =3D { + { + "en", + (CHAR16 *)L"Nxp I2C Driver" + }, + { } +}; + +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] =3D { + { + "en", + (CHAR16 *)L"Nxp I2C Controller" + }, + { } +}; + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form o= f a + Unicode string. If the driver specified by This has a user readable name= in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver speci= fied + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTO= COL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the calle= r is + requesting, and it must match one of the + languages specified in SupportedLanguages.= The + number of languages supported by a driver = is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code for= mat. + + @param DriverName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specifie= d by + This and the language specified by Languag= e was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not supp= ort + the language specified by Language. + +**/ +STATIC +EFI_STATUS +EFIAPI +NxpI2cGetDriverName ( + IN EFI_COMPONENT_NAME2_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ) +{ + return LookupUnicodeString2 (Language, + This->SupportedLanguages, + mNxpI2cDriverNameTable, + DriverName, + FALSE); +} + +/** + Retrieves a Unicode string that is the user readable name of the control= ler + that is being managed by a driver. + + This function retrieves the user readable name of the controller specifi= ed by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specif= ied by + Language, then a pointer to the controller name is returned in Controlle= rName, + and EFI_SUCCESS is returned. If the driver specified by This is not cur= rently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does = not + support the language specified by Language, then EFI_UNSUPPORTED is retu= rned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTO= COL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param ControllerHandle[in] The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to = be + returned. + + @param ChildHandle[in] The handle of the child controller to retr= ieve + the name of. This is an optional paramete= r that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus d= rivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of= a + child controller. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the calle= r is + requesting, and it must match one of the + languages specified in SupportedLanguages.= The + number of languages supported by a driver = is up + to the driver writer. Language is specifie= d in + RFC 4646 or ISO 639-2 language code format. + + @param ControllerName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle a= nd + ChildHandle in the language specified by + Language from the point of view of the dri= ver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable n= ame in + the language specified by Language for the + driver specified by This was returned in + DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a va= lid + EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is not curren= tly + managing the controller specified by + ControllerHandle and ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This does not supp= ort + the language specified by Language. + +**/ +STATIC +EFI_STATUS +EFIAPI +NxpI2cGetControllerName ( + IN EFI_COMPONENT_NAME2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle O= PTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ) +{ + if (ChildHandle !=3D NULL) { + return EFI_UNSUPPORTED; + } + + return LookupUnicodeString2 (Language, + This->SupportedLanguages, + mNxpI2cControllerNameTable, + ControllerName, + FALSE); +} + +// +// EFI Component Name 2 Protocol +// +EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2 =3D { + NxpI2cGetDriverName, + NxpI2cGetControllerName, + "en" +}; diff --git a/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c b/Silicon/NXP/Drive= rs/I2cDxe/DriverBinding.c new file mode 100644 index 000000000000..59320447b5fd --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c @@ -0,0 +1,235 @@ +/** @file + + Copyright 2018-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include + +#include "I2cDxe.h" + +/** + Tests to see if this driver supports a given controller. + + @param This[in] A pointer to the EFI_DRIVER_BINDING_PRO= TOCOL + instance. + @param ControllerHandle[in] The handle of the controller to test. + @param RemainingDevicePath[in] The remaining device path. + (Ignored - this is not a bus driver.) + + @retval EFI_SUCCESS The driver supports this controller. + @retval EFI_ALREADY_STARTED The device specified by ControllerHandl= e is + already being managed by the driver spe= cified + by This. + @retval EFI_UNSUPPORTED The device specified by ControllerHandl= e is + not supported by the driver specified b= y This. + +**/ +EFI_STATUS +EFIAPI +NxpI2cDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + NON_DISCOVERABLE_DEVICE *Dev; + EFI_STATUS Status; + + // + // Connect to the non-discoverable device + // + Status =3D gBS->OpenProtocol (ControllerHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + (VOID **) &Dev, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER); + if (EFI_ERROR (Status)) { + return Status; + } + + if (CompareGuid (Dev->Type, &gNxpNonDiscoverableI2cMasterGuid)) { + Status =3D EFI_SUCCESS; + } else { + Status =3D EFI_UNSUPPORTED; + } + + // + // Clean up. + // + gBS->CloseProtocol (ControllerHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + This->DriverBindingHandle, + ControllerHandle); + + return Status; +} + + +/** + Starts a device controller or a bus controller. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PRO= TOCOL + instance. + @param[in] ControllerHandle The handle of the device to start. This + handle must support a protocol interfac= e that + supplies an I/O abstraction to the driv= er. + @param[in] RemainingDevicePath The remaining portion of the device pat= h. + (Ignored - this is not a bus driver.) + + @retval EFI_SUCCESS The device was started. + @retval EFI_DEVICE_ERROR The device could not be started due to a + device error. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +NxpI2cDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + return NxpI2cInit (This->DriverBindingHandle, ControllerHandle); +} + + +/** + Stops a device controller or a bus controller. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOC= OL + instance. + @param[in] ControllerHandle A handle to the device being stopped. The = handle + must support a bus specific I/O protocol f= or the + driver to use to stop the device. + @param[in] NumberOfChildren The number of child device handles in + ChildHandleBuffer. + @param[in] ChildHandleBuffer An array of child handles to be freed. May= be + NULL if NumberOfChildren is 0. + + @retval EFI_SUCCESS The device was stopped. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a d= evice + error. + +**/ +EFI_STATUS +EFIAPI +NxpI2cDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + return NxpI2cRelease (This->DriverBindingHandle, ControllerHandle); +} + + +STATIC EFI_DRIVER_BINDING_PROTOCOL gNxpI2cDriverBinding =3D { + NxpI2cDriverBindingSupported, + NxpI2cDriverBindingStart, + NxpI2cDriverBindingStop, + 0xa, + NULL, + NULL +}; + + +/** + The entry point of I2c UEFI Driver. + + @param ImageHandle The image handle of the UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The Driver or UEFI Driver exited norm= ally. + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than + SystemTable->Hdr.Revision. + +**/ +EFI_STATUS +EFIAPI +I2cDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Add the driver to the list of drivers + // + Status =3D EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, SystemTable, &gNxpI2cDriverBinding, ImageHandle, + NULL, &gNxpI2cDriverComponentName2); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +/** + Unload function for the I2c UEFI Driver. + + @param ImageHandle[in] The allocated handle for the EFI image + + @retval EFI_SUCCESS The driver was unloaded successfully + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle. + +**/ +EFI_STATUS +EFIAPI +I2cDxeUnload ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + + // + // Retrieve all USB I/O handles in the handle database + // + Status =3D gBS->LocateHandleBuffer (ByProtocol, + &gEdkiiNonDiscoverableDeviceProtocolGu= id, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Disconnect the driver from the handles in the handle database + // + for (Index =3D 0; Index < HandleCount; Index++) { + Status =3D gBS->DisconnectController (HandleBuffer[Index], + gImageHandle, + NULL); + } + + // + // Free the handle array + // + gBS->FreePool (HandleBuffer); + + // + // Uninstall protocols installed by the driver in its entrypoint + // + Status =3D gBS->UninstallMultipleProtocolInterfaces (ImageHandle, + &gEfiDriverBindingProtocolGuid, + &gNxpI2cDriverBinding, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.c new file mode 100644 index 000000000000..853c426fbca2 --- /dev/null +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c @@ -0,0 +1,690 @@ +/** I2cDxe.c + I2c driver APIs for read, write, initialize, set speed and reset + + Copyright 2017-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "I2cDxe.h" + +STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cControllerCapabilities = =3D { + 0, + 0, + 0, + 0 +}; + +STATIC CONST CLK_DIV mClkDiv[] =3D { + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E } +}; + +/** + Calculate and return proper clock divider + + @param Rate desired clock rate + + @retval ClkDiv Index value used to get Bus Clock Rate + +**/ +STATIC +UINT8 +GetClkDivIndex ( + IN UINT32 Rate + ) +{ + UINTN ClkRate; + UINT32 Div; + UINT8 Index; + + Index =3D 0; + ClkRate =3D GetBusFrequency (); + + Div =3D (ClkRate + Rate - 1) / Rate; + + if (Div < mClkDiv[0].SCLDivider) { + return 0; + } + + do { + if (mClkDiv[Index].SCLDivider >=3D Div ) { + return Index; + } + Index++; + } while (Index < ARRAY_SIZE (mClkDiv)); + + return (ARRAY_SIZE (mClkDiv) - 1); +} + +/** + Function used to check if i2c is in mentioned state or not + + @param I2cRegs Pointer to I2C registers + @param State i2c state need to be checked + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval CurrState Value of state register + +**/ +STATIC +EFI_STATUS +WaitForI2cState ( + IN I2C_REGS *I2cRegs, + IN UINT32 State + ) +{ + UINT8 CurrState; + UINT64 Count; + + for (Count =3D 0; Count < I2C_STATE_RETRIES; Count++) { + MemoryFence (); + CurrState =3D MmioRead8 ((UINTN)&I2cRegs->I2cSr); + if (CurrState & I2C_SR_IAL) { + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL); + return EFI_NOT_READY; + } + + if ((CurrState & (State >> 8)) =3D=3D (UINT8)State) { + return CurrState; + } + } + + return EFI_TIMEOUT; +} + +/** + Function to transfer byte on i2c + + @param I2cRegs Pointer to i2c registers + @param Byte Byte to be transferred on i2c bus + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Data transfer was succesful + +**/ +STATIC +EFI_STATUS +TransferByte ( + IN I2C_REGS *I2cRegs, + IN UINT8 Byte + ) +{ + EFI_STATUS RetVal; + + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte); + + RetVal =3D WaitForI2cState (I2cRegs, IIF); + if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { + return RetVal; + } + + if (RetVal & I2C_SR_RX_NO_AK) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Function to stop transaction on i2c bus + + @param I2cRegs Pointer to i2c registers + + @retval EFI_NOT_READY Arbitration was lost + @retval EFI_TIMEOUT Timeout occured + @retval EFI_SUCCESS Stop operation was successful + +**/ +STATIC +EFI_STATUS +I2cStop ( + IN I2C_REGS *I2cRegs + ) +{ + EFI_STATUS RetVal; + UINT32 Temp; + + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + + Temp &=3D ~(I2C_CR_MSTA | I2C_CR_MTX); + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + RetVal =3D WaitForI2cState (I2cRegs, BUS_IDLE); + + if (RetVal < 0) { + return RetVal; + } else { + return EFI_SUCCESS; + } +} + +/** + Function to send start signal, Chip Address and + memory offset + + @param I2cRegs Pointer to i2c base registers + @param Chip Chip Address + @param Offset Slave memory's offset + @param AddressLength length of chip address + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +InitTransfer ( + IN I2C_REGS *I2cRegs, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 AddressLength + ) +{ + UINT32 Temp; + EFI_STATUS RetVal; + + // Enable I2C controller + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) { + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN); + } + + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) =3D=3D (Chip << 1)) { + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2); + } + + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + RetVal =3D WaitForI2cState (I2cRegs, BUS_IDLE); + if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { + return RetVal; + } + + // Start I2C transaction + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + // set to master mode + Temp |=3D I2C_CR_MSTA; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + RetVal =3D WaitForI2cState (I2cRegs, BUS_BUSY); + if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { + return RetVal; + } + + Temp |=3D I2C_CR_MTX | I2C_CR_TX_NO_AK; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + // write slave Address + RetVal =3D TransferByte (I2cRegs, Chip << 1); + if (RetVal !=3D EFI_SUCCESS) { + return RetVal; + } + + if (AddressLength >=3D 0) { + while (AddressLength--) { + RetVal =3D TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & = 0xff); + if (RetVal !=3D EFI_SUCCESS) + return RetVal; + } + } + return EFI_SUCCESS; +} + +/** + Function to check if i2c bus is idle + + @param Base Pointer to base address of I2c controller + + @retval EFI_SUCCESS + +**/ +STATIC +INT32 +I2cBusIdle ( + IN VOID *Base + ) +{ + return EFI_SUCCESS; +} + +/** + Function to initiate data transfer on i2c bus + + @param I2cRegs Pointer to i2c base registers + @param Chip Chip Address + @param Offset Slave memory's offset + @param AddressLength length of chip address + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +InitDataTransfer ( + IN I2C_REGS *I2cRegs, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 AddressLength + ) +{ + EFI_STATUS RetVal; + INT32 Retry; + + for (Retry =3D 0; Retry < RETRY_COUNT; Retry++) { + RetVal =3D InitTransfer (I2cRegs, Chip, Offset, AddressLength); + if (RetVal =3D=3D EFI_SUCCESS) { + return EFI_SUCCESS; + } + + I2cStop (I2cRegs); + + if (EFI_NOT_FOUND =3D=3D RetVal) { + return RetVal; + } + + // Disable controller + if (RetVal !=3D EFI_NOT_READY) { + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); + } + + if (I2cBusIdle (I2cRegs) < 0) { + break; + } + } + return RetVal; +} + +/** + Function to read data using i2c bus + + @param BaseAddr I2c Controller Base Address + @param Chip Address of slave device from where data to be r= ead + @param Offset Offset of slave memory + @param AddressLength Address length of slave + @param Buffer A pointer to the destination buffer for the data + @param Len Length of data to be read + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +I2cDataRead ( + IN UINTN BaseAddr, + IN UINT8 Chip, + IN UINT32 Offset, + IN UINT32 AddressLength, + IN UINT8 *Buffer, + IN UINT32 Len + ) +{ + EFI_STATUS RetVal; + UINT32 Temp; + INT32 I; + I2C_REGS *I2cRegs; + + I2cRegs =3D (I2C_REGS *)(BaseAddr); + + RetVal =3D InitDataTransfer (I2cRegs, Chip, Offset, AddressLength); + if (RetVal !=3D EFI_SUCCESS) { + return RetVal; + } + + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp |=3D I2C_CR_RSTA; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + + RetVal =3D TransferByte (I2cRegs, (Chip << 1) | 1); + if (RetVal !=3D EFI_SUCCESS) { + I2cStop (I2cRegs); + return RetVal; + } + + // setup bus to read data + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp &=3D ~(I2C_CR_MTX | I2C_CR_TX_NO_AK); + if (Len =3D=3D 1) { + Temp |=3D I2C_CR_TX_NO_AK; + } + + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + + // Dummy Read to initiate recieve operation + MmioRead8 ((UINTN)&I2cRegs->I2cDr); + + for (I =3D 0; I < Len; I++) { + RetVal =3D WaitForI2cState (I2cRegs, IIF); + if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { + I2cStop (I2cRegs); + return RetVal; + } + // + // It must generate STOP before read I2DR to prevent + // controller from generating another clock cycle + // + if (I =3D=3D (Len - 1)) { + I2cStop (I2cRegs); + } else if (I =3D=3D (Len - 2)) { + Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); + Temp |=3D I2C_CR_TX_NO_AK; + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); + } + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); + Buffer[I] =3D MmioRead8 ((UINTN)&I2cRegs->I2cDr); + } + + I2cStop (I2cRegs); + + return EFI_SUCCESS; +} + +/** + Function to write data using i2c bus + + @param BaseAddr I2c Controller Base Address + @param Chip Address of slave device where data to be written + @param Offset Offset of slave memory + @param AddressLength Address length of slave + @param Buffer A pointer to the source buffer for the data + @param Len Length of data to be write + + @retval EFI_NOT_READY Arbitration lost + @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time + @retval EFI_NOT_FOUND ACK was not recieved + @retval EFI_SUCCESS Read was successful + +**/ +STATIC +EFI_STATUS +I2cDataWrite ( + IN UINTN BaseAddr, + IN UINT8 Chip, + IN UINT32 Offset, + IN INT32 AddressLength, + OUT UINT8 *Buffer, + IN INT32 Len + ) +{ + EFI_STATUS RetVal; + I2C_REGS *I2cRegs; + INT32 I; + + I2cRegs =3D (I2C_REGS *)BaseAddr; + + RetVal =3D InitDataTransfer (I2cRegs, Chip, Offset, AddressLength); + if (RetVal !=3D EFI_SUCCESS) { + return RetVal; + } + + // Write operation + for (I =3D 0; I < Len; I++) { + RetVal =3D TransferByte (I2cRegs, Buffer[I]); + if (RetVal !=3D EFI_SUCCESS) { + break; + } + } + + I2cStop (I2cRegs); + return RetVal; +} + +/** + Function to set i2c bus frequency + + @param This Pointer to I2c master protocol + @param BusClockHertz value to be set + + @retval EFI_SUCCESS Operation successfull +**/ +STATIC +EFI_STATUS +EFIAPI +SetBusFrequency ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN OUT UINTN *BusClockHertz + ) +{ + I2C_REGS *I2cRegs; + UINT8 ClkId; + UINT8 SpeedId; + NXP_I2C_MASTER *I2c; + + I2c =3D NXP_I2C_FROM_THIS (This); + + I2cRegs =3D (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin); + + ClkId =3D GetClkDivIndex (*BusClockHertz); + SpeedId =3D mClkDiv[ClkId].BusClockRate; + + // Store divider value + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId); + + MemoryFence (); + + return EFI_SUCCESS; +} + +/** + Function to reset I2c Controller + + @param This Pointer to I2c master protocol + + @return EFI_SUCCESS Operation successfull +**/ +STATIC +EFI_STATUS +EFIAPI +Reset ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ) +{ + I2C_REGS *I2cRegs; + NXP_I2C_MASTER *I2c; + + I2c =3D NXP_I2C_FROM_THIS (This); + + I2cRegs =3D (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin); + + // Reset module + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0); + + MemoryFence (); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +StartRequest ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + IN EFI_EVENT Event OPTIONAL, + OUT EFI_STATUS *I2cStatus OPTIONAL + ) +{ + NXP_I2C_MASTER *I2c; + UINT32 Count; + INT32 RetVal; + UINT32 Length; + UINT8 *Buffer; + UINT32 Flag; + UINT32 RegAddress; + UINT32 OffsetLength; + + RegAddress =3D 0; + + I2c =3D NXP_I2C_FROM_THIS (This); + + if (RequestPacket->OperationCount <=3D 0) { + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n", + __FUNCTION__, RequestPacket->OperationCount)); + return EFI_INVALID_PARAMETER; + } + + OffsetLength =3D RequestPacket->Operation[0].LengthInBytes; + RegAddress =3D *RequestPacket->Operation[0].Buffer; + + for (Count =3D 1; Count < RequestPacket->OperationCount; Count++) { + Flag =3D RequestPacket->Operation[Count].Flags; + Length =3D RequestPacket->Operation[Count].LengthInBytes; + Buffer =3D RequestPacket->Operation[Count].Buffer; + + if (Length <=3D 0) { + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n", + __FUNCTION__, Length)); + return EFI_INVALID_PARAMETER; + } + + if (Flag =3D=3D I2C_FLAG_READ) { + RetVal =3D I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAd= dress, + RegAddress, OffsetLength, Buffer, Length); + if (RetVal !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n", + __FUNCTION__, RetVal)); + return RetVal; + } + } else if (Flag =3D=3D I2C_FLAG_WRITE) { + RetVal =3D I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveA= ddress, + RegAddress, OffsetLength, Buffer, Length); + if (RetVal !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n", + __FUNCTION__, RetVal)); + return RetVal; + } + } else { + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag)); + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +NxpI2cInit ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle + ) +{ + EFI_STATUS RetVal; + NON_DISCOVERABLE_DEVICE *Dev; + NXP_I2C_MASTER *I2c; + + RetVal =3D gBS->OpenProtocol (ControllerHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + (VOID **)&Dev, DriverBindingHandle, + ControllerHandle, EFI_OPEN_PROTOCOL_BY_DRIVE= R); + if (EFI_ERROR (RetVal)) { + return RetVal; + } + + I2c =3D AllocateZeroPool (sizeof (NXP_I2C_MASTER)); + + I2c->Signature =3D NXP_I2C_SIGNATURE; + I2c->I2cMaster.SetBusFrequency =3D SetBusFrequency; + I2c->I2cMaster.Reset =3D Reset; + I2c->I2cMaster.StartRequest =3D StartRequest; + I2c->I2cMaster.I2cControllerCapabilities =3D &mI2cControllerCapabilitie= s; + I2c->Dev =3D Dev; + + CopyGuid (&I2c->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); + I2c->DevicePath.MmioBase =3D I2c->Dev->Resources[0].AddrRangeMin; + SetDevicePathNodeLength (&I2c->DevicePath.Vendor, + sizeof (I2c->DevicePath) - sizeof (I2c->DevicePath.End)); + SetDevicePathEndNode (&I2c->DevicePath.End); + + RetVal =3D gBS->InstallMultipleProtocolInterfaces (&ControllerHandle, + &gEfiI2cMasterProtocolGuid, (VOID**)&I2c->I2cMaster, + &gEfiDevicePathProtocolGuid, &I2c->DevicePath, + NULL); + + if (EFI_ERROR (RetVal)) { + FreePool (I2c); + gBS->CloseProtocol (ControllerHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + DriverBindingHandle, + ControllerHandle); + } + + return RetVal; +} + +EFI_STATUS +NxpI2cRelease ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle + ) +{ + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + EFI_STATUS RetVal; + NXP_I2C_MASTER *I2c; + + RetVal =3D gBS->HandleProtocol (ControllerHandle, + &gEfiI2cMasterProtocolGuid, + (VOID **)&I2cMaster); + ASSERT_EFI_ERROR (RetVal); + if (EFI_ERROR (RetVal)) { + return RetVal; + } + + I2c =3D NXP_I2C_FROM_THIS (I2cMaster); + + RetVal =3D gBS->UninstallMultipleProtocolInterfaces (ControllerHandle, + &gEfiI2cMasterProtocolGuid, I2cMaster, + &gEfiDevicePathProtocolGuid, &I2c->DevicePath, + NULL); + if (EFI_ERROR (RetVal)) { + return RetVal; + } + + RetVal =3D gBS->CloseProtocol (ControllerHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + DriverBindingHandle, + ControllerHandle); + ASSERT_EFI_ERROR (RetVal); + if (EFI_ERROR (RetVal)) { + return RetVal; + } + + gBS->FreePool (I2c); + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 21 Nov 2019 02:41:45 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 174B01A0124; Thu, 21 Nov 2019 11:41:43 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 949271A0A3D; Thu, 21 Nov 2019 11:41:42 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id CE5EA366; Thu, 21 Nov 2019 16:11:41 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library Date: Thu, 21 Nov 2019 21:55:09 +0530 Message-Id: <1574353514-23986-7-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332905; bh=ZCGNqtlRyAr3oPbYmtbnqcQDW9k6A+mbVjYCDGd939g=; h=Cc:Date:From:Reply-To:Subject:To; b=VMhJSn5TPEy9Jtge9FoDuIYAPU216+z8vju3uixnbj8fAh6mg3/lPniEWluITA5mFvG WSPaMdQvMkGTgJGjxUyVZ0+Lgq2edDzCnAhbUJ+CpyGckdSBG/sHtFiPQvfDQZKCQDSmP BXZv8b5+pQSEIzRNLwD+JCcRZLKlLy24uHc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Real time clock Apis on top of I2C Apis Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 23 ++ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 40 +++ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 48 +++ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 372 ++++++++++++++++= ++++ 4 files changed, 483 insertions(+) diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/= Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec new file mode 100644 index 000000000000..27283e714732 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec @@ -0,0 +1,23 @@ +#/** @file +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Ds1307RtcLib + PACKAGE_GUID =3D 0c095cf6-834d-4fa2-a5a0-31ac35591ad2 + PACKAGE_VERSION =3D 0.1 + +[Guids] + gDs1307RtcLibTokenSpaceGuid =3D { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x= 2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }} + +[Protocols] + gDs1307RealTimeClockLibI2cMasterProtocolGuid =3D { 0xd37c4d54, 0x1bca, 0= x49e0, { 0xa0, 0x4a, 0x5c, 0x37, 0x59, 0x38, 0xc7, 0xec}} + +[PcdsFixedAtBuild] + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001 + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002 diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/= Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf new file mode 100644 index 000000000000..b92f658bfc46 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf @@ -0,0 +1,40 @@ +# @Ds1307RtcLib.inf +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Ds1307RtcLib + FILE_GUID =3D 7112fb46-8dda-4a41-ac40-bf212fedfc08 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + +[Sources.common] + Ds1307RtcLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiLib + +[Protocols] + gEfiI2cMasterProtocolGuid ## CONSUMES + gDs1307RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES + +[FixedPcd] + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency + +[Depex] + gDs1307RealTimeClockLibI2cMasterProtocolGuid diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim= /Library/Ds1307RtcLib/Ds1307Rtc.h new file mode 100644 index 000000000000..aa5b3583ec7e --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h @@ -0,0 +1,48 @@ +/** Ds1307Rtc.h +* +* Copyright 2017 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef DS1307RTC_H_ +#define DS1307RTC_H_ + +/* + * RTC time register + */ +#define DS1307_SEC_REG_ADDR 0x00 +#define DS1307_MIN_REG_ADDR 0x01 +#define DS1307_HR_REG_ADDR 0x02 +#define DS1307_DAY_REG_ADDR 0x03 +#define DS1307_DATE_REG_ADDR 0x04 +#define DS1307_MON_REG_ADDR 0x05 +#define DS1307_YR_REG_ADDR 0x06 + +#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ + +/* + * RTC control register + */ +#define DS1307_CTL_REG_ADDR 0x07 + +#define START_YEAR 1970 +#define END_YEAR 2070 + +/* + * TIME MASKS + */ +#define MASK_SEC 0x7F +#define MASK_MIN 0x7F +#define MASK_HOUR 0x3F +#define MASK_DAY 0x3F +#define MASK_MONTH 0x1F + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION SetAddressOp; + EFI_I2C_OPERATION GetSetDateTimeOp; +} RTC_I2C_REQUEST; + +#endif // DS1307RTC_H_ diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Ma= xim/Library/Ds1307RtcLib/Ds1307RtcLib.c new file mode 100644 index 000000000000..88dc198ffec8 --- /dev/null +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c @@ -0,0 +1,372 @@ +/** Ds1307RtcLib.c + Implement EFI RealTimeClock via RTC Lib for DS1307 RTC. + + Based on RTC implementation available in + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Ds1307Rtc.h" + +STATIC VOID *mDriverEventRegistration; +STATIC EFI_HANDLE mI2cMasterHandle; +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; + +/** + Read RTC register. + + @param RtcRegAddr Register offset of RTC to be read. + + @retval Register Value read + +**/ + +STATIC +UINT8 +RtcRead ( + IN UINT8 RtcRegAddr + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + UINT8 Val; + + Val =3D 0; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D I2C_FLAG_READ; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr)); + } + + return Val; +} + +/** + Write RTC register. + + @param RtcRegAddr Register offset of RTC to write. + @param Val Value to be written + +**/ + +STATIC +VOID +RtcWrite ( + IN UINT8 RtcRegAddr, + IN UINT8 Val + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + } +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ + +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Second; + UINT8 Minute; + UINT8 Hour; + UINT8 Day; + UINT8 Month; + UINT8 Year; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + Status =3D EFI_SUCCESS; + + Second =3D RtcRead (DS1307_SEC_REG_ADDR); + Minute =3D RtcRead (DS1307_MIN_REG_ADDR); + Hour =3D RtcRead (DS1307_HR_REG_ADDR); + Day =3D RtcRead (DS1307_DATE_REG_ADDR); + Month =3D RtcRead (DS1307_MON_REG_ADDR); + Year =3D RtcRead (DS1307_YR_REG_ADDR); + + if (Second & DS1307_SEC_BIT_CH) { + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n")); + /* clear the CH flag */ + RtcWrite (DS1307_SEC_REG_ADDR, + RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH); + Status =3D EFI_DEVICE_ERROR; + } + + Time->Second =3D BcdToDecimal8 (Second & MASK_SEC); + Time->Minute =3D BcdToDecimal8 (Minute & MASK_MIN); + Time->Hour =3D BcdToDecimal8 (Hour & MASK_HOUR); + Time->Day =3D BcdToDecimal8 (Day & MASK_DAY); + Time->Month =3D BcdToDecimal8 (Month & MASK_MONTH); + + // + // RTC can save year 1970 to 2069 + // On writing Year, save year % 100 + // On Reading reversing the operation e.g. 2012 + // write =3D 12 (2012 % 100) + // read =3D 2012 (12 + 2000) + // + Time->Year =3D BcdToDecimal8 (Year) + + (BcdToDecimal8 (Year) >=3D 70 ? START_YEAR - 70 : END_YEAR = -70); + + return Status; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if (Time->Year < START_YEAR || Time->Year >=3D END_YEAR){ + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n= ")); + return EFI_INVALID_PARAMETER; + } + + RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100)); + RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month)); + RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day)); + RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour)); + RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute)); + RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second)); + + return EFI_SUCCESS; +} + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this + platform. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // The DS1307 does not support setting the alarm + return EFI_UNSUPPORTED; +} + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // The DS1307 does not support setting the alarm + return EFI_UNSUPPORTED; +} + +STATIC +VOID +I2cDriverRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + UINTN BusFrequency; + EFI_HANDLE Handle; + UINTN BufferSize; + + // + // Try to connect the newly registered driver to our handle. + // + do { + BufferSize =3D sizeof (EFI_HANDLE); + Status =3D gBS->LocateHandle (ByRegisterNotify, + &gEfiI2cMasterProtocolGuid, + mDriverEventRegistration, + &BufferSize, + &Handle); + if (EFI_ERROR (Status)) { + if (Status !=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n", + __FUNCTION__, Status)); + } + break; + } + + if (Handle !=3D mI2cMasterHandle) { + continue; + } + + DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__)); + + gBS->CloseEvent (Event); + + Status =3D gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocol= Guid, + (VOID **)&I2cMaster, gImageHandle, NULL, + EFI_OPEN_PROTOCOL_EXCLUSIVE); + ASSERT_EFI_ERROR (Status); + + Status =3D I2cMaster->Reset (I2cMaster); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n", + __FUNCTION__, Status)); + break; + } + + BusFrequency =3D FixedPcdGet16 (PcdI2cBusFrequency); + Status =3D I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\= n", + __FUNCTION__, Status)); + break; + } + + mI2cMaster =3D I2cMaster; + break; + } while (TRUE); + + return; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + + // + // Find the handle that marks the controller + // that will provide the I2C master protocol. + // + BufferSize =3D sizeof (EFI_HANDLE); + Status =3D gBS->LocateHandle ( + ByProtocol, + &gDs1307RealTimeClockLibI2cMasterProtocolGuid, + NULL, + &BufferSize, + &mI2cMasterHandle + ); + ASSERT_EFI_ERROR (Status); + + // + // Register a protocol registration notification callback on the driver + // binding protocol so we can attempt to connect our I2C master to it + // as soon as it appears. + // + EfiCreateProtocolNotifyEvent ( + &gEfiI2cMasterProtocolGuid, + TPL_CALLBACK, + I2cDriverRegistrationEvent, + NULL, + &mDriverEventRegistration); + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51040): https://edk2.groups.io/g/devel/message/51040 Mute This Topic: https://groups.io/mt/61076179/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51041+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51041+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332906; cv=none; d=zoho.com; s=zohoarc; b=MYSNQhO7NT3+HCOM6vd3kqn8exhQlUzmoSYyQ33s7AvxseZCCoSipdiPlFy8sZRzolMOmgliZrwVVM03x/99y0a/t4We9zPQS3IsZBDNfduayUj9MsIw+0RnrgrYyHaPwDGzYKGIO+7of15UPevZ8bIKY2jVGzpGmG040BbGU0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332906; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=QTzD3b0d3LavlN9SuL9ZMYRZzQXtNsOpbydOn4qIJzo=; b=JsebbtcPMSfWCDFvxss+fELftQ7jrTnoRJ+Q4wwoG+/dWOEzQnLqzo8l6FXoHz675mTTcCaDAOqYS5vfHS3x3xY+z3Yp9u20jTtjGftduHc6vVwJgUK7W6x/vvlEZybei9XuY0m7V5OK9lp9FCU5wYzJqf5PXTB459c7QShJTe0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51041+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332906671380.1084642310092; Thu, 21 Nov 2019 02:41:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:46 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web10.22187.1574332904929495279 for ; Thu, 21 Nov 2019 02:41:45 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8BC801A08CD; Thu, 21 Nov 2019 11:41:43 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 38DC01A07B7; Thu, 21 Nov 2019 11:41:43 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 7DE56316; Thu, 21 Nov 2019 16:11:42 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Date: Thu, 21 Nov 2019 21:55:10 +0530 Message-Id: <1574353514-23986-8-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332906; bh=K/zdwI/H58Vcb42bXxD7HW9Tku94bYccTpn+JMmDRRE=; h=Cc:Date:From:Reply-To:Subject:To; b=LipACNyxrzIAoBB5KF/IOB7j7ijZalVcQjUUSerzYZf1eCwrhHrF5HfMnQYfGMXJgTi 40xlr95gzuNMg9cF8MUnJ6CaWH/TbpaVXovvALS/5NQEkXBB4RTQW1dRFnqGtJ4B+s1PP HDrVy+/qMqSQfIuCM5r1zdhGRa84DtnYWr8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add MemoryInitPei Library for NXP platforms. It has changes to get DRAM information from TFA. Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 +++++++ Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 +++++++++++++= +++++++ 2 files changed, 187 insertions(+) diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silic= on/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf new file mode 100644 index 000000000000..806da6d9ab9a --- /dev/null +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright 2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmMemoryInitPeiLib + FILE_GUID =3D 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemoryInitPeiLib|SEC PEIM DXE_DRIVER + +[Sources] + MemoryInitPeiLib.c + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + HobLib + ArmMmuLib + ArmPlatformLib + PcdLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.c new file mode 100644 index 000000000000..9889d5730261 --- /dev/null +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -0,0 +1,139 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* +* Copyright 2019 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + //Note: Because we called PeiServicesInstallPeiMemory() before to call I= nitMmu() the MMU Page Table resides in + // DRAM (even at the top of DRAM as it is the first permanent memor= y allocation) + Status =3D ArmConfigureMmu (MemoryTable, &TranslationTableBase, &Transla= tionTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + EFI_PEI_HOB_POINTERS NextHob; + BOOLEAN Found; + DRAM_INFO DramInfo; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + // + // Ensure MemoryTable[0].Length which is size of DRAM has been set + // by ArmPlatformGetVirtualMemoryMap () + // + ASSERT (MemoryTable[0].Length !=3D 0); + + // + // Now, the permanent memory has been installed, we can call AllocatePag= es() + // + ResourceAttributes =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + if (GetDramBankInfo (&DramInfo)) { + DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); + return EFI_UNSUPPORTED; + } + + while (DramInfo.NumOfDrams--) { + // + // Check if the resource for the main system memory has been declared + // + Found =3D FALSE; + NextHob.Raw =3D GetHobList (); + while ((NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = NextHob.Raw)) !=3D NULL) { + if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) && + (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >=3D NextH= ob.ResourceDescriptor->PhysicalStart) && + (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDes= criptor->ResourceLength <=3D + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo= .DramRegion[DramInfo.NumOfDrams].Size)) + { + Found =3D TRUE; + break; + } + NextHob.Raw =3D GET_NEXT_HOB (NextHob); + } + + if (!Found) { + // Reserved the memory space occupied by the firmware volume + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress, + DramInfo.DramRegion[DramInfo.NumOfDrams].Size + ); + } + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51041): https://edk2.groups.io/g/devel/message/51041 Mute This Topic: https://groups.io/mt/61076180/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51042+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51042+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332907; cv=none; d=zoho.com; s=zohoarc; b=A52pmzLX6liLM2eZas3Emy4zv0HE1j0yUO/W75jjXh2XRl8VLFD5Fj22/LB6G15CTLxMO2Czay3Wi/733QcxPG4OdJrWVtrn5ielknyovI3CXu/JP2+qtQUe6jA3cej8sVSNWwHH4X09LqKyQ4+tgO0daXLLcW3Wg2NyNtO003o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332907; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=JlTmqiPxQNY4s67HeHirl7v7bk8KJ5vIFl6xqbdSdOs=; b=jtmxXelHgf/r3tqfWE/8zMubEpsbdBnJBdihGa1b2uZIG67HKNVIuczeTdLJL0pI6x0aCAB1wE+K2uPZzryXwFx7fejEiLwxWrkuNW0J/2KwslynqjEFChMX709qmMa0iHLFW/CB/eOBJ4mNY59y6Opc3pP6EdjEVEHRE5+IiCw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51042+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332907489255.4231763762424; Thu, 21 Nov 2019 02:41:47 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:47 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web11.22092.1574332906015574916 for ; Thu, 21 Nov 2019 02:41:46 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 974981A07B7; Thu, 21 Nov 2019 11:41:44 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 21C851A0A3D; Thu, 21 Nov 2019 11:41:44 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 2204D341; Thu, 21 Nov 2019 16:11:43 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib Date: Thu, 21 Nov 2019 21:55:11 +0530 Message-Id: <1574353514-23986-9-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332907; bh=qryaYfkjIBbfRxlyamsCPWMR3q+g2nYudp6u5zJWtYw=; h=Cc:Date:From:Reply-To:Subject:To; b=dD6zeCrY2389mRDoVKhv4Jc4nyEZij+VKioxBpRCczA0S/PqF9x0LIgkVrraoh+0cI1 49cnukX0/tJFUDkRhk3x6CvdfyWxJyA7ugrkYJWXDCW7T8SGCYMu8g2ENHeGEq+aDx1nR kT+h4PWdb5bvic4LI78+O6RKwpU46BdxHM0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 55 ++= ++++++ Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c | 98 ++= +++++++++++ Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 144 ++= ++++++++++++++++++ Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S | 31 ++= +++ 4 files changed, 328 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 000000000000..f7ae74afc6ca --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,55 @@ +# @file +# +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# Copyright 2017, 2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + NxpQoriqLsMem.c + ArmPlatformLib.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 000000000000..eac7d4aa4e47 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,98 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +extern VOID SocInit (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit (); + + return EFI_SUCCESS; +} + +ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_I= NFO); + *ArmCoreTable =3D LS1043aMpCoreInfoCTA53x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 000000000000..c6c256da0727 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,144 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017, 2019 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing a Physical-to- + Virtual Memory mapping. This array must be = ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + DRAM_INFO DramInfo; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_V= IRTUAL_MEMORY_MAP_DESCRIPTORS)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + if (GetDramBankInfo (&DramInfo)) { + DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); + return; + } + + + for (Index =3D 0; Index < DramInfo.NumOfDrams; Index++) { + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D DramInfo.DramRegion[Index].= BaseAddress; + VirtualMemoryTable[Index].VirtualBase =3D DramInfo.DramRegion[Index].= BaseAddress; + VirtualMemoryTable[Index].Length =3D DramInfo.DramRegion[Index].= Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; + } + + // CCSR Space + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // For write transactions from core, IFC interface memories = (including IFC SRAM) + // should be configured as device type memory in MMU. + // For write transactions from non-core masters (like system= DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 000000000000..84ee8c9f9700 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,31 @@ +# @file +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright 2017 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) +EL1_OR_EL2(x0) +1: +2: + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51042): https://edk2.groups.io/g/devel/message/51042 Mute This Topic: https://groups.io/mt/61076182/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51043+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51043+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332908; cv=none; d=zoho.com; s=zohoarc; b=Dy1+cO0mQnu/eB6ccFRj41hkYTDu1wFI1oqZczc4kfXlRW9MLgDYKFEj0VUtZlPTNp/c9VM1T6uqTIVQtNzm9uR2i9dMcoa4EIdVtOkfDNQhFmSMJKNUwQQt5sE4gtDoDh5vj8srFKkm7u4KXveGol9bVQbwFuD0GJHXN9PfruA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332908; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=RhAOcyB1aLPZSzFSYvTpf0seONlMjkP9M47LJPfDH+s=; b=R1RnN+JKkBtdwCSaI8FSvONqeWAXLvAbTJOFuU/rinULUJ1DKjp5QBFAVq3UqWfdhBZOn2O+YbndlhIVHgrNh1Krexpd8Iygm/QuZpt7k2E3onVI1e/eZB9A0vaTKBHEitiWJpsnG5tt8yYeVnIZKL8BfNIqxbl2dsi/Q78cSp8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51043+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332908256237.4406000970382; Thu, 21 Nov 2019 02:41:48 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:47 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web11.22093.1574332906445371376 for ; Thu, 21 Nov 2019 02:41:46 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 185671A0AE4; Thu, 21 Nov 2019 11:41:45 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B9CA81A05E5; Thu, 21 Nov 2019 11:41:44 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id BB46F316; Thu, 21 Nov 2019 16:11:43 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board Date: Thu, 21 Nov 2019 21:55:12 +0530 Message-Id: <1574353514-23986-10-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332907; bh=ks4vc8zyKZSJCLdFGfcZjnUY5iKm/bsFDS6txnkbpk8=; h=Cc:Date:From:Reply-To:Subject:To; b=F4+rL71Vsh7MtkHAMy4ItEGLAIO9nkHqOZmh5Lk9DThnTbLFdLjpcu4vpsce/QtS7M4 Y9mWDeER+cP9LBm0kgLiMg9p3J68lGpuriL2SOt2z0jJO7bMxgpB5TZ0mdFZlGix0bDDX WBb2RUGeoEwh0DSE6BMLUfqG8by6G6MbvP8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Platform driver will be used for platform specific work. At present, it populate i2c driver structure with platform specific information and install RTC on i2c. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 52 +++++= ++++ Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 114 +++++= +++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf= b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf new file mode 100644 index 000000000000..d689cf4db58e --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -0,0 +1,52 @@ +## @file +# +# Component description file for LS1043 DXE platform driver. +# +# Copyright 2018-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformDxe + FILE_GUID =3D 21108101-adcd-4123-930e-a2354a554db7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformDxeEntryPoint + +[Sources] + PlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Guids] + gNxpNonDiscoverableI2cMasterGuid + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController + +[Depex] + TRUE diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b= /Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c new file mode 100644 index 000000000000..f89dcdeff3c1 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -0,0 +1,114 @@ +/** @file + LS1043 DXE platform driver. + + Copyright 2018-2019 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc; + UINT8 EndDesc; +} ADDRESS_SPACE_DESCRIPTOR; + +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cControlle= r)]; + +STATIC +EFI_STATUS +RegisterDevice ( + IN EFI_GUID *TypeGuid, + IN ADDRESS_SPACE_DESCRIPTOR *Desc, + OUT EFI_HANDLE *Handle + ) +{ + NON_DISCOVERABLE_DEVICE *Device; + EFI_STATUS Status; + + Device =3D (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device)= ); + if (Device =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Device->Type =3D TypeGuid; + Device->DmaType =3D NonDiscoverableDeviceDmaTypeNonCoherent; + Device->Resources =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc; + + Status =3D gBS->InstallMultipleProtocolInterfaces (Handle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, Device, + NULL); + if (EFI_ERROR (Status)) { + goto FreeDevice; + } + return EFI_SUCCESS; + +FreeDevice: + FreePool (Device); + + return Status; +} + +VOID +PopulateI2cInformation ( + IN VOID + ) +{ + UINT32 Index; + + for (Index =3D 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) { + mI2cDesc[Index].StartDesc.Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + mI2cDesc[Index].StartDesc.Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCR= IPTOR) - 3; + mI2cDesc[Index].StartDesc.ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + mI2cDesc[Index].StartDesc.GenFlag =3D 0; + mI2cDesc[Index].StartDesc.SpecificFlag =3D 0; + mI2cDesc[Index].StartDesc.AddrSpaceGranularity =3D 32; + mI2cDesc[Index].StartDesc.AddrRangeMin =3D FixedPcdGet64 (PcdI2c0BaseA= ddr) + + (Index * FixedPcdGet32 (PcdI2= cSize)); + mI2cDesc[Index].StartDesc.AddrRangeMax =3D mI2cDesc[Index].StartDesc.A= ddrRangeMin + + FixedPcdGet32 (PcdI2cSize) - = 1; + mI2cDesc[Index].StartDesc.AddrTranslationOffset =3D 0; + mI2cDesc[Index].StartDesc.AddrLen =3D FixedPcdGet32 (PcdI2cSize); + + mI2cDesc[Index].EndDesc =3D ACPI_END_TAG_DESCRIPTOR; + } +} + +EFI_STATUS +EFIAPI +PlatformDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + Handle =3D NULL; + + PopulateI2cInformation (); + + Status =3D RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid, + &mI2cDesc[0], &Handle); + ASSERT_EFI_ERROR (Status); + + // + // Install the DS1307 I2C Master protocol on this handle so the RTC driv= er + // can identify it as the I2C master it can invoke directly. + // + Status =3D gBS->InstallProtocolInterface (&Handle, + &gDs1307RealTimeClockLibI2cMasterProtocolGuid, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Date: Thu, 21 Nov 2019 21:55:13 +0530 Message-Id: <1574353514-23986-11-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332908; bh=JpgU9ZYktRFvwklPE8iBIF5IvtMlq4qoAF8UhyXnapM=; h=Cc:Date:From:Reply-To:Subject:To; b=AKpYpBs2KvEq4bKsZU8BsSvQOZvpSK8GCB2qS48a/gG6LJFjmM+NaY6W6tjbYn7ftk7 lh5nW8Y+Qo4p+7IyB9hG+8CqJ8EBKqsRjI58xmdMhIZYAmRp4cNShMuvHZTcgiVeHYDHO 1Rihl06aJXtfgeC49np41RDetp5NrxnjIrY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The firmware device, description and declaration files. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 ++ Silicon/NXP/LS1043A/LS1043A.dec | 16 + Silicon/NXP/NxpQoriqLs.dec | 103 ++++++ Platform/NXP/NxpQoriqLs.dsc.inc | 368 ++++++++++++++++++++ Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 77 ++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 167 +++++++++ Platform/NXP/FVRules.fdf.inc | 93 +++++ 8 files changed, 908 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dec new file mode 100644 index 000000000000..ed56db0222e4 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec @@ -0,0 +1,23 @@ +# LS1043aRdbPkg.dec +# LS1043a board package. +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + PACKAGE_NAME =3D LS1043aRdbPkg + PACKAGE_GUID =3D 6eba6648-d853-4eb3-9761-528b82d5ab04 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.= dec new file mode 100644 index 000000000000..cd79949790f0 --- /dev/null +++ b/Silicon/NXP/LS1043A/LS1043A.dec @@ -0,0 +1,16 @@ +# LS1043A.dec +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + +[Guids.common] + gNxpLs1043ATokenSpaceGuid =3D {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} + +[Includes] + Include diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec new file mode 100644 index 000000000000..764b9bb0e2d3 --- /dev/null +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -0,0 +1,103 @@ +# @file. +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + +[Guids.common] + gNxpQoriqLsTokenSpaceGuid =3D {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} + gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} + +[PcdsFixedAtBuild.common] + # + # Pcds for I2C Controller + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002 + + # + # Pcds for base address and size + # + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100 + gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101 + gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103 + gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104 + gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120 + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123 + + # + # IFC PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194 + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0000= 0196 + + # + # NV Pcd + # + gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210 + gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211 + + # + # Platform PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 + + # + # Clock PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0 + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1 + + # + # Pcds to support Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310 + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311 + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312 + gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314 diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.= inc new file mode 100644 index 000000000000..fa5f30dd3909 --- /dev/null +++ b/Platform/NXP/NxpQoriqLs.dsc.inc @@ -0,0 +1,368 @@ +# @file +# +# Copyright 2017-2019 NXP. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001A + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + # Networking Requirements + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + + # ARM GIC400 General Interrupt Driver + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib= .inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing= Lib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCom= mandLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf + + # 1/123 faster than Stm or Vstm version + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + +[LibraryClasses.common.PEIM] + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf + +[LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + +[BuildOptions] + RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu cortex-a9 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsDynamicDefault.common] + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|10 + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units,= 100,000 x 100 ns =3D 10,000,000 ns =3D 10 ms + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000045 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # Serial Terminal + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # Timer + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 + + # We want to use the Shell Libraries but don't want it to initialise + # automatically. We initialise the libraries when the command is called = by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + # Use the serial console for both ConIn & ConOut + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000 +!ifdef $(NO_SHELL_PROFILES) + gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00 +!endif #$(NO_SHELL_PROFILES) + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # SEC + # + ArmPlatformPkg/PrePi/PeiUniCore.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + # FDT installation + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + FatPkg/FatPei/FatPei.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Example Application + # + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.i= nf + ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + ShellPkg/Application/Shell/Shell.inf { + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf +!ifndef $(NO_SHELL_PROFILES) + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf +!endif #$(NO_SHELL_PROFILES) + } + + ## diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc new file mode 100644 index 000000000000..dbd680b0ad28 --- /dev/null +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -0,0 +1,61 @@ +# LS1043A.dsc +# LS1043A Soc package. +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000 + +[PcdsFixedAtBuild.common] + + # + # CCSR Address Space and other attached Memories + # + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 + gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 + + # + # Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE + +## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc new file mode 100644 index 000000000000..c8105593533f --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -0,0 +1,77 @@ +# LS1043aRdbPkg.dsc +# +# LS1043ARDB Board package. +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS1043aRdbPkg + PLATFORM_GUID =3D 60169ec4-d2b4-44f8-825e-f8684fd42e4f + OUTPUT_DIRECTORY =3D Build/LS1043aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LS1043aRdbPkg/LS1043aRdb= Pkg.fdf + +!include Platform/NXP/NxpQoriqLs.dsc.inc +!include Silicon/NXP/LS1043A/LS1043A.dsc.inc + +[LibraryClasses.common] + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf + RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf + +[PcdsFixedAtBuild.common] + + # + # LS1043a board Specific PCDs + # XX (DRAM - Region 1 2GB) + # (NOR - IFC Region 1 512MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + + # + # Board Specific Pcds + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 + + # + # RTC Pcds + # + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68 + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf + + ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf new file mode 100644 index 000000000000..8d66f36d7407 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -0,0 +1,167 @@ +# LS1043aRdbPkg.fdf +# +# FLASH layout file for LS1043a board. +# +# Copyright (c) 2016, Freescale Ltd. All rights reserved. +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS1043ARDB_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xED000 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x000ED000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include Platform/NXP/FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf + + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/FatPei/FatPei.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc new file mode 100644 index 000000000000..c9fba65dae85 --- /dev/null +++ b/Platform/NXP/FVRules.fdf.inc @@ -0,0 +1,93 @@ +# FvRules.fdf.inc +# +# Rules for creating FD. +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#51045): https://edk2.groups.io/g/devel/message/51045 Mute This Topic: https://groups.io/mt/61076186/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 04:41:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+51044+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51044+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=nxp.com ARC-Seal: i=1; a=rsa-sha256; t=1574332909; cv=none; d=zoho.com; s=zohoarc; b=Pji4mdq5TGGagXF7Fe4Ir0USJZToLkwRz+5oIzfHz5vH9MY1X7SbFCXZZga/C3HVWQebtfO2dCD+2RplIH+D+nghabbDAUxGwNT6kyiRRFe1NmP26FkxbxlsXqfGyqbTc+Bz3V4ZZEccliSxlD7ZM2eT7NAO4gkJEi806//AQCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574332909; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=7k6LqEmHAzl1sL73WkriiKw7lH422r/Uy50i2K8VH9k=; b=JrSs3olBVUxZnaReXZnauuSOYfVf6LlcqcAexM2cyde2mDa3vNJIoP+G02cHRvg0Fxq9jteckj9ylkDbzBZAdrZdWCfawTUB6VYBvDxXwQJ2l+dxkJGx5beYNzLKkHNXHEJOTYcsvdDIqkKyM/hiiX83Q+SrxSkEU3NRPUEio54= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+51044+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1574332909208508.4555581118159; Thu, 21 Nov 2019 02:41:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Thu, 21 Nov 2019 02:41:48 -0800 X-Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by mx.groups.io with SMTP id smtpd.web11.22096.1574332907684656356 for ; Thu, 21 Nov 2019 02:41:48 -0800 X-Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 48B6E1A05E5; Thu, 21 Nov 2019 11:41:46 +0100 (CET) X-Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1945B1A0ADD; Thu, 21 Nov 2019 11:41:46 +0100 (CET) X-Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 10BAA341; Thu, 21 Nov 2019 16:11:45 +0530 (IST) From: "Meenakshi Aggarwal" To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, devel@edk2.groups.io Cc: v.sethi@nxp.com, Meenakshi Aggarwal Subject: [edk2-devel] [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file. Date: Thu, 21 Nov 2019 21:55:14 +0530 Message-Id: <1574353514-23986-12-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com> <1574353514-23986-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,meenakshi.aggarwal@nxp.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1574332908; bh=yyn9YAMPozWjXH0CL0oVgtVlCMHF94tErs9ubzCZEJE=; h=Cc:Date:From:Reply-To:Subject:To; b=AljwCM/Horv3KQrPC7M49nUf0r4h+It4e2oLWKeRDeqYNdAcOlUO8pPDaCAXU5s5PIT z3TO8ej6gAHccpCbyVmWhtQHO9wPUOEvRkGxRA9Tk59MylSECyEzP93kFaFf7n2BSh3LF i1N8KmpI8s/OUtMlvreAagnfw5Bi4pSmZbU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Readme.md to explain how to build NXP board packages. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm --- Platform/NXP/Readme.md | 5 +++++ Readme.md | 3 +++ 2 files changed, 8 insertions(+) diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md new file mode 100644 index 000000000000..2d60d7cb3044 --- /dev/null +++ b/Platform/NXP/Readme.md @@ -0,0 +1,5 @@ +Support for all NXP boards is available in this directory. + +# How to build + +Please follow top-level Readme.md for build instructions.. diff --git a/Readme.md b/Readme.md index 1befd0b5448a..104c33f557e5 100644 --- a/Readme.md +++ b/Readme.md @@ -246,6 +246,9 @@ For more information, see the ## Socionext * [SynQuacer](Platform/Socionext/DeveloperBox) =20 +## NXP +* [LS1043aRdb](Platform/NXP/LS1043aRdbPkg) + # Maintainers =20 See [Maintainers.txt](Maintainers.txt). --=20 1.9.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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