From nobody Mon Feb 9 12:42:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49520+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49520+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1572238359; cv=none; d=zoho.com; s=zohoarc; b=bKCzseQZAY5SL0bNBGEVz/DBVp9CzEJ/jNMwHynJQY5eEVB7WoI24ha0zca/pBecxA+c5stxeOu8LhAqAm8ueysdqSQMUhhcZhS/4t5Nlf9gNrqaX6Y6Ub3m27nfHVDRoqCjVZ+poNhchmTGXtcw5klf/KFJih8w/8RraV1zt98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572238359; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=+5v7mMORvr4vlI48U0R3uQ1gveRFU0yuRQhHbFX4Y2k=; b=ogiWKXrPH76OJvxrnjj/AGbRiVVVFs/ClFPHpM7qP9naFCI/HvZbfwiEX9dLAxTbGeigIEsSJyG2SqZkMo2iEr1xueXjUq6gc7yUCyTXzfkSowhNH4KnqZgOwEOTqgYfOxrTJokZpNnjtlr8P9nFiR/84iUsa2COsAO9b8aCCDM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49520+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572238359154839.7854330789029; Sun, 27 Oct 2019 21:52:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eKBHYY1788612xlGnNJNnq4a; Sun, 27 Oct 2019 21:52:38 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.2397.1572238357649238924 for ; Sun, 27 Oct 2019 21:52:37 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S4pa94012635; Mon, 28 Oct 2019 04:52:37 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvbnuj0ud-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 04:52:36 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 64F105E; Mon, 28 Oct 2019 04:52:36 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 591F548; Mon, 28 Oct 2019 04:52:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Ard Biesheuvel , Leif Lindholm , Gilbert Chen , Palmer Dabbelt Subject: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 04/18] SiFive/U54MC: Initial version of SiFive U54MC Coreplex library. Date: Mon, 28 Oct 2019 12:20:19 +0800 Message-Id: <1572236433-15404-5-git-send-email-abner.chang@hpe.com> In-Reply-To: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> References: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 5oyJgYSZ3NEotAPolpS0X66xx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572238358; bh=XHxsgvJ+DgvCjDW11as5bsWlvKYc4YUDurJyPNsU7oc=; h=Cc:Date:From:Reply-To:Subject:To; b=mdM8OmK1CNBYfmd6OB8tEZnMzK4QWBvsGrKFmcx34M4IfPR4c3XESQ5dd5a4UTBhC/5 Xy2U/aE8Z2ITs0lffuxsBZOpWYSk5GswlibNpOfokc+upf8W8XildD1nFuxQw86JSHluR XJhl0Irj1UjkrDy3lrYIlPOGQZOoafULIjc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SiFive U54MC Coreplex library for building core information hob data. Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Gilbert Chen Cc: Palmer Dabbelt Signed-off-by: Abner Chang --- .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ++++++ .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 55 ++++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 +++++++++++++++++= ++++ 3 files changed, 285 insertions(+) create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= PeiCoreInfoHobLib.inf create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= CoreInfoHob.c diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCore= InfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/Pei= CoreInfoHobLib.inf new file mode 100644 index 0000000..c5f4478 --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHob= Lib.inf @@ -0,0 +1,46 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SiliconSiFiveU54MCCoreplexInfoLib + FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU54MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid + diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon= /SiFive/Include/Library/SiFiveU54MCCoreplex.h new file mode 100644 index 0000000..0e14b28 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h @@ -0,0 +1,55 @@ +/** @file + SiFive U54 Coreplex library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SIFIVE_U54MC_COREPLEX_CORE_H_ +#define SIFIVE_U54MC_COREPLEX_CORE_H_ + +#include + +#include +#include + +#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0 +#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1 +#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2 +#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3 +#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4 + +/** + Build up U54MC coreplex processor core-specific information. + + @param UniqueId U54MC unique ID. + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CreateU54MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr + ); +#endif diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInf= oHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob= .c new file mode 100644 index 0000000..97bed2a --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,184 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include + +/** + Build up processor-specific HOB for U54MC Coreplex + + @param UniqueId Unique ID of this U54MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ThisGuidHobData; + EFI_GUID *ParentProcessorGuid; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + ParentProcessorGuid =3D PcdGetPtr (PcdSiFiveU54MCCoreplexGuid); + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= )); + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCC= oreplexGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DAT= A)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54M= CCoreplexGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D NULL; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex= RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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