From nobody Mon Feb 9 09:22:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49518+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49518+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1572238353; cv=none; d=zoho.com; s=zohoarc; b=NUzNLJSEahg9xhm2QjMhj66Rj2wPSzNnPfUOb6s+dCOsbdPdnC49xxjZ6Q1EfPFDa4wfwEy0qI/gRj8oz07R/4ln+J2u+4PchFAemhcYWtfeTA8slI14miaBY+WqmNvwFxcKAGFBnSCAMSfIsi7LiDXa7MlezS2f9QcZKGuXIbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572238353; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=wytF5AfIJtaiiwOTJncaG3IFqlee1JBundPiJn0g8Y8=; b=lIzorOGM1StXdGJNTlaARvStp6HI1JDMBHWZTuPKerfZXNAgnBr5KEOJOfkpOkQRY0NcRC/tn8T/7Sw1x+b6L6e64uVEfKR+D0zZR3fGFfB7coR4s6uzaKn2GmwRgcSXIF+P12COYBjcu0Zq81mK3ja61N7OrBWxuC6pDcwbR9Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49518+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572238353266932.9524161234325; Sun, 27 Oct 2019 21:52:33 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QjwwYY1788612x4TKQcPGjdE; Sun, 27 Oct 2019 21:52:32 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.2362.1572238352410296440 for ; Sun, 27 Oct 2019 21:52:32 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S4pcOB005241; Mon, 28 Oct 2019 04:52:32 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2vw02aw6xk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 04:52:32 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 6F5F753; Mon, 28 Oct 2019 04:52:31 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 615E548; Mon, 28 Oct 2019 04:52:29 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Ard Biesheuvel , Leif Lindholm , Gilbert Chen , Palmer Dabbelt Subject: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 02/18] SiFive/E51: Initial version of SiFive E51 core library. Date: Mon, 28 Oct 2019 12:20:17 +0800 Message-Id: <1572236433-15404-3-git-send-email-abner.chang@hpe.com> In-Reply-To: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> References: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: xNs4Fnk2g4xegHZbhSsz02WDx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572238352; bh=1Ea1OInOxGj6x0QzgfZV+D77/BWgSRx6dWMTQR+yinI=; h=Cc:Date:From:Reply-To:Subject:To; b=ok11U3ku4Y5f48coBpolZ8XlJBQZXIUNTKYUSKV+yqImu0tywPcerAlJ3Rfit2Q0yXi Flb/i+kYTjFf0akfctzqXNLMBqCVr4ZY1QiCt/X11Ar0PNgP5aUzQWWJh3a7G07+l0V+L HVhct5vQH1k6c42wXzDLPvvzO7qW4Si9PRw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SiFive E51 core library for building core information hob data. Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Gilbert Chen Cc: Palmer Dabbelt Signed-off-by: Abner Chang --- .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ++++ Silicon/SiFive/Include/Library/SiFiveE51.h | 60 +++++ .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++= ++++ 3 files changed, 349 insertions(+) create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 0000000..a065373 --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,47 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SiliconSiFiveE51CoreInfoLib + FILE_GUID =3D 80A59B85-1245-4309-AC58-2CFA4199B46C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveE51CoreInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + RiscVPlatformPkg/RiscVPlatformPkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + FirmwareContextProcessorSpecificLib + MemoryAllocationLib + PcdLib + PrintLib + +[FixedPcd] + gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/In= clude/Library/SiFiveE51.h new file mode 100644 index 0000000..6b58766 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveE51.h @@ -0,0 +1,60 @@ +/** @file + SiFive E51 Core library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SIFIVE_E51_CORE_H_ +#define SIFIVE_E51_CORE_H_ + +#include + +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECI= FIC_HOB_DATA. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr + ); + +#endif diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 0000000..68eabc3 --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,242 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Function to build core specific information HOB. RISC-V SMBIOS DXE drive= r collect + this information and build SMBIOS Type44. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData + ) +{ + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob; + EFI_GUID *ProcessorSpecDataHobGuid; + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob; + struct sbi_scratch *ThisHartSbiScratch; + struct sbi_platform *ThisHartSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + if (GuidHobData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ThisHartSbiScratch =3D sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(= ), (UINT32)HartId); + DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch)= ); + ThisHartSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ThisHart= SbiScratch); + DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatfor= m)); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPla= tform->firmware_context; + DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); + FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; + DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); + + // + // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA. + // + CommonFirmwareContextHartSpecificInfo ( + FirmwareContextHartSpecific, + ParentProcessorGuid, + ParentProcessorUid, + (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid), + HartId, + IsBootHart, + &ProcessorSpecDataHob + ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; + ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; + + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + + // + // Build GUID HOB for E51 core, this is for SMBIOS type 44 + // + ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); + CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_HOB_DATA)); + if (CoreGuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + ASSERT (FALSE); + } + *GuidHobData =3D CoreGuidHob; + return EFI_SUCCESS; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob; + RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Build up SMBIOS type 7 L1 instruction cache record. + // + ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA)); + CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveE51CoreGuid)); + L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; + L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; + L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA)); + if (L1InstCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); + CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veE51CoreGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_TYPE4_HOB_DATA.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D NULL; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_SMBIOS_HOB_DATA.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} + + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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