From nobody Mon Feb 9 09:24:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49502+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49502+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1572229926; cv=none; d=zoho.com; s=zohoarc; b=YPJk6MtKRSKZua3KvjKSKAQ20lsCe+ujzYRTHew2wEVfXEPoawAP0Gts1pV2fGYDxZ7Yfu+6CX5ji+EQpTMBCtGjFqzKx3GgH+Ozk3yo9hvOwlqzc1U3coloDsCICsqrBD73onUNv/8CYbwrY6UIanlvMQlwg2EkePSUM4maIxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572229926; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GWeCuX66RAGYIysW210Aqm4RU44v3N2kE3ahDi/meNw=; b=lu/83WKr34kH5S1bQeHGa71cVHq3BIQjyWn1h/9GFrAGBU58U/haJbxdISEgE/3ASCfvK+IPuklg40/5H0MHe5srZNKMRXgFqodzpShcsrWOEkja1/An4crobBFE198n2IiAr/QEQLvjP1yJF88MNrANuMcp6/E5D0yUw2y71tE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49502+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572229926703487.8805971972382; Sun, 27 Oct 2019 19:32:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OEGhYY1788612xGMyRXiVpas; Sun, 27 Oct 2019 19:32:05 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.570.1572229924860753722 for ; Sun, 27 Oct 2019 19:32:05 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2Vj5U008646; Mon, 28 Oct 2019 02:32:04 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvd90rwym-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:32:03 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 1D10351; Mon, 28 Oct 2019 02:32:03 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id B986045; Mon, 28 Oct 2019 02:32:01 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms. Date: Mon, 28 Oct 2019 09:59:04 +0800 Message-Id: <1572227957-13169-27-git-send-email-abner.chang@hpe.com> In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: yti3vF0hMiGmTJsmUAM69Ho5x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572229925; bh=6pVk/rpRDwUbgbL98/QRqhJ6yXO5EfjcILBYgYWzMz8=; h=Cc:Date:From:Reply-To:Subject:To; b=vMVZfGcZa58wO1ZPI6dyaJi5eNGCnlrZSSi6/7nkvAq2He2R1M+q6IwS0gjCZDsb+cd FZdQ6S3RcQiw+sdittrQSWQxCR56aXlfrVw0oKgNpAIF2EC/+OJPdxa5huiU1FW/YQQr3 PsdV2X+zyF82pjNDeLRff/FB17Qzt/d+HhY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7 and type 44 records. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- RiscVPkg/RiscVPkg.dec | 6 + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 ++++ RiscVPkg/Include/ProcessorSpecificHobData.h | 97 ++++++ RiscVPkg/Include/SmbiosProcessorSpecificData.h | 57 ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 23 ++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 +++++++++++++++++= ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 + .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 + 8 files changed, 602 insertions(+) create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf create mode 100644 RiscVPkg/Include/ProcessorSpecificHobData.h create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec index 3542185..2314698 100644 --- a/RiscVPkg/RiscVPkg.dec +++ b/RiscVPkg/RiscVPkg.dec @@ -23,6 +23,12 @@ gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} =20 [PcdsFixedAtBuild] + # Processor Specific Data GUID HOB GUID + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0= x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2= , 0xFA, 0x93}|VOID*|0x00001000 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0= x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA= , 0x6F}|VOID*|0x00001001 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x= 36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C,= 0x25, 0xB9}|VOID*|0x00001002 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0x= B4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF,= 0x71, 0x65}|VOID*|0x00001003 + # # 1000000000 # PcdRiscVMachineTimerTickInNanoSecond =3D -----------------------------= ---------- diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.inf new file mode 100644 index 0000000..7a3c517 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf @@ -0,0 +1,55 @@ +## @file +# RISC-V SMBIOS DXE module. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSmbiosDxe + MODULE_UNI_FILE =3D RiscVSmbiosDxe.uni + FILE_GUID =3D 5FC01647-AADD-42E1-AD99-DF4CB89F5A92 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D RiscVSmbiosBuilderEntry + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + HobLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Sources] + RiscVSmbiosDxe.c + RiscVSmbiosDxe.h + +[Protocols] + gEfiSmbiosProtocolGuid # Consumed + +[Guids] + + +[Pcd] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + +[Depex] + gEfiSmbiosProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include= /ProcessorSpecificHobData.h new file mode 100644 index 0000000..c19f355 --- /dev/null +++ b/RiscVPkg/Include/ProcessorSpecificHobData.h @@ -0,0 +1,97 @@ +/** @file + Definition of Processor Specific Data HOB. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_ +#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_ + +#include +#include +#include + +#define TO_BE_FILLED 0 +#define TO_BE_FILLED_BY_VENDOR 0 +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 +#define TO_BE_FILLED_BY_CODE 0 + +#pragma pack(1) + +/// +/// RISC-V processor specific data HOB +/// +typedef struct { + EFI_GUID ParentPrcessorGuid; + UINTN ParentProcessorUid; + EFI_GUID CoreGuid; + VOID *Context; // The additional information of this core whi= ch + // built in PEI phase and carried to DXE phase. + // The content is pocessor or platform specifi= c. + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; +} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA; + +/// +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE4 SmbiosType4Processor; + UINT16 EndingZero; +} RISC_V_PROCESSOR_TYPE4_HOB_DATA; + +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF + +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03 + +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3 +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIG= URATION_SOCKET_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_= CONFIGURATION_SOCKET_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5 +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONF= IGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7 +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_= CONFIGURATION_ENABLE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACH= E_CONFIGURATION_ENABLE_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8 +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE7 SmbiosType7Cache; + UINT16 EndingZero; +} RISC_V_PROCESSOR_TYPE7_HOB_DATA; + +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCache; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCache; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache; +} RISC_V_PROCESSOR_SMBIOS_HOB_DATA; + +#pragma pack() + +#endif diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Incl= ude/SmbiosProcessorSpecificData.h new file mode 100644 index 0000000..81e48cd --- /dev/null +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h @@ -0,0 +1,57 @@ +/** @file + Industry Standard Definitions of RISC-V Processor Specific data defined = in + below link for complaiant with SMBIOS Table Specification v3.3.0. + https://github.com/riscv/riscv-smbios + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_ +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_ + +#include +#include + +#pragma pack(1) + +typedef enum{ + RegisterUnsupported =3D 0x00, + RegisterLen32 =3D 0x01, + RegisterLen64 =3D 0x02, + RegisterLen128 =3D 0x03 +} RISC_V_REGISTER_LENGTH; + +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100 + +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0) +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2) +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3) +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7) + +/// +/// RISC-V processor specific data for SMBIOS type 44 +/// +typedef struct { + UINT16 Revision; + UINT8 Length; + RISCV_UINT128 HartId; + UINT8 BootHartId; + RISCV_UINT128 MachineVendorId; + RISCV_UINT128 MachineArchId; + RISCV_UINT128 MachineImplId; + UINT32 InstSetSupported; + UINT8 PrivilegeModeSupported; + RISCV_UINT128 MModeExcepDelegation; + RISCV_UINT128 MModeInterruptDelegation; + UINT8 HartXlen; + UINT8 MachineModeXlen; + UINT8 Reserved; + UINT8 SupervisorModeXlen; + UINT8 UserModeXlen; +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA; + +#pragma pack() +#endif + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.h new file mode 100644 index 0000000..1072877 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h @@ -0,0 +1,23 @@ +/** @file + RISC-V SMBIOS Builder DXE module header file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISC_V_SMBIOS_DXE_H_ +#define RISC_V_SMBIOS_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.c new file mode 100644 index 0000000..90cbeea --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -0,0 +1,339 @@ +/** @file + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and t= ype 44 records. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "RiscVSmbiosDxe.h" + +#define RISCV_SMBIOS_DEBUG_INFO 1 + +STATIC EFI_SMBIOS_PROTOCOL *mSmbios; + +/** + This function builds SMBIOS type 7 record according to + the given RISC_V_PROCESSOR_TYPE7_HOB_DATA. + + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA + @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_HOB_DATA + @param SmbiosHandle Pointer to SMBIOS_HANDLE + + @retval EFI_STATUS + +**/ +STATIC +EFI_STATUS +BuildSmbiosType7 ( + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData, + IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob, + OUT SMBIOS_HANDLE *SmbiosHandle +) +{ + EFI_STATUS Status; + SMBIOS_HANDLE Handle; + + if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGu= id) || + Type4HobData->ProcessorUid !=3D Type7DataHob->ProcessorUid) { + return EFI_INVALID_PARAMETER; + } + Handle =3D SMBIOS_HANDLE_PI_RESERVED; + Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMATIO= N; + Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE7); + Type7DataHob->SmbiosType7Cache.Hdr.Handle =3D 0; + Type7DataHob->EndingZero =3D 0; + Status =3D mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosTy= pe7Cache.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__)); + return Status; + } + DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Ha= ndle)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Cache belone to processor GUID: %g\n", &Type7D= ataHob->PrcessorGuid)); + DEBUG ((DEBUG_INFO, " Cache belone processor UID: %d\n", Type7DataH= ob->ProcessorUid)); + DEBUG ((DEBUG_INFO, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((DEBUG_INFO, " Socket Designation: %d\n", Type7DataHob->Smbio= sType7Cache.SocketDesignation)); + DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\n", Type7DataHob->Sm= biosType7Cache.CacheConfiguration)); + DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n", Type7DataHob->Smb= iosType7Cache.MaximumCacheSize)); + DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n", Type7DataHob->SmbiosT= ype7Cache.InstalledSize)); + DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\n", Type7DataHob->Sm= biosType7Cache.SupportedSRAMType)); + DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n", Type7DataHob->Smbi= osType7Cache.CurrentSRAMType)); + DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType= 7Cache.CacheSpeed)); + DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%x\n", Type7DataHob->= SmbiosType7Cache.ErrorCorrectionType)); + DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n", Type7DataHob->Smbi= osType7Cache.SystemCacheType)); + DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n", Type7DataHob->SmbiosTy= pe7Cache.Associativity)); +#endif + + *SmbiosHandle =3D Handle; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 4 record according to + the given RISC_V_PROCESSOR_TYPE4_HOB_DATA. + + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA + @param SmbiosHandle Pointer to SMBIOS_HANDLE + + @retval EFI_STATUS + +**/ +STATIC +EFI_STATUS +BuildSmbiosType4 ( + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData, + OUT SMBIOS_HANDLE *SmbiosHandle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData; + SMBIOS_HANDLE Cache; + SMBIOS_HANDLE Processor; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Building Type 4.\n")); + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorG= uid)); + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorU= id)); + + Type4HobData->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4HobData->SmbiosType4Processor.L2CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4HobData->SmbiosType4Processor.L3CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType7GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n")); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs. + // + do { + Type7HobData =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA = (GuidHob); + Status =3D BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache); + if (EFI_ERROR (Status)) { + return Status; + } + if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CON= FIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) { + Type4HobData->SmbiosType4Processor.L1CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) { + Type4HobData->SmbiosType4Processor.L2CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) { + Type4HobData->SmbiosType4Processor.L3CacheHandle =3D Cache; + } else { + DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", C= ache)); + } + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e7GuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + + // + // Build SMBIOS Type 4 record + // + Processor =3D SMBIOS_HANDLE_PI_RESERVED; + Type4HobData->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_IN= FORMATION; + Type4HobData->SmbiosType4Processor.Hdr.Length =3D sizeof(SMBIOS_TABLE_TY= PE4); + Type4HobData->SmbiosType4Processor.Hdr.Handle =3D 0; + Type4HobData->EndingZero =3D 0; + Status =3D mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->Smbio= sType4Processor.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n")); + return Status; + } + DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Pr= ocessor)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Socket StringID: %d\n", Type4HobData->SmbiosTy= pe4Processor.Socket)); + DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n", Type4HobData->SmbiosT= ype4Processor.ProcessorType)); + DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n", Type4HobData->Smbio= sType4Processor.ProcessorFamily)); + DEBUG ((DEBUG_INFO, " Processor Manufacture StringID: %d\n", Type4Ho= bData->SmbiosType4Processor.ProcessorManufacture)); + DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n", \ + Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4H= obData->SmbiosType4Processor.ProcessorId.FeatureFlags)); + DEBUG ((DEBUG_INFO, " Processor Version StringID: %d\n", Type4HobDat= a->SmbiosType4Processor.ProcessorVersion)); + DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4HobData->SmbiosType4Pro= cessor.Voltage)); + DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n", Type4HobData->SmbiosT= ype4Processor.ExternalClock)); + DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n", Type4HobData->SmbiosType4P= rocessor.MaxSpeed)); + DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n", Type4HobData->SmbiosTy= pe4Processor.CurrentSpeed)); + DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4HobData->SmbiosType4Proc= essor.Status)); + DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n", Type4HobData->Smbio= sType4Processor.ProcessorUpgrade)); + DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n", Type4HobData->Smbios= Type4Processor.L1CacheHandle)); + DEBUG ((DEBUG_INFO, " L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosT= ype4Processor.L2CacheHandle)); + DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n", Type4HobData->Smbios= Type4Processor.L3CacheHandle)); + DEBUG ((DEBUG_INFO, " Serial Number StringID: %d\n", Type4HobData->S= mbiosType4Processor.SerialNumber)); + DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n", Type4HobData->Smbio= sType4Processor.AssetTag)); + DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n", Type4HobData->Smb= iosType4Processor.PartNumber)); + DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4HobData->SmbiosType4Pr= ocessor.CoreCount)); + DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n", Type4HobData->Smbios= Type4Processor.EnabledCoreCount)); + DEBUG ((DEBUG_INFO, " Thread Count: %d\n", Type4HobData->SmbiosType4= Processor.ThreadCount)); + DEBUG ((DEBUG_INFO, " Processor Characteristics: 0x%x\n", Type4HobDa= ta->SmbiosType4Processor.ProcessorCharacteristics)); + DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n", Type4HobData->Smbi= osType4Processor.ProcessorFamily2)); + DEBUG ((DEBUG_INFO, " Core Count 2: %d\n", Type4HobData->SmbiosType4= Processor.CoreCount2)); + DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n", Type4HobData->Smbio= sType4Processor.EnabledCoreCount2)); + DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n", Type4HobData->SmbiosTyp= e4Processor.ThreadCount2)); +#endif + + *SmbiosHandle =3D Processor; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 44 record according.. + + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA + @param Type4Handle SMBIOS handle of type 4 + + @retval EFI_STATUS + +**/ +EFI_STATUS +BuildSmbiosType44 ( + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData, + IN SMBIOS_HANDLE Type4Handle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData; + SMBIOS_HANDLE RiscVType44; + SMBIOS_TABLE_TYPE44 *Type44Ptr; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Building Type 44 for...\n")); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->Prcessor= Guid)); + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->Processor= Uid)); +#endif + + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n")= ); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores. + // + do { + ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GU= ID_HOB_DATA (GuidHob); + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4Ho= bData->PrcessorGuid) || + ProcessorSpecificData->ParentProcessorUid !=3D Type4HobData->Process= orUid) { + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + if (GuidHob =3D=3D NULL) { + break; + } + continue; + } + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((DEBUG_INFO, "Core GUID: %g\n", &ProcessorSpecificData->CoreGui= d)); +#endif + + Type44Ptr =3D AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SM= BIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero. + if (Type44Ptr =3D=3D NULL) { + return EFI_NOT_FOUND; + } + Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION; + Type44Ptr->Hdr.Handle =3D 0; + Type44Ptr->Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA); + Type44Ptr->RefHandle =3D Type4Handle; + Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof(SMBIOS_RISC_V_PROC= ESSOR_SPECIFIC_DATA); + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =3D Type4HobData->= SmbiosType4Processor.ProcessorFamily2 - + ProcessorFamilyR= iscvRV32 + \ + ProcessorSpecifi= cBlockArchTypeRiscVRV32; + CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->Proc= essorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA)); + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, "Core type: %d\n", Type44Ptr->ProcessorSpecificBlo= ck.ProcessorArchType)); + DEBUG ((DEBUG_INFO, " HartId =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSO= R_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " Is Boot Hart? =3D 0x%x\n", ((SMBIOS_RISC_V_P= ROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId)); + DEBUG ((DEBUG_INFO, " PrivilegeModeSupported =3D 0x%x\n", ((SMBIOS= _RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported)= ); + DEBUG ((DEBUG_INFO, " MModeExcepDelegation =3D 0x%x\n", ((SMBIOS_R= ISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Valu= e64_L)); + DEBUG ((DEBUG_INFO, " MModeInterruptDelegation =3D 0x%x\n", ((SMBI= OS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegat= ion.Value64_L)); + DEBUG ((DEBUG_INFO, " HartXlen =3D 0x%x\n", ((SMBIOS_RISC_V_PROCES= SOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen)); + DEBUG ((DEBUG_INFO, " MachineModeXlen =3D 0x%x\n", ((SMBIOS_RISC_V= _PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen)); + DEBUG ((DEBUG_INFO, " SupervisorModeXlen =3D 0x%x\n", ((SMBIOS_RIS= C_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " UserModeXlen =3D 0x%x\n", ((SMBIOS_RISC_V_PR= OCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen)); + DEBUG ((DEBUG_INFO, " InstSetSupported =3D 0x%x\n", ((SMBIOS_RISC_= V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported)); + DEBUG ((DEBUG_INFO, " MachineVendorId =3D 0x%x\n", ((SMBIOS_RISC_V= _PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " MachineArchId =3D 0x%x\n", ((SMBIOS_RISC_V_P= ROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " MachineImplId =3D 0x%x\n", ((SMBIOS_RISC_V_P= ROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L)); +#endif + + // + // Add to SMBIOS table. + // + RiscVType44 =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n")); + return Status; + } + DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n",= RiscVType44)); + + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificD= ataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + return EFI_SUCCESS; +} + +/** + Entry point of RISC-V SMBIOS builder. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +RiscVSmbiosBuilderEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData; + SMBIOS_HANDLE Processor; + + DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__)); + + Status =3D gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&mSmbios + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n")); + return Status; + } + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType4GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n")); + return EFI_NOT_FOUND; + } + Type4HobData =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (G= uidHob); + Status =3D EFI_NOT_FOUND; + // + // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs. + // + do { + Status =3D BuildSmbiosType4 (Type4HobData, &Processor); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n")); + ASSERT (FALSE); + } + Status =3D BuildSmbiosType44 (Type4HobData, Processor); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n")); + ASSERT (FALSE); + } + + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e4GuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__)); + return Status; +} + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.uni new file mode 100644 index 0000000..1bffe09 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni @@ -0,0 +1,12 @@ +// /** @file +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor = SMBIOS Builder" + +#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Proc= essor SMBIOS Type 4, 7, 44 records." + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPk= g/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni new file mode 100644 index 0000000..4b37ca2 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni @@ -0,0 +1,13 @@ +// /** @file +// RISC-V SMBIOS Builder Localized Strings and Content +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"RISC-V SMBIOS Record Builder DXE Driver" + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49502): https://edk2.groups.io/g/devel/message/49502 Mute This Topic: https://groups.io/mt/38757542/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-