From nobody Mon Feb 9 21:02:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49479+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49479+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1572229909; cv=none; d=zoho.com; s=zohoarc; b=fUVXdTju7rEECuBKK4hz5C1mRxZTDDwrCsf+/PVPFZKiRn6mKcP51m0vOg6V41hFnXFSOVX3mBTmKZsP78+H6/nZ9Lq7xs/l5dABPrfiyGjM7+NnvkSTaBTBALG80fZPas43YUmHZaUkUkmp7dVxI27cHd/47nwFTAQlRYNRqDI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572229909; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=IxdJM+PpeJM1z15cnBvyRkSgQBEANVquEY63QkRccmw=; b=jift5ah0o32B5r8X0BfGUNDqgEGiGav5R7bxNMC6Sw1dadugjSuhnTZZ7q32Pp3k5PE1vMLDIob6XIFFmPuJfxVN3qsVyC8R9Cpm8HlxNJxxm+yRe6lgar9OGtit0N30ky/b62xs0RmpxH/x7Rgq2jxgWtST5pWF9b6tcnQYjHY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49479+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572229909326261.9102338664802; Sun, 27 Oct 2019 19:31:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id brJNYY1788612xo9fqxcPbzd; Sun, 27 Oct 2019 19:31:48 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.555.1572229908045395726 for ; Sun, 27 Oct 2019 19:31:48 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2Vlhk004922; Mon, 28 Oct 2019 02:31:47 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvbh619mm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:47 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 47787BE; Mon, 28 Oct 2019 02:31:42 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id E59C347; Mon, 28 Oct 2019 02:31:40 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library Date: Mon, 28 Oct 2019 09:58:53 +0800 Message-Id: <1572227957-13169-16-git-send-email-abner.chang@hpe.com> In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: smZWe3xy5THzceKVqxujc9lrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572229908; bh=MSglQ5BFR9nT8a75mAnGcMWhAW2e5iYNdlvWLNEtXew=; h=Cc:Date:From:Reply-To:Subject:To; b=hSOif5qfgbf6WkrR9uQVgZJwWaYDiXfzYGV+zE5vlpmbnVZE2ajVkaAOAPX9FLrzfor lgQBiNtMFSX8Kz60i7tQtWyfkEY226HU+/QAvdp71wlXGBaD/g+tdzGWc9LPUF/dql3un DM0B78LOoCrOp2MbIVoaxdqcdWaqylTu+Cw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This library provides CSR assembly functions to read/write RISC-V specific Control and Status registers. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++ RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++ RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 +++++++++++++++++++++++= ++++ 3 files changed, 217 insertions(+) create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Librar= y/RiscVCpuLib/RiscVCpuLib.inf new file mode 100644 index 0000000..fc9131b --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -0,0 +1,34 @@ +## @file +# RISC-V RV64 CPU library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVCpuLib + FILE_GUID =3D 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVCpuLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + +[Sources.RISCV64] + Cpu.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Libr= ary/RiscVCpuLib.h new file mode 100644 index 0000000..58c763a --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h @@ -0,0 +1,68 @@ +/** @file + RISC-V CPU library definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISCV_CPU_LIB_H_ +#define RISCV_CPU_LIB_H_ + +#include "RiscVImpl.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext); + +UINT32 +RiscVGetScratch (VOID); + +UINT32 +RiscVGetTrapCause (VOID); + +UINT64 +RiscVReadMachineTimer (VOID); + +VOID +RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp(VOID); + +UINT64 +RiscVReadMachineIE(VOID); + +UINT64 +RiscVReadMachineIP(VOID); + +UINT64 +RiscVReadMachineStatus(VOID); + +VOID +RiscVWriteMachineStatus(UINT64); + +UINT64 +RiscVReadMachineTvec(VOID); + +UINT64 +RiscVReadMisa (VOID); + +UINT64 +RiscVReadMVendorId (VOID); + +UINT64 +RiscVReadMArchId (VOID); + +UINT64 +RiscVReadMImplId (VOID); + +#endif diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpu= Lib/Cpu.S new file mode 100644 index 0000000..2b68b9d --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V CPU functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVSetScratch) +.global ASM_PFX(RiscVGetScratch) +.global ASM_PFX(RiscVGetMachineTrapCause) +.global ASM_PFX(RiscVReadMachineIE) +.global ASM_PFX(RiscVReadMachineIP) +.global ASM_PFX(RiscVReadMachineStatus) +.global ASM_PFX(RiscVWriteMachineStatus) +.global ASM_PFX(RiscVReadMachineTvec) +.global ASM_PFX(RiscVReadMisa) +.global ASM_PFX(RiscVReadMVendorId) +.global ASM_PFX(RiscVReadMArchId) +.global ASM_PFX(RiscVReadMImplId) +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVSetScratch): + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVGetScratch): + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_PFX (RiscVGetMachineTrapCause): + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_PFX (RiscVReadMachineIE): + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_PFX (RiscVReadMachineIP): + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_PFX(RiscVReadMachineStatus): + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_PFX(RiscVWriteMachineStatus): + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_PFX(RiscVReadMachineTvec): + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_PFX(RiscVReadMisa): + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_PFX(RiscVReadMVendorId): + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_PFX(RiscVReadMArchId): + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_PFX(RiscVReadMImplId): + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49479): https://edk2.groups.io/g/devel/message/49479 Mute This Topic: https://groups.io/mt/38757495/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-