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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:32 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information Date: Thu, 10 Oct 2019 07:42:14 +0200 Message-Id: <1570686139-25182-5-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686155; bh=kZUatF5JpERfrHLewMmQ3kaCpKR1RFX7FGOjbGhTlwc=; h=Cc:Date:From:Reply-To:Subject:To; b=CyrrdrA9hj75rlEwWHQL1O0OOZ+R7k6NKUKHP5vm8Gw57rw0AR3u4BjBtMIiPHnbP0d jKZjECrqEz1L37iiw1My0P/95/Skix68DyqAw5gxg4pwLJ0JR0qDp/6n97I5ucdI3iYLn YIv4lb2GOQm128LL/7eZqIzld8pn9PGSlec= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hitherto SoC description and MppLib libraries code assumed that there could be only two Xenon SdMmc controller instances in the SoC. Remove those limitations, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas Acked-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 5 +-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 34 +++++++++++++------- Silicon/Marvell/Library/MppLib/MppLib.c = | 4 +-- 3 files changed, 26 insertions(+), 17 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 0296d43..265b4f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -90,8 +90,9 @@ // // Platform description of SDMMC controllers // -#define MV_SOC_MAX_SDMMC_COUNT 2 -#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) +#define MV_SOC_SDMMC_PER_CP_COUNT 1 +#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000 +#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000) =20 // // Platform description of UTMI PHY's diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 5947601..3ffd57e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -349,26 +349,36 @@ EFI_STATUS EFIAPI ArmadaSoCDescSdMmcGet ( IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, - IN OUT UINTN *DescCount + IN OUT UINTN *Count ) { - MV_SOC_SDMMC_DESC *Desc; - UINTN Index; + MV_SOC_SDMMC_DESC *SdMmc; + UINTN CpCount, CpIndex; =20 - Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); - if (Desc =3D=3D NULL) { + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT; + SdMmc =3D AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC)); + if (SdMmc =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); return EFI_OUT_OF_RESOURCES; } =20 - for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { - Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); - Desc[Index].SdMmcMemSize =3D SIZE_1KB; - Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; - } + *SdMmcDesc =3D SdMmc; + + /* AP80x controller */ + SdMmc->SdMmcBaseAddress =3D MV_SOC_AP80X_SDMMC_BASE; + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; =20 - *SdMmcDesc =3D Desc; - *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + /* CP11x controllers */ + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + SdMmc->SdMmcBaseAddress =3D MV_SOC_CP_SDMMC_BASE (CpIndex); + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; + } =20 return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Libr= ary/MppLib/MppLib.c index 40d9077..f20668d 100644 --- a/Silicon/Marvell/Library/MppLib/MppLib.c +++ b/Silicon/Marvell/Library/MppLib/MppLib.c @@ -139,11 +139,9 @@ SetSdMmcPhyMpp ( case 0: Offset =3D SD_MMC_PHY_AP_MPP_OFFSET; break; - case 1: + default: Offset =3D SD_MMC_PHY_CP0_MPP_OFFSET; break; - default: - return; } =20 /* --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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