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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:28 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/9] Marvell/Armada7k8k: Fix 32-bit compilation Date: Thu, 10 Oct 2019 07:42:11 +0200 Message-Id: <1570686139-25182-2-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686152; bh=EMNoThU4jdqbPPGMcWyZ/4Zyc7RUyfbLkxrX01f6cPA=; h=Cc:Date:From:Reply-To:Subject:To; b=u2u3DUVgGjO3M6ouLd/2hKNrc1GaIjW9CGoaClN7djr40nlfcuQE+Ky3nVjqZWTzr8T vI223qC2TYkHbxnwWMoQx9SzsXDfFHOjjbw2FIffN8//IRhwGW/V8wnlUadMlN3WWetoV SRB1eQYNhiEDcR6spMWB4FqyGsGLnK0Dq24= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It turned out, that the recently added features broke ARM compilation. Fix all issues: * Update signatures types in structures (UINTN -> UINT64) * Use fixed type for address in ICU * Limit memory for ARM build to 1GB and stop using non-existent PCD Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h |= 2 +- Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h |= 2 +- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h |= 4 ++-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c |= 8 ++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S |= 11 ----------- 5 files changed, 12 insertions(+), 15 deletions(-) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.h index a6f551b..3b5a28c 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 typedef struct { MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; - UINTN Signature; + UINT64 Signature; EFI_HANDLE Handle; EFI_LOCK Lock; } MV_BOARD_DESC; diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h b/Silicon/M= arvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h index 1cb006a..ce683e7 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h @@ -36,7 +36,7 @@ typedef struct { EMBEDDED_GPIO GpioProtocol; GPIO_CONTROLLER *SoCGpio; UINTN GpioDeviceCount; - UINTN Signature; + UINT64 Signature; EFI_HANDLE Handle; } MV_GPIO; =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 6432916..da7a41e 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -109,8 +109,8 @@ typedef enum { =20 typedef struct { ICU_GROUP Group; - UINTN SetSpiAddr; - UINTN ClrSpiAddr; + EFI_PHYSICAL_ADDRESS SetSpiAddr; + EFI_PHYSICAL_ADDRESS ClrSpiAddr; } ICU_MSI; =20 typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index a735fe5..cc19694 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -36,6 +36,7 @@ GetDramSize ( IN OUT UINT64 *MemSize ) { +#if defined(MDE_CPU_AARCH64) ARM_SMC_ARGS SmcRegs =3D {0}; EFI_STATUS Status; =20 @@ -48,6 +49,13 @@ GetDramSize ( ArmCallSmc (&SmcRegs); =20 *MemSize =3D SmcRegs.Arg0; +#else + // + // Use fixed value, as currently there is no support + // in Armada early firmware for 32-bit SMC + // + *MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); +#endif =20 return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatfo= rmHelper.S b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatfo= rmHelper.S index 4416163..db43b0f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelpe= r.S +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelpe= r.S @@ -28,17 +28,6 @@ ASM_FUNC(ArmPlatformPeiBootAction) .err PcdSystemMemoryBase should be 0x0 on this platform! .endif =20 - .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapT= arget) - // - // Use the low range for UEFI itself. The remaining memory will be map= ped - // and added to the GCD map later. - // - ADRL (r0, mSystemMemoryEnd) - MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) - mov r3, #0 - strd r2, r3, [r0] - .endif - bx lr =20 //UINTN --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48695): https://edk2.groups.io/g/devel/message/48695 Mute This Topic: https://groups.io/mt/34471897/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48696+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48696+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686155; cv=none; d=zoho.com; s=zohoarc; b=d26abGPvw6zrqU9Ju5TVJINCRBvfJuYmtsDYl2wy4af6XMssH8H5DmWLHuMKxoi/res/Nbgw1iRBCEDFUx6Eo2mn6yWtw/kE+C8UAhvdE3KWh7Td8mWwxrQZT/wkfHeuwk+kn3jTb30WbFhO+OiC3uvDLYiNmME6HJXFyTIJL54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686155; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ABEDjzNSaw4RT3ywqjR1MiqAOYFHyfglYDi3uSzU66I=; b=F6dIlHCKN1v43X7UipCbnr9qSJbb6nfwkaB/qb21epRQqDT7/vbvP7D/VA2PbuMHTg+NQKFK8hyg8izaHsDDnafHJ5Qi9r3Gi7E8UfLLUwELhd8xT1aXJu1Igy5mIxi+mcKrzCODDMOFtDHrAYk28PY3dJmIvDgCGGdPfrPNgPQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48696+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686155332757.0306441115208; Wed, 9 Oct 2019 22:42:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:34 -0700 X-Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by mx.groups.io with SMTP id smtpd.web11.2579.1570686153109619619 for ; Wed, 09 Oct 2019 22:42:33 -0700 X-Received: by mail-lj1-f194.google.com with SMTP id d1so4803037ljl.13 for ; Wed, 09 Oct 2019 22:42:32 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqwLyaDk7XmCO40s4f/VKF3A8CVf52NyM09RMIhpvLdNPR26o38qXl/cQr3ukGj6qQ0uZT9BZQ== X-Received: by 2002:a05:651c:1b9:: with SMTP id c25mr4762444ljn.163.1570686150468; Wed, 09 Oct 2019 22:42:30 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:29 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 2/9] Marvell/Cn9130Db: Add ACPI tables Date: Thu, 10 Oct 2019 07:42:12 +0200 Message-Id: <1570686139-25182-3-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686154; bh=c/CODcIgHo4G8KdOD3ehOTW1f8KgwWkkpYVlr79hSww=; h=Cc:Date:From:Reply-To:Subject:To; b=JArLK0WSItr4H0KNVLjW/lJKz8CY4Qx6r6B7aJztAdnuinrAq35sMKSmfNUnelv3VYN 8hC+1CxElo7vbZfpNSh4r913Knuc8iCIOceZc7T2E8g0Zpbn2pmMIcX19/iUoq6Z3gx10 tfNyViQPsuqsNaYtCJnVH+E3B2shsvKD4Mo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds ACPI tables and necessary headers, which are common for Cn913x SoCs and the CN9130 development board (variant A). Wiring up of support will be done in the follow-up commits. Signed-off-by: Marcin Wojtas Acked-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 37 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++= ++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 ++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 ++++++++= +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 +++ 11 files changed, 1046 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.= asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.= aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf new file mode 100644 index 0000000..191a747 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -0,0 +1,56 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9130 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h new file mode 100644 index 0000000..b5fd397 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -0,0 +1,37 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} +#define ACPI_OEM_REVISION 0 +#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define ACPI_CREATOR_REVISION 0 + +#if defined(CN9130) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#endif + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define __ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h b/Sil= icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h new file mode 100644 index 0000000..634bd8d --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h @@ -0,0 +1,20 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x10000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xDFF00000 +#define PCI_ECAM_BASE 0xD0008000 +#define PCI_ECAM_SIZE 0x10000000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h new file mode 100644 index 0000000..6befe2a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -0,0 +1,36 @@ +/** + + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Glossary - abbreviations used in Marvell SampleAtReset library implement= ation: + ICU - Interrupt Consolidation Unit + AP - Application Processor hardware block (CN913x incorporates AP807) + CP - South Bridge hardware blocks (CN913x incorporates CP115) + +**/ + +#define CP_GIC_SPI_CP0_PCI0 64 +#define CP_GIC_SPI_CP0_PCI1 65 +#define CP_GIC_SPI_CP0_PCI2 66 +#define CP_GIC_SPI_CP0_SDMMC 67 +#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 +#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 +#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 +#define CP_GIC_SPI_CP0_EIP_RNG0 105 +#define CP_GIC_SPI_CP0_USB_H1 112 +#define CP_GIC_SPI_CP0_USB_H0 113 +#define CP_GIC_SPI_CP0_SATA_H0 114 + +#define CP_GIC_SPI_CP1_PCI0 288 +#define CP_GIC_SPI_CP1_PCI1 289 +#define CP_GIC_SPI_CP1_PCI2 290 +#define CP_GIC_SPI_CP1_SDMMC 291 +#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 +#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 +#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 +#define CP_GIC_SPI_CP1_EIP_RNG0 329 +#define CP_GIC_SPI_CP1_USB_H1 336 +#define CP_GIC_SPI_CP1_USB_H0 337 +#define CP_GIC_SPI_CP1_SATA_H0 338 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl new file mode 100644 index 0000000..3dcf78a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -0,0 +1,324 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xDbA/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (COM1) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xCFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + PCI_ECAM_SIZE + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc b/= Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc new file mode 100644 index 0000000..88f59ab --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc @@ -0,0 +1,41 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" +#include "Cn913xDbA/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Fadt.aslc new file mode 100644 index 0000000..ea396bd --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc @@ -0,0 +1,80 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \ + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_6_0_HEADLESS + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepStatusReg +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Gtdt.aslc new file mode 100644 index 0000000..46bfe37 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc @@ -0,0 +1,58 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +// active low, level triggered +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILI= TY + +// active high, level triggered +#define GTDT_WDG_FLAGS 0x0 + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog; +} ACPI_6_0_GTDT_STRUCTURE; +#pragma pack() + +ACPI_6_0_GTDT_STRUCTURE Gtdt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_GTDT_STRUCTURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= Address + 0x1, // UINT32 PlatformTim= erCount + sizeof (Gtdt.Header) // UINT32 PlatformTim= erOffset + }, { + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof (Gtdt.SbsaWatchdog), // UINT16 Length + 0x0, // UINT8 Reserved + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFram= ePhysicalAddress + FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogCon= trolFramePhysicalAddress + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTim= erGSIV + GTDT_WDG_FLAGS // UINT32 WatchdogTim= erFlags + }, +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Madt.aslc new file mode 100644 index 0000000..abd3cfc --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc @@ -0,0 +1,135 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceB= ase) +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define GICH_BASE 0xF0240000 +#define GICV_BASE 0xF0260000 +#define VGIC_MAINT_INT 25 + +#define GIC_MSI_FRAME0 0xF0280000 +#define GIC_MSI_FRAME1 0xF0290000 +#define GIC_MSI_FRAME2 0xF02A0000 +#define GIC_MSI_FRAME3 0xF02B0000 + +#define PMU_INTERRUPT_CPU0 130 +#define PMU_INTERRUPT_CPU1 131 +#define PMU_INTERRUPT_CPU2 132 +#define PMU_INTERRUPT_CPU3 133 + +#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_= PERFORMANCE_INTERRUPT_MODEL + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicC[4]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4]; +} ACPI_6_0_MADT_STRUCTURE; +#pragma pack(pop) + + +ACPI_6_0_MADT_STRUCTURE Madt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MADT_STRUCTURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId + 0x000, // AcpiCpu= Uid + 0x000, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU0, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId + 0x001, // AcpiCpu= Uid + 0x001, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU1, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId + 0x100, // AcpiCpu= Uid + 0x100, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU2, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId + 0x101, // AcpiCpu= Uid + 0x101, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU3, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDist= HwId + GICD_BASE, // GicDist= Base + 0x0, // GicDist= Vector + EFI_ACPI_6_0_GIC_V2 // GicVers= ion + ), + { + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiF= rameId + GIC_MSI_FRAME0, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiF= rameId + GIC_MSI_FRAME1, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiF= rameId + GIC_MSI_FRAME2, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiF= rameId + GIC_MSI_FRAME3, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Pptt.aslc new file mode 100644 index 0000000..f37c751 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc @@ -0,0 +1,210 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define NUM_CORES FixedPcdGet64 (PcdCoreCount) + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_2_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_2_PPTT_CORE Cores[2]; +} ACPI_6_2_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + ACPI_6_2_PPTT_CLUSTER Clusters[NUM_C= ORES / 2]; +} ACPI_6_2_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_2_PPTT_PACKAGE Packages[1]; +} ACPI_6_2_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 256 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + 3 * SIZE_16KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 3, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2C= ache), \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_512KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE(pid, cid, 0), = \ + PPTT_CORE(pid, cid, 1), = \ + } = \ +} + +ACPI_6_2_PPTT_STRUCTURE Pptt =3D { + { + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTU= RE_SIGNATURE, + ACPI_6_2_PPTT_STRUCTURE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVIS= ION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResour= ces */ + }, { + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 1, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_1MB, /* Size */ + 2048, /* NumberOfSets */ + 8, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#endif + } + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc new file mode 100644 index 0000000..f663d8a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -0,0 +1,49 @@ +/** @file + Serial Port Console Redirection Table (SPCR) + + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include +#include + +#include "AcpiHeader.h" + +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + { EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] + MV_UART_AS32 (FixedPcdGet64(PcdSerialRegisterBase)), //= BaseAddress + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //= InterruptType + 0, //= Irq + 51, //= GlobalSystemInterrupt + 0, //= BaudRate + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //= Parity + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //= StopBits + 0, //= FlowControl + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //= TerminalType + EFI_ACPI_RESERVED_BYTE, //= Language + 0xFFFF, //= PciDeviceId + 0xFFFF, //= PciVendorId + 0, //= PciBusNumber + 0, //= PciDeviceNumber + 0, //= PciFunctionNumber + 0, //= PciFlags + 0, //= PciSegment + EFI_ACPI_RESERVED_DWORD //= Reserved2 +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48696): https://edk2.groups.io/g/devel/message/48696 Mute This Topic: https://groups.io/mt/34471898/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48697+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48697+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686155; cv=none; d=zoho.com; s=zohoarc; b=Q7Wu1Y8YCQfMgqmcXHO8IKCNnw9kkaJ0HfDKpbLg69LzwAZnvE/55TvnXE6BBeGCkNTRjYlMaqOIpe6kyWSHYaeOaa5ITfF8PCeMzqhAcZ8G1KWTVdABPlHTnjMNMbiW2/9mI4BcAqFEAoh32nASId6OTR2L7kQz3Sg1DsC6ThM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686155; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ke+4PAR8Oh/dghgiWz5XlyukBeV5Z5ffZE5Px+XCymc=; b=ekq/Xs9GT93A8uCz+AJCwNCgjS9Y/ECOWoFsri5LUCfiyGG5fvnBrS6zqZxQNC7uDni0afXSDCsex3Pw5ZKA62rClKThSqZe2KDwoD25pHRZKlPPAa17cObyWm8AnEFJ6NczQGA29AtOUJ+IDDoZu22A1gIhsne6MuDNedWc85I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48697+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15706861552711006.8486526130802; Wed, 9 Oct 2019 22:42:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:34 -0700 X-Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by mx.groups.io with SMTP id smtpd.web10.2525.1570686153862309110 for ; Wed, 09 Oct 2019 22:42:34 -0700 X-Received: by mail-lf1-f65.google.com with SMTP id w67so3379578lff.4 for ; Wed, 09 Oct 2019 22:42:33 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqyv/IogFkp2DbGOK4Lq+foG11axxMmhvtzbtGswpWXUNcYotg4uulll+Gk+2sOovRx8v7vWgQ== X-Received: by 2002:ac2:4a75:: with SMTP id q21mr4549306lfp.94.1570686151593; Wed, 09 Oct 2019 22:42:31 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:30 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 3/9] Marvell/Cn9130Db: Introduce board support Date: Thu, 10 Oct 2019 07:42:13 +0200 Message-Id: <1570686139-25182-4-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686154; bh=J0677CBzt2xt0i3myy32WoREvLxmKf0A9srMpQ9cdus=; h=Cc:Date:From:Reply-To:Subject:To; b=ccm1VEcBpIaC5PSmiQBCG51zVgE6AFFhu1W31f5zn5aPOqp/bWXdg7nCOKpjcK3Q+Np J0UwHztX27ZXmJsBjc7j8vaavNOG+Kxa7l6F1anU03JxnNuo3r9WgsS0IcIQd+xYvJIUU 72SrJ3pyghBz2QCjpiVaGe7/hCHQhPik1CY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9130-DB setup A. Because the board is modular and can be extended to support also CN9131 and CN9132 SoC variants, extract common part into .dsc.inc file, which will be included by them. In order to build this variant, '-D CN9130' flag should be added. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc = | 107 +++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 48 +++++++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf = | 29 ++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.in= f | 37 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 19 +++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c = | 126 +++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 144 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc = | 18 +++ 8 files changed, 528 insertions(+) create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbA= BoardDescLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.h create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbA= BoardDescLib.c create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.c create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc new file mode 100644 index 0000000..33fb7cc --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -0,0 +1,107 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|2 + + # APN807 MPP + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP115 #0 MPP + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0x9 } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + + # SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + # PCIE + gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 + + # RTC + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + + # SoC Configuration Space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 + + # Variable store + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc new file mode 100644 index 0000000..fc1190d --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -0,0 +1,48 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] +!if $(CN9130) + PLATFORM_NAME =3D Cn9130DbA +!endif + PLATFORM_GUID =3D 087305a1-8ddd-4027-89ca-68a3ef78fcc7 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001000B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Cn913xDb/Cn913xDbA.f= df.inc + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc + +[Components.common] + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf + +[Components.AARCH64] + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf + +[LibraryClasses.common] + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDes= cLib.inf new file mode 100644 index 0000000..dfbdc84 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbABoardDescLib + FILE_GUID =3D d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaBoardDescLib + +[Sources] + Cn9130DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscove= rableInitLib.inf new file mode 100644 index 0000000..f7cfb36 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbANonDiscoverableInitLib + FILE_GUID =3D 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NonDiscoverableInitLib + +[Sources] + NonDiscoverableInitLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + MvGpioLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Depex] + gMarvellPlatformInitCompleteProtocolGuid diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h new file mode 100644 index 0000000..e1a5c34 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -0,0 +1,19 @@ +/** +* +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef NON_DISCOVERABLE_INIT_LIB_H__ +#define NON_DISCOVERABLE_INIT_LIB_H__ + +#define CN9130_DB_IO_EXPANDER0 0 +#define CN9130_DB_VBUS0_PIN 0 +#define CN9130_DB_VBUS0_LIMIT_PIN 4 +#define CN9130_DB_VBUS1_PIN 1 +#define CN9130_DB_VBUS1_LIMIT_PIN 5 +#define CN9130_DB_SDMMC_VCC_PIN 14 +#define CN9130_DB_SDMMC_VCCQ_PIN 15 + +#endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescL= ib.c new file mode 100644 index 0000000..2b46d14 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -0,0 +1,126 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander =3D { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount =3D 1; + *GpioExpanders =3D &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xD0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xDFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x10000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D MAX_UINT64, + .PcieMmio64WinSize =3D 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc =3D mSdMmcDescTemplate; + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c new file mode 100644 index 0000000..598c649 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -0,0 +1,144 @@ +/** +* +* Copyright (c) 2017, Linaro Ltd. All rights reserved. +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "NonDiscoverableInitLib.h" + +STATIC +EFI_STATUS +EFIAPI +ConfigurePins ( + IN CONST MV_GPIO_PIN *VbusPin, + IN UINTN PinCount, + IN MV_GPIO_DRIVER_TYPE DriverType + ) +{ + EMBEDDED_GPIO_MODE Mode; + EMBEDDED_GPIO_PIN Gpio; + EMBEDDED_GPIO *GpioProtocol; + EFI_STATUS Status; + UINTN Index; + + Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _)); + return Status; + } + + for (Index =3D 0; Index < PinCount; Index++) { + Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0; + Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber); + GpioProtocol->Set (GpioProtocol, Gpio, Mode); + VbusPin++; + } + + return EFI_SUCCESS; +} + +STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0XhciVbusPins, + ARRAY_SIZE (mCp0XhciVbusPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCC_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCCQ_PIN, + FALSE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0SdMmcInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0SdMmcPins, + ARRAY_SIZE (mCp0SdMmcPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +NON_DISCOVERABLE_DEVICE_INIT +EFIAPI +NonDiscoverableDeviceInitializerGet ( + IN NON_DISCOVERABLE_DEVICE_TYPE Type, + IN UINTN Index + ) +{ + if (Type =3D=3D NonDiscoverableDeviceTypeXhci) { + switch (Index) { + case 0: + case 1: + return Cp0XhciInit; + } + } + + if (Type =3D=3D NonDiscoverableDeviceTypeSdhci) { + switch (Index) { + case 1: + return Cp0SdMmcInit; + } + } + + return NULL; +} diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn913xDbA.fdf.inc new file mode 100644 index 0000000..0c321d1 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -0,0 +1,18 @@ +# +# Copyright (C) 2019 Marvell International Ltd. and its affiliates +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-board additional content of the DXE phase firmware volume + + INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf + +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf +!endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48697): https://edk2.groups.io/g/devel/message/48697 Mute This Topic: https://groups.io/mt/34471899/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48698+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48698+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686156; cv=none; d=zoho.com; s=zohoarc; b=jKXv6eQiLGPj87zTKnvdfgJEr6J+uB16tnt8NETWOAHudMgCM2O2V35zL6hdlM/4RsNAAO/3RQaF+Tp+YzhTRjwxAfnVxHNfxBZ8eFAMwry6PwS8NRCCckomWTDsnbEDolRBgiJQsACiOlzWHIjw/wKsD8UVo/g+cvwlsxo4yo0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686156; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Ms4v3C7L2OPkk75SiSftAyilKrKYX3bMb4ybZmai50w=; b=V6miF/tPFaHP5sS8YPL6r1ITEbuR9k2p948Gzl7JQXzo+dN2izLWUEedK54Vh8Gn9NzpFrw6Fux8m9/e727f+JY5UyKAf4qqBHhbdU+KFsCPRM7Pqf+6wIx8vICrxg+Zowu8y1MnwdCkm1tOtKdQc8Jv6OQ7tv4NHE8sj9YcHv0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48698+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686156119463.5189149482027; Wed, 9 Oct 2019 22:42:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:35 -0700 X-Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by mx.groups.io with SMTP id smtpd.web10.2526.1570686154852512176 for ; Wed, 09 Oct 2019 22:42:35 -0700 X-Received: by mail-lf1-f66.google.com with SMTP id u3so3366868lfl.10 for ; Wed, 09 Oct 2019 22:42:34 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqztrd+zMjFBGydmK+VQgnrSQW5poLZzOKYicyoTt1j62wwTk3IMVV5KOZCA7mjVYtaVM0wCkA== X-Received: by 2002:a19:4a13:: with SMTP id x19mr4849271lfa.184.1570686152825; Wed, 09 Oct 2019 22:42:32 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:32 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information Date: Thu, 10 Oct 2019 07:42:14 +0200 Message-Id: <1570686139-25182-5-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686155; bh=kZUatF5JpERfrHLewMmQ3kaCpKR1RFX7FGOjbGhTlwc=; h=Cc:Date:From:Reply-To:Subject:To; b=CyrrdrA9hj75rlEwWHQL1O0OOZ+R7k6NKUKHP5vm8Gw57rw0AR3u4BjBtMIiPHnbP0d jKZjECrqEz1L37iiw1My0P/95/Skix68DyqAw5gxg4pwLJ0JR0qDp/6n97I5ucdI3iYLn YIv4lb2GOQm128LL/7eZqIzld8pn9PGSlec= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hitherto SoC description and MppLib libraries code assumed that there could be only two Xenon SdMmc controller instances in the SoC. Remove those limitations, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas Acked-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 5 +-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 34 +++++++++++++------- Silicon/Marvell/Library/MppLib/MppLib.c = | 4 +-- 3 files changed, 26 insertions(+), 17 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 0296d43..265b4f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -90,8 +90,9 @@ // // Platform description of SDMMC controllers // -#define MV_SOC_MAX_SDMMC_COUNT 2 -#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) +#define MV_SOC_SDMMC_PER_CP_COUNT 1 +#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000 +#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000) =20 // // Platform description of UTMI PHY's diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 5947601..3ffd57e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -349,26 +349,36 @@ EFI_STATUS EFIAPI ArmadaSoCDescSdMmcGet ( IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, - IN OUT UINTN *DescCount + IN OUT UINTN *Count ) { - MV_SOC_SDMMC_DESC *Desc; - UINTN Index; + MV_SOC_SDMMC_DESC *SdMmc; + UINTN CpCount, CpIndex; =20 - Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); - if (Desc =3D=3D NULL) { + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT; + SdMmc =3D AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC)); + if (SdMmc =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); return EFI_OUT_OF_RESOURCES; } =20 - for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { - Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); - Desc[Index].SdMmcMemSize =3D SIZE_1KB; - Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; - } + *SdMmcDesc =3D SdMmc; + + /* AP80x controller */ + SdMmc->SdMmcBaseAddress =3D MV_SOC_AP80X_SDMMC_BASE; + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; =20 - *SdMmcDesc =3D Desc; - *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + /* CP11x controllers */ + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + SdMmc->SdMmcBaseAddress =3D MV_SOC_CP_SDMMC_BASE (CpIndex); + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; + } =20 return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Libr= ary/MppLib/MppLib.c index 40d9077..f20668d 100644 --- a/Silicon/Marvell/Library/MppLib/MppLib.c +++ b/Silicon/Marvell/Library/MppLib/MppLib.c @@ -139,11 +139,9 @@ SetSdMmcPhyMpp ( case 0: Offset =3D SD_MMC_PHY_AP_MPP_OFFSET; break; - case 1: + default: Offset =3D SD_MMC_PHY_CP0_MPP_OFFSET; break; - default: - return; } =20 /* --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48698): https://edk2.groups.io/g/devel/message/48698 Mute This Topic: https://groups.io/mt/34471900/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48699+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48699+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686157; cv=none; d=zoho.com; s=zohoarc; b=jKU1qnJD+WnsxKxaLVtHuz78ysKbi+qCgdzWu7YcV/AE/4BnVVLIruFnF7aZmUeWmgcWZkMcinjnpVvS/kLqFaPl2ouf2VpxBn1H2JN2zeSAJO8l1w6euk4WI3PB1eGY+v2jmSWRpgq6/ZWdlk7JkTEwhR82PpH+Qx//WZYv5ag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686157; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=MgFy/2JTO/lmvX/d1heF6pyVN0gdJ/vs6Wvd9D7WxTk=; b=JWh9sVCxW/KrGmPoYt1OpPxMUwnf6U7eMxzCtoeqif41LIX801ygZtLP38SntArw/Urvc5yyH6eENiglFGnGSwi5Uu5s71HPJ5wpT9C4bqhiMNyBfPp572d6DclxkMbPHQx5xRHLFSzuuZG0kfFNlLhY0ZRX0yaBvdCJACpkUi0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48699+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686157141149.91624882177825; Wed, 9 Oct 2019 22:42:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:36 -0700 X-Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by mx.groups.io with SMTP id smtpd.web11.2582.1570686155845708256 for ; Wed, 09 Oct 2019 22:42:36 -0700 X-Received: by mail-lf1-f65.google.com with SMTP id r134so3362682lff.12 for ; Wed, 09 Oct 2019 22:42:35 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqwsjU3pAYPdl5fFLHbVHf6z9Um/KNmIgi2GGNMuTX4Avswoh7D10EqO3a1N4kKjhjD1Z9rR3g== X-Received: by 2002:a19:84c:: with SMTP id 73mr4568956lfi.180.1570686153864; Wed, 09 Oct 2019 22:42:33 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:33 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 5/9] Marvell/Library: IcuLib: Fix debug information Date: Thu, 10 Oct 2019 07:42:15 +0200 Message-Id: <1570686139-25182-6-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686156; bh=N/8iw0i5IKGc8VNJKjp4pHp+i69UIe3DathZGAGwUSU=; h=Cc:Date:From:Reply-To:Subject:To; b=dCrWiIvhAoaVP0E+5zOQ/0iO94g7KGL6+/FbjNQyN7Ee5jkwtlYHKhFjAON53iULF7N HL4p39Jvh5DQCTLkWylYHMpmtDpFO2T0uP5DPiWw2DTAwCWeZTEUbExPSc4EmRGqbotKq KwA/GAFiGHl5wp8eMmyVfBoJkpCP2JbRr+8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In case the number of CP11x components exceeded the maximum of currently supported, the user is informed with the information. It turned out that the print arguments were incorrect - fix it. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c index 343c21b..4d9f174 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.c +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -280,8 +280,8 @@ ArmadaIcuInitialize ( if (CpCount > ICU_MAX_SUPPORTED_UNITS) { DEBUG ((DEBUG_ERROR, "%a: Default ICU to GIC mapping is available for maximum %d CP110 un= its", - ICU_MAX_SUPPORTED_UNITS, - __FUNCTION__)); + __FUNCTION__, + ICU_MAX_SUPPORTED_UNITS)); CpCount =3D ICU_MAX_SUPPORTED_UNITS; } =20 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48699): https://edk2.groups.io/g/devel/message/48699 Mute This Topic: https://groups.io/mt/34471901/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48700+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48700+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686160; cv=none; d=zoho.com; s=zohoarc; b=YNxAb6WYZkNa3frYMXTd2XcZlay6feTt9cVzvEBoDTwLCiHHnDtz0k+P0SbI+JeHDpGP2PVMx3YpLUtO1hHGxszs7eAg1E8MBdh+3zqyP6q/NDuB4R2rUNsZdyazTVjEh/1ilzrto4dJa3dIJ8ZCrF0EYWUkFuFJxXmSRGKXHog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686160; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=AaXFlVJhtlOKrB1NaMpNP1siEP+CJjs4YOsKzrpxLjg=; b=muPnwhYPevtAq6rJv7GvU8EJ1gVT2o1cHgRTNsJToEkae6eVfSncfrhb0Zr9ImeBz/NLv5zbtPM13n/iXF18HavZ2ZfN8XQkWtU0ChU2zyH89XzsNg8GFJjPRptOS+/w+ZuInpeCgTD3F+SYTDiRg1OwigYdt9MmO8kU6zm7B/g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48700+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686160035227.55827680890195; Wed, 9 Oct 2019 22:42:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:38 -0700 X-Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by mx.groups.io with SMTP id smtpd.web11.2583.1570686157144888461 for ; Wed, 09 Oct 2019 22:42:37 -0700 X-Received: by mail-lj1-f193.google.com with SMTP id d1so4803167ljl.13 for ; Wed, 09 Oct 2019 22:42:36 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqzhzPRJ+PqUFsay2OU6W7ibFshQSZoM6ToNwMIdDggkkm2FlgZDzz0KOIpVDBm5OUUiDHOa1Q== X-Received: by 2002:a2e:9981:: with SMTP id w1mr4804576lji.205.1570686155042; Wed, 09 Oct 2019 22:42:35 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:34 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 6/9] Marvell/Cn9131Db: Introduce board support Date: Thu, 10 Oct 2019 07:42:16 +0200 Message-Id: <1570686139-25182-7-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686158; bh=g9j32nsFzRlprCVyqIjrpJ1XYM5iPN1X3OpMJf+hsnE=; h=Cc:Date:From:Reply-To:Subject:To; b=iFdecf9SuKQRGz7+AljhIzndJ3asx7guVRqrnlRGBn4xpe/m+2LRQL1DI6Pwov9bqD9 sdD4YP7+poBO+nnQ9VFYihv6zTjkV9DSS5myHMRd+uo2ZUOPh3r+Yv2yjOAM129KHkqXS n5hmY0+kt+uWKFEhDpDbcmd67RObNADbI5E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9131-DB setup A. In order to build this variant, '-D CN9131' flag should be added. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc = | 72 ++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 5 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf = | 57 ++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h = | 2 + Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 29 ++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl = | 98 ++++++++++++++++++++ 7 files changed, 265 insertions(+) create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.= asl diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.dsc.inc new file mode 100644 index 0000000..7235b9f --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9131 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # CP115 #1 MPP + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0= x7, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: UNCONNECTED + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_D= EFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index fc1190d..70f99cf 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -15,6 +15,8 @@ [Defines] !if $(CN9130) PLATFORM_NAME =3D Cn9130DbA +!elseif $(CN9131) + PLATFORM_NAME =3D Cn9131DbA !endif PLATFORM_GUID =3D 087305a1-8ddd-4027-89ca-68a3ef78fcc7 PLATFORM_VERSION =3D 0.1 @@ -36,6 +38,9 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +!if $(CN9131) +!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc +!endif =20 [Components.common] Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf new file mode 100644 index 0000000..bbf1b51 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -0,0 +1,57 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn9131DbA/Ssdt.asl + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9131 diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index e1a5c34..3ca6374 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -15,5 +15,7 @@ #define CN9130_DB_VBUS1_LIMIT_PIN 5 #define CN9130_DB_SDMMC_VCC_PIN 14 #define CN9130_DB_SDMMC_VCCQ_PIN 15 +#define CN9131_DB_VBUS0_PIN 3 +#define CN9131_DB_VBUS0_LIMIT_PIN 2 =20 #endif diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index b5fd397..2838676 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -18,6 +18,8 @@ =20 #if defined(CN9130) #define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#elif defined (CN9131) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ',= ' ') #endif =20 /** diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index 598c649..dded150 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -91,6 +91,33 @@ Cp0XhciInit ( MV_GPIO_DRIVER_TYPE_PCA95XX); } =20 +STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp1XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp1XhciVbusPins, + ARRAY_SIZE (mCp1XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet ( case 0: case 1: return Cp0XhciInit; + case 2: + return Cp1XhciInit; } } =20 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl new file mode 100644 index 0000000..99bc751 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -0,0 +1,98 @@ +/** @file + + Secondary System Description Table Fields (SSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_USB_H1 + } + }) + } + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + } + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48700): https://edk2.groups.io/g/devel/message/48700 Mute This Topic: https://groups.io/mt/34471903/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48701+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48701+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686160; cv=none; d=zoho.com; s=zohoarc; b=fk2dsDAgr/uhkO068x8NFrPm5V5KlBIA6cpetc0mALzK9wJB02TMRquGlUFZCdFhchyXeC3hAhXdg17Y1J0xrFmu0XnMF1ZEFjihwvj4MeB+BK/ihg+ioY3rUh+5PRCSCVmg57BRb10AxCTF9RaLjDFKsWkR2X0q3w94PXKLrVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686160; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=OJnd5fuOQsaU1/H6zCkfvBndzrLvFjAWvRYK+mwCLEs=; b=Dvy/FpNgsUuSVj7Sae8BR9YgUpghY2EubGtUuy+zSo2SwbDzQKDRmgfA2b7R2OwrtQKBA+UNH9D/umz1AwXbtZlwfbdR6iF48beYTb913kBh2223DbEVzmHAi9tcIjIBnFevsjLT4R5UXS05VLJL/IVLNHfsbgmEDUbi7QZhp9A= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48701+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686160871428.8707955110759; Wed, 9 Oct 2019 22:42:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:39 -0700 X-Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) by mx.groups.io with SMTP id smtpd.web10.2529.1570686158713664066 for ; Wed, 09 Oct 2019 22:42:39 -0700 X-Received: by mail-lj1-f170.google.com with SMTP id b20so4852771ljj.5 for ; Wed, 09 Oct 2019 22:42:38 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqz9vBdA6blyNTSE4ehoMKFfVaL2aXEEmamxzAGMjiuH7byeGUgWG7gSoZrg/UfO18qz6MuCiQ== X-Received: by 2002:a2e:9890:: with SMTP id b16mr4931068ljj.181.1570686156382; Wed, 09 Oct 2019 22:42:36 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:35 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 7/9] Marvell/Cn9132Db: Introduce board support Date: Thu, 10 Oct 2019 07:42:17 +0200 Message-Id: <1570686139-25182-8-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686159; bh=z4DPVgmLCDA3//L/MjCROZg6MnahkoQS6/eaXFCbobQ=; h=Cc:Date:From:Reply-To:Subject:To; b=hld9Q+MwdeMMzMY921DaO2w0qaOfFTjTc6hP0juH3qnJ4D85HQ4h4L6TWtc4S2HBBSH tEre8nyP0zr+PVsOxj0nTO90gJCqQ7mvaRxND4HgBsbA0grmyEGuDnB/1xe2W2oO6kiDS 0AY8XqvP03WSfUZdG36ELuCqrLBds61Tj3Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9132-DB setup A. Note the ACPI is not yet available for this variant, due to the current ICU (CP1xx interrupt controller) support implementation. In order to build this variant, '-D CN9132' flag should be added. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc = | 72 +++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 13 +- Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf = | 29 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 4 + Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c = | 135 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 42 ++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc = | 2 + 7 files changed, 296 insertions(+), 1 deletion(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbA= BoardDescLib.inf create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbA= BoardDescLib.c diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9132DbA.dsc.inc new file mode 100644 index 0000000..a0b90fa --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9132 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|4 + + # CP115 #2 MPP + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x9, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0= x0, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: SATA0 5 Gbps + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0= } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index 70f99cf..268c39c 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -17,6 +17,8 @@ PLATFORM_NAME =3D Cn9130DbA !elseif $(CN9131) PLATFORM_NAME =3D Cn9131DbA +!elseif $(CN9132) + PLATFORM_NAME =3D Cn9132DbA !endif PLATFORM_GUID =3D 087305a1-8ddd-4027-89ca-68a3ef78fcc7 PLATFORM_VERSION =3D 0.1 @@ -38,16 +40,25 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc -!if $(CN9131) +!if $(CN9131) || $(CN9132) !include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc !endif +!if $(CN9132) +!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc +!endif =20 [Components.common] Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf =20 +!ifndef $(CN9132) [Components.AARCH64] Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf +!endif =20 [LibraryClasses.common] +!if $(CN9132) + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132D= bABoardDescLib.inf +!else ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf +!endif NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDes= cLib.inf new file mode 100644 index 0000000..27a0214 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9132DbABoardDescLib + FILE_GUID =3D cf7a0f12-45fe-417b-9c34-053605973b68 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaBoardDescLib + +[Sources] + Cn9132DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index 3ca6374..a641420 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -17,5 +17,9 @@ #define CN9130_DB_SDMMC_VCCQ_PIN 15 #define CN9131_DB_VBUS0_PIN 3 #define CN9131_DB_VBUS0_LIMIT_PIN 2 +#define CN9132_DB_VBUS0_PIN 2 +#define CN9132_DB_VBUS0_LIMIT_PIN 0 +#define CN9132_DB_VBUS1_PIN 3 +#define CN9132_DB_VBUS1_LIMIT_PIN 1 =20 #endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescL= ib.c new file mode 100644 index 0000000..d2846dd --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c @@ -0,0 +1,135 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander =3D { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount =3D 1; + *GpioExpanders =3D &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xD0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xDFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x10000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D MAX_UINT64, + .PcieMmio64WinSize =3D 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF6780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc =3D mSdMmcDescTemplate; + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index dded150..42dc54a 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -118,6 +118,45 @@ Cp1XhciInit ( MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); } =20 +STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp2XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp2XhciVbusPins, + ARRAY_SIZE (mCp2XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet ( return Cp0XhciInit; case 2: return Cp1XhciInit; + case 3: + case 4: + return Cp2XhciInit; } } =20 diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn913xDbA.fdf.inc index 0c321d1..78bdb79 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -12,7 +12,9 @@ # DTB INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf =20 +!ifndef $(CN9132) !if $(ARCH) =3D=3D AARCH64 # ACPI support INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf !endif +!endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48701): https://edk2.groups.io/g/devel/message/48701 Mute This Topic: https://groups.io/mt/34471904/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48702+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48702+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686161; cv=none; d=zoho.com; s=zohoarc; b=f1aeHQ4Auvtqc+oksOB/OiwBP3nJ83Se5ACd9M3mw1SX1SxjfYcKU6lp9FTg0wO9unBkhgt3L18AlLTeOS5PyTkCJQyv8mBVIb3b7qMt0ZE5WgZt24wl9CZxHIXni8hGttQX9bTxJBe9jNgbStUJO5b3BBb+Tg4ngAGR353Wo8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686161; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=EpOMb48UWn/RLsl8AXztgsG1NTmgWhkeIAlzZK8knfA=; b=PwY0/oR0ZspyEubGKidcNtfv09mdGg1HyWFMcTSr/4boqG03Is65Vk3h2tEStiqis5xdIabnluQI/ljs3tU5H8hk35GG3uTRThX5DP6YUReW/9aWXVz2TTrpn3kMOfSLthcafiO5u05aXBkFw2P3wTFHJL5tJN6q35qnLyTS3eE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48702+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15706861612151016.624216847536; Wed, 9 Oct 2019 22:42:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:40 -0700 X-Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by mx.groups.io with SMTP id smtpd.web10.2530.1570686159869148185 for ; Wed, 09 Oct 2019 22:42:40 -0700 X-Received: by mail-lj1-f195.google.com with SMTP id n14so4817226ljj.10 for ; Wed, 09 Oct 2019 22:42:39 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqz/Zsobkt5tShxD8SSTejqjO7IUArV5l4yqt0XAIZo5yUSu9AZSK5hM3b9WRFMys6UTkQ5KsQ== X-Received: by 2002:a2e:9e85:: with SMTP id f5mr5063291ljk.203.1570686157823; Wed, 09 Oct 2019 22:42:37 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:37 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Patryk Duda Subject: [edk2-devel] [edk2-platforms: PATCH v3 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD Date: Thu, 10 Oct 2019 07:42:18 +0200 Message-Id: <1570686139-25182-9-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686160; bh=KomZTacLu1bOLwpa6xe920wR/EdAm5uQi/s5bSO/QC0=; h=Cc:Date:From:Reply-To:Subject:To; b=PBdxyNz1SfaFUuArARkdrZuM22kLw9cW40vfmFTJPGglYDYZvYgij8NslHr0yJl3a+W d9WJJNqndhq770ISk/CNZ2WeqysCcYkfo3UZBGNt8TQUB+1yqSd9pAp0Fuh7ikD5rs4jI xVZWJjAYEXQnbNTqz90ObDe++r4mMicZfpA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Patryk Duda This patch implements convenient way of changing strings included in SMBIOS Table1, Table2, Table3. Strings can be altered by defining following PCDs: gMarvellTokenSpaceGuid.PcdProductManufacturer gMarvellTokenSpaceGuid.PcdProductPlatformName gMarvellTokenSpaceGuid.PcdProductVersion gMarvellTokenSpaceGuid.PcdProductSerial This patch adds also limit for length of string which can be increased if necessary in future. Signed-off-by: Patryk Duda --- Silicon/Marvell/Marvell.dec | 6 ++ Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 4 + Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 79 +++++= ++++++++++++--- 3 files changed, 78 insertions(+), 11 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index d337d3e..a84b056 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -169,6 +169,12 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 +#Platform description + gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell = \0"|VOID*|0x50000100 + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board= \0"|VOID*|0x50000101 + gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set = \0"|VOID*|0x50000103 + gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown = \0"|VOID*|0x50000102 + #RTC gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 =20 diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 8b4586c..7722146 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -36,6 +36,10 @@ =20 [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + gMarvellTokenSpaceGuid.PcdProductManufacturer + gMarvellTokenSpaceGuid.PcdProductPlatformName + gMarvellTokenSpaceGuid.PcdProductSerial + gMarvellTokenSpaceGuid.PcdProductVersion =20 [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index 08f4fa7..c5b1d77 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -21,6 +21,22 @@ #include =20 // +// SMBIOS specification indicates that there is no limit for string size. +// However, some strings are printed in UEFI and OS. Printing very big str= ing +// can lead to unexpected behaviour. Second reason of string size definiti= on +// is that static buffers can be used instead of dynamic ones. +// +// Nevertheless, this value can be increased if necessary +// + +#define MV_SMBIOS_STRING_MAX_SIZE 32 + +STATIC CHAR8 mSysInfoManufacturer[MV_SMBIOS_STRING_MAX_SIZE]; +STATIC CHAR8 mSysInfoProductName[MV_SMBIOS_STRING_MAX_SIZE]; +STATIC CHAR8 mSysInfoVersion[MV_SMBIOS_STRING_MAX_SIZE]; +STATIC CHAR8 mSysInfoSerial[MV_SMBIOS_STRING_MAX_SIZE]; + +// // SMBIOS tables often reference each other using // fixed constants, define a list of these constants // for our hardcoded tables @@ -101,10 +117,10 @@ STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 =3D { }; =20 STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] =3D { - "Marvell \0",/* Manufacturer */ - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ - "Revision unknown \0",/* Version placeholder */ - " \0",/* 32 character buffer */ + mSysInfoManufacturer, + mSysInfoProductName, + mSysInfoVersion, + mSysInfoSerial, NULL }; =20 @@ -129,10 +145,10 @@ STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 =3D { }; =20 STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] =3D { - "Marvell \0",/* Manufacturer */ - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ - "Revision unknown \0",/* Version placeholder */ - "Serial Not Set \0",/* Serial */ + mSysInfoManufacturer, + mSysInfoProductName, + mSysInfoVersion, + mSysInfoSerial, "Base of Chassis \0",/* Board location */ NULL }; @@ -160,9 +176,9 @@ STATIC SMBIOS_TABLE_TYPE3 mArmadaDefaultType3 =3D { }; =20 STATIC CHAR8 CONST *mArmadaDefaultType3Strings[] =3D { - "Marvell \0",/* Manufacturer placeholder */ - "Revision unknown \0",/* Version placeholder */ - "Serial Not Set \0",/* Serial placeholder */ + mSysInfoManufacturer, + mSysInfoVersion, + mSysInfoSerial, NULL }; =20 @@ -743,6 +759,45 @@ SmbiosMemoryInstall ( } =20 /** + Copy Type1, Type2, Type3 strings form PCD +**/ + +STATIC +VOID +MvSmbiosCopyStrings ( + VOID + ) +{ + EFI_STATUS Status; + + ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductManufacturer), + MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE); + ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductPlatformName), + MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE); + ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductVersion), + MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE); + ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductSerial), + MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE); + + Status =3D AsciiStrCpyS (mSysInfoManufacturer, + MV_SMBIOS_STRING_MAX_SIZE, + (CHAR8 *)PcdGetPtr (PcdProductManufacturer)); + ASSERT_EFI_ERROR (Status); + Status =3D AsciiStrCpyS (mSysInfoProductName, + MV_SMBIOS_STRING_MAX_SIZE, + (CHAR8 *)PcdGetPtr (PcdProductPlatformName)); + ASSERT_EFI_ERROR (Status); + Status =3D AsciiStrCpyS (mSysInfoVersion, + MV_SMBIOS_STRING_MAX_SIZE, + (CHAR8 *)PcdGetPtr (PcdProductVersion)); + ASSERT_EFI_ERROR (Status); + Status =3D AsciiStrCpyS (mSysInfoSerial, + MV_SMBIOS_STRING_MAX_SIZE, + (CHAR8 *)PcdGetPtr (PcdProductSerial)); + ASSERT_EFI_ERROR (Status); +} + +/** Install all structures from the DefaultTables structure =20 @param Smbios SMBIOS protocol @@ -760,6 +815,8 @@ SmbiosInstallAllStructures ( FirmwareMajorRevisionNumber =3D (PcdGet32 (PcdFirmwareRevision) >> 16) &= 0xFF; FirmwareMinorRevisionNumber =3D PcdGet32 (PcdFirmwareRevision) & 0xFF; =20 + MvSmbiosCopyStrings(); + // // Update Firmware Revision, CPU and DRAM frequencies. // --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48702): https://edk2.groups.io/g/devel/message/48702 Mute This Topic: https://groups.io/mt/34471905/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 07:21:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48703+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48703+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686162; cv=none; d=zoho.com; s=zohoarc; b=IpIJ4yUvjbkGJnbosWq7jXTj2UeY0lS2kjfFY3qFJoM7kxz0gQYD60ZOtAzmbGAKyzQcfcB/n/Vl8E/Wmg+IRPwOkwmW2LlDA6OR/jvCcUKRt0DvqzIlge+gSU3ICRV2Tr3XCLsdk4fCMddKWJ+u+fhZC14DkgNqp/BAOfQ9EgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686162; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=PxVu03wmRYcQOPTmFRsXNeTj5dBwFGrZehTEsE2btTk=; b=IlGK2iTUCxDlzPZxogFr8WcI2x93rPYZpopxWS6EZ790peli7a8Yn+46hi7F7XMTXypxOYHkxLXH1Yr7cVEIo4pO3+U2JK5kosUEREEa3NPrv62LRXWhOf1Q87aDuYIii+m2+aWaFXhC6BdDIT/6kpHwU2DO92AK0sW/JvSHtQI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48703+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686162445360.2028611532787; Wed, 9 Oct 2019 22:42:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:42:41 -0700 X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web10.2531.1570686160741237401 for ; Wed, 09 Oct 2019 22:42:41 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id 7so4841809ljw.7 for ; Wed, 09 Oct 2019 22:42:40 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqzzeKHRS07I22iPdN21wK+LN3j9CwdtnWbtg8fugPzTAmB3akChsr2VCNKXdKJefoS6bS7J3g== X-Received: by 2002:a2e:9cc9:: with SMTP id g9mr5047170ljj.160.1570686158745; Wed, 09 Oct 2019 22:42:38 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p27sm1001481lfo.95.2019.10.09.22.42.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:42:38 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v3 9/9] Marvell: Customize per-board SBMIOS strings Date: Thu, 10 Oct 2019 07:42:19 +0200 Message-Id: <1570686139-25182-10-git-send-email-mw@semihalf.com> In-Reply-To: <1570686139-25182-1-git-send-email-mw@semihalf.com> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686161; bh=2KMhT/CMyuYlFGkrBLc+gstF2WcqHvHQQb1WGoE7UcA=; h=Cc:Date:From:Reply-To:Subject:To; b=k8w8qwKFxbxy3P+ogkLj+UJfT3Qb1Ggmn+/udVeWlE/iqlEZ6fAlcGMi775QPVxXYHq s0//CzSgmVfkLmaDzJSdLwEiicPxaLAm2bocoAZ7EhHUjYNP3xZ49N7+lNBw78hYRNc00 YHtSJvtTpVFkNA+OpCMWG0pQdr0+8UEmqpw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that the customization of Type1/2/3 SBMIOS tables strings is possible, adjust them for all supported boards. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 ++++ Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 ++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 11 +++++++++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 5 +++++ 4 files changed, 24 insertions(+) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 523e60e..3626967 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -45,6 +45,10 @@ # ##########################################################################= ###### [PcdsFixedAtBuild.common] + #Platform description + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB\0" + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5\0" + #CP110 count gMarvellTokenSpaceGuid.PcdMaxCpCount|1 =20 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 4e6e62b..ce0c541 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -45,6 +45,10 @@ # ##########################################################################= ###### [PcdsFixedAtBuild.common] + #Platform description + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB\0" + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4\0" + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|3 =20 diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index 268c39c..bcc5158 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -62,3 +62,14 @@ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf !endif NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf + +[PcdsFixedAtBuild.common] + #Platform description + !if $(CN9130) + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A\0" + !elseif $(CN9131) + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A\0" + !elseif $(CN9132) + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A\0" + !endif + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1\0" diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index 2b42d75..f7d5a57 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -46,6 +46,11 @@ # ##########################################################################= ###### [PcdsFixedAtBuild.common] + #Platform description + gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun\0" + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin\= 0" + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3\0" + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|3 =20 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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