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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27sm950028ljd.55.2019.10.09.22.41.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:41:49 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-non-osi: PATCH 1/3] Marvell/Cn9130Db: Add DeviceTree Date: Thu, 10 Oct 2019 07:41:16 +0200 Message-Id: <1570686078-25140-2-git-send-email-mw@semihalf.com> In-Reply-To: <1570686078-25140-1-git-send-email-mw@semihalf.com> References: <1570686078-25140-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686114; bh=RdxKYDq0saFNXoaFPQQ7v5n1FclPd0GscRi58b+O5GI=; h=Cc:Date:From:Reply-To:Subject:To; b=dlgop3+/UZHuuU5aKS1y7zRoAbIvz+EbeLVCLGIu0rtwnj1n9zWW2gJOfjgaqtPpd7t Xf9a53tW6p9SasCFVX5Ewrs7CsQo1wjtHiizAQSoHmr7mbe9ph/RaZqRcNCbfK9UOQQK+ kQgD2xsxlwMhO8tvDsm57T8/kMEJx7CvjFM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds device tree sources which are common for Cn913x SoCs and the CN9130 development board (variant A). Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 +++++= +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 +++++= +++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++= ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 173 ++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 76 +++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 151 ++++++ 12 files changed, 1799 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.d= tsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf new file mode 100644 index 0000000..091a5b4 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9130-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Quad"; + compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +/dts-v1/; + +/ { + model =3D "Marvell Armada AP806"; + compatible =3D "marvell,armada-ap806"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + gpio0 =3D &ap_gpio; + spi0 =3D &spi0; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + ap806 { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + config-space@f0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + interrupts =3D ; + reg =3D <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x280000 0x1000>; + arm,msi-base-spi =3D <160>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m1: v2m@290000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x290000 0x1000>; + arm,msi-base-spi =3D <192>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2a0000 0x1000>; + arm,msi-base-spi =3D <224>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2b0000 0x1000>; + arm,msi-base-spi =3D <256>; + arm,msi-num-spis =3D <32>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupt-parent =3D <&pic>; + interrupts =3D <17>; + }; + + odmi: odmi@300000 { + compatible =3D "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames =3D <4>; + reg =3D <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base =3D <128>, <136>, <144>, = <152>; + }; + + gicp: gicp@3f0040 { + compatible =3D "marvell,ap806-gicp"; + reg =3D <0x3f0040 0x10>; + marvell,spi-ranges =3D <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible =3D "marvell,armada-8k-pic"; + reg =3D <0x3f0100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + xor@400000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x510600 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + i2c0: i2c@511000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x511000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + timeout-ms =3D <1000>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart0: serial@512000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart1: serial@512100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; + interrupts =3D ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible =3D "marvell,armada-ap806-sdhci= "; + reg =3D <0x6e0000 0x300>; + interrupts =3D ; + clock-names =3D "core"; + clocks =3D <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status =3D "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f4000 0x2000>; + + ap_clk: clock { + compatible =3D "marvell,ap806-cloc= k"; + #clock-cells =3D <1>; + }; + + ap_pinctrl: pinctrl { + compatible =3D "marvell,ap806-pinc= trl"; + + uart0_pins: uart0-pins { + marvell,pins =3D "mpp11", = "mpp19"; + marvell,function =3D "uart= 0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible =3D "marvell,armada-8k-= gpio"; + offset =3D <0x1040>; + ngpios =3D <20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + }; + }; + + ap_thermal: thermal@6f808c { + compatible =3D "marvell,armada-ap806-therm= al"; + reg =3D <0x6f808c 0x4>, + <0x6f8084 0x8>; + }; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/S= ilicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi new file mode 100644 index 0000000..b6e5ded --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP110. + */ + +#include "armada-common.dtsi" + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0= xf00000) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP110_NAME: CP110_NAME { }; +}; + +&CP110_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP110_LABEL(icu)>; + ranges; + + config-space@CP110_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; + + CP110_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, + <&CP110_LABEL(core_clk)>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP110_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP110_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP110_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #interrupt-cells =3D <3>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP110_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D ; + status =3D "disabled"; + }; + + CP110_LABEL(thermal): thermal@400078 { + compatible =3D "marvell,armada-cp110-thermal"; + reg =3D <0x400078 0x4>, + <0x400070 0x8>; + }; + + CP110_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP110_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + status =3D "disabled"; + #clock-cells =3D <2>; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + + CP110_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + }; + + CP110_LABEL(usb3_0): usb3@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(usb3_1): usb3@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + interrupts =3D ; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(nand_clk)>, + <&CP110_LABEL(x2core_clk)>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP110_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "okay"; + }; + + CP110_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D ; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; + dma-coherent; + status =3D "disabled"; + }; + + CP110_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197"; + reg =3D <0x800000 0x200000>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + dma-coherent; + }; + }; + + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_B= ASE(0) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_B= ASE(1) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_B= ASE(2) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + /* 1 GHz fixed main PLL */ + CP110_LABEL(mainpll): CP110_LABEL(mainpll) { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(core_clk): CP110_LABEL(core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <3>; + }; + + CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <4>; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts new file mode 100644 index 0000000..9e4aa51 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "cn9130-db.dtsi" + +/ { + model =3D "Model: Marvell CN9130 development board (CP NOR) setup(= A)"; + compatible =3D "marvell,cn9130-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + i2c0 =3D &cp0_i2c0; + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth2; + }; + + memory@00000000 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +/* on-board eMMC - U9 */ +&ap_sdhci0 { + pinctrl-names =3D "default"; + bus-width =3D <8>; + status =3D "okay"; + vqmmc-supply =3D <&ap0_reg_sd_vccq>; +}; + +/* + * CP related configuration + */ +&cp0_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&cp0_i2c1 { + status =3D "okay"; +}; + +/* CON 28 */ +&cp0_sdhci0 { + status =3D "okay"; +}; + +/* U54 */ +&cp0_nand_controller { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nand_pins>; + + nand@0 { + reg =3D <0>; + label =3D "main-storage"; + nand-rb =3D <0>; + nand-ecc-mode =3D "hw"; + nand-on-flash-bbt; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xd00000>; + }; + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* U55 */ +&cp0_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_spi0_pins>; + reg =3D <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>; /* CS0 */ + status =3D "disabled"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency =3D <40000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; +}; + +/* SLM-1521-V2, CON6 */ +&cp0_pcie0 { + status =3D "okay"; + num-lanes =3D <4>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + status =3D "okay"; + /* SLM-1521-V2, CON2 */ +}; + +&cp0_mdio { + status =3D "okay"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp0_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp0_sfp_eth0>; +}; + +/* CON56 */ +&cp0_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +/* CON57 */ +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi new file mode 100644 index 0000000..eeb96f6 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +#include "cn9130.dtsi" /* include SoC device tree */ + +/ { + model =3D "DB-CN-9130"; + compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy0: cp0_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus0>; + }; + + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy1: cp0_usb3_phy1 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus1>; + }; + + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 15 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 + 3300000 0x0>; + }; + + ap0_reg_sd_vccq: ap0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "ap0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 8 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 + 3300000 0x0>; + }; + + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0_sd_vcc"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + cp0_sfp_eth0: sfp-eth0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp0_sfpp0_i2c>; + los-gpio =3D <&cp0_moudle_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_moudle_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp0_moudle_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp0_moudle_expander1 8 GPIO_ACTIVE_HIG= H>; + status =3D "disabled"; + }; +}; + +/* + * CP0 + */ +&cp0_i2c0 { + clock-frequency =3D <100000>; + + /* U36 */ + expander0: pca953x@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + status =3D "okay"; + }; + + /* U42 */ + eeprom0: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + pagesize =3D <0x20>; + }; + + /* U38 */ + eeprom1: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <0x20>; + }; +}; + +&cp0_i2c1 { + clock-frequency =3D <100000>; + + /* SLM-1521-V2 - U3 */ + i2c-mux@72 { /* verify address - depends on dpr */ + compatible =3D "nxp,pca9544"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x72>; + cp0_sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + /* U12 */ + cp0_moudle_expander1: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + + }; + }; +}; + + +&cp0_sdhci0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins>; + bus-width =3D <4>; + no-1-8-v; + vqmmc-supply =3D <&cp0_reg_sd_vccq>; + vmmc-supply =3D <&cp0_reg_sd_vcc>; +}; + +&cp0_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy0>; + phy-names =3D "usb"; +}; + +&cp0_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy1>; + phy-names =3D "usb"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/= Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi new file mode 100644 index 0000000..97ea923 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +/* + * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and + * three CP110. + */ + +#include "armada-ap806-quad.dtsi" + +/ { + aliases { + gpio1 =3D &cp0_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + }; +}; + +/* This defines used to calculate the base address of each CP */ +#define CP110_PCIE_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : = 0xf00000) +#define CP110_PCIE_BUS_MEM_CFG (0x82000000) + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 +#define CP110_BASE f2000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : \ + (0xe0000000 + (iface - 1) * 0x100= 0000)) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +#undef CP110_NUM +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/ { + model =3D "Marvell CN 9130"; + compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad", + "marvell,armada-ap806"; +}; + +&cp0_crypto { + status =3D "okay"; +}; + +&cp0_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-7k-pinctrl"; + + cp0_devbus_pins: cp0-devbus-pins { + marvell,pins =3D "mpp15", "mpp16", "mpp17", + "mpp18", "mpp19", "mpp20", + "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins =3D "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11"; + marvell,function =3D "ge0"; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins =3D "mpp44", "mpp45", "mpp46", + "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52", + "mpp53", "mpp54", "mpp55"; + marvell,function =3D "ge1"; + }; + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { + marvell,pins =3D "mpp43"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins =3D "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; + marvell,function =3D "spi1"; + }; + nand_pins: nand-pins { + marvell,pins =3D + "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23", "mpp24", + "mpp25", "mpp26", "mpp27"; + marvell,function =3D "dev"; + }; + nand_rb: nand-rb { + marvell,pins =3D "mpp13"; + marvell,function =3D "nf"; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts new file mode 100644 index 0000000..f08a748 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "cn9130-db-A.dts" +#include "cn9131-db.dtsi" + +/ { + model =3D "Marvell CN9131 development board (CP NOR) setup(A)"; + compatible =3D "marvell,cn9131-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +/* CON50 */ +&cp1_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp1_sfp_eth1>; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi new file mode 100644 index 0000000..c8e425a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NUM 1 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1= 000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) + +#include "armada-cp110.dtsi" + +/ { + model =3D "Marvell CN9131 development board"; + compatible =3D "marvell,cn9131-db", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + aliases { + gpio3 =3D &cp1_gpio1; + gpio4 =3D &cp1_gpio2; + ethernet3 =3D &cp1_eth0; + ethernet4 =3D &cp1_eth1; + }; + + cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_xhci0_vbus_pins>; + regulator-name =3D "cp1-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + cp1_usb3_0_phy0: cp1_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp1_reg_usb3_vbus0>; + }; + + cp1_sfp_eth1: sfp-eth1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp1_i2c0>; + los-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfp_pins>; + status =3D "disabled"; + }; +}; + +&cp1_crypto { + status =3D "okay"; +}; + +&cp1_gpio1 { + status =3D "okay"; +}; + +&cp1_gpio2 { + status =3D "okay"; +}; + +&cp1_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_i2c0_pins>; + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +/* CON40 */ +&cp1_pcie0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_pcie_reset_pins>; + num-lanes =3D <2>; + num-viewport =3D <8>; + marvell,reset-gpio =3D <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy0 0 + &cp1_comphy1 0>; +}; + +&cp1_sata0 { + status =3D "okay"; + /* CON32 */ + sata-port@1 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 1>; + }; +}; + +/* U24 */ +&cp1_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_spi0_pins>; + reg =3D <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>; /* CS0 */ + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency =3D <40000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; + +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp1_i2c0_pins: cp1-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp1_spi0_pins: cp1-spi-pins-0 { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; + marvell,function =3D "spi1"; + }; + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { + marvell,pins =3D "mpp3"; + marvell,function =3D "gpio"; + }; + cp1_sfp_pins: sfp-pins { + marvell,pins =3D "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function =3D "gpio"; + }; + cp1_pcie_reset_pins: cp1-pcie-reset-pins { + marvell,pins =3D "mpp0"; + marvell,function =3D "gpio"; + }; + }; +}; + +/* CON58 */ +&cp1_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy3 1>; + phy-names =3D "usb"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts new file mode 100644 index 0000000..e9464f8 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -0,0 +1,76 @@ +/* + * copyright (c) 2019 marvell international ltd. + * + * spdx-license-identifier: gpl-2.0 + * https://spdx.org/licenses + */ + +#include "cn9131-db-A.dts" +#include "cn9132-db.dtsi" + +/ { + model =3D "Model: Marvell CN9132 development board (CP NOR) setup(= A)"; + compatible =3D "marvell,cn9132-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + aliases { + gpio5 =3D &cp2_gpio1; + gpio6 =3D &cp2_gpio2; + ethernet5 =3D &cp2_eth0; + }; +}; + +&cp2_ethernet { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp2_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp2_sfp_eth0>; +}; + +/* SLM-1521-V2, CON6 */ +&cp2_pcie0 { + status =3D "okay"; + num-lanes =3D <2>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy0 0 + &cp2_comphy1 0>; +}; + +/* SLM-1521-V2, CON8 */ +&cp2_pcie2 { + status =3D "okay"; + num-lanes =3D <1>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy5 2>; +}; + +&cp2_sata0 { + status =3D "okay"; + /* SLM-1521-V2, CON4 */ + sata-port@0 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy2 0>; + }; +}; + +/* CON 2 on SLM-1683 - microSD */ +&cp2_sdhci0 { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON11 */ +&cp2_usb3_1 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy3 1>; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi new file mode 100644 index 0000000..8613607 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -0,0 +1,151 @@ +/* + * copyright (c) 2019 marvell international ltd. + * + * spdx-license-identifier: gpl-2.0 + * https://spdx.org/licenses + */ + +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NUM 2 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1= 000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) + +#include "armada-cp110.dtsi" + +/ { + model =3D "DB-CN-9132"; + compatible =3D "marvell,cn9132", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp2-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + cp2_usb3_0_phy0: cp2_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp2_reg_usb3_vbus0>; + }; + + cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp2-xhci1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + cp2_usb3_0_phy1: cp2_usb3_phy1 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp2_reg_usb3_vbus1>; + }; + + cp2_reg_sd_vccq: cp2_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp2_sd_vcc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 3300000 0x0>; + }; + + cp2_sfp_eth0: sfp-eth0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp2_sfpp0_i2c>; + los-gpio =3D <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp2_moudle_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp2_moudle_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIG= H>; + status =3D "disabled"; + }; +}; + +&cp2_crypto { + status =3D "okay"; +}; + +&cp2_gpio1 { + status =3D "okay"; +}; + +&cp2_gpio2 { + status =3D "okay"; +}; + +&cp2_i2c0 { + clock-frequency =3D <100000>; + + /* SLM-1521-V2 - U3 */ + i2c-mux@72 { + compatible =3D "nxp,pca9544"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x72>; + cp2_sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + /* U12 */ + cp2_moudle_expander1: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + }; + }; +}; + +&cp2_sdhci0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp2_sdhci_pins>; + bus-width =3D <4>; + cd-gpios =3D <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; + vqmmc-supply =3D <&cp2_reg_sd_vccq>; +}; + +&cp2_syscon0 { + cp2_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp2_i2c0_pins: cp2-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp2_sdhci_pins: cp2-sdhi-pins-0 { + marvell,pins =3D "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + }; +}; + +&cp2_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp2_usb3_0_phy0>; + phy-names =3D "usb"; +}; + +&cp2_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp2_usb3_0_phy1>; + phy-names =3D "usb"; +}; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48692): https://edk2.groups.io/g/devel/message/48692 Mute This Topic: https://groups.io/mt/34471894/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 13:43:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48691+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48691+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686114; cv=none; d=zoho.com; s=zohoarc; b=Bi//96TjlA4TD4PIh4ZjOnCausNvz7aek0z4LZsDXNJ5Efmn1bIltEdiRY+VnDrwS2z2m8HA3imFmVngiHXvUPk4vii8mrAaKkWzJEFuhrOdgtpll1GqtOAcS3O/0QEevRVhdAaTrmg5reRuWndCEyBPRhNou0jCqYbFxG3emz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686114; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=6ExdGx38mHG1iKYXsh8I+rpAma3CjJDXL36LGcHOGas=; b=Gf+PMsjgmOMbI0yPiW4+RQnwZAO5MCAv9Ke5rHp1y9UaXAlwy/wOUbXyyyL+xEuQN+ieCserSBwcFW28ZoANRb6zsVeRiOaaWEPJmJaROb565CKKFfWKMyyrDTB+Iu9ucS1b3C17cJ1r8ZelhTd0xbgR/ApmUhagVQMsATaak50= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48691+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686114534515.5801125520818; Wed, 9 Oct 2019 22:41:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:41:54 -0700 X-Received: from mail-lf1-f67.google.com (mail-lf1-f67.google.com [209.85.167.67]) by mx.groups.io with SMTP id smtpd.web12.2515.1570686113303739297 for ; Wed, 09 Oct 2019 22:41:53 -0700 X-Received: by mail-lf1-f67.google.com with SMTP id w6so3384738lfl.2 for ; Wed, 09 Oct 2019 22:41:53 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqyxT6Dgq2Mw/K5d+bqwgXDKjubtVZW3RRz66/0WtE4kEAQJEbvEdDAB9laAZckV5NV4aZduxg== X-Received: by 2002:a05:6512:74:: with SMTP id i20mr4520065lfo.97.1570686111267; Wed, 09 Oct 2019 22:41:51 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27sm950028ljd.55.2019.10.09.22.41.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:41:50 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-non-osi: PATCH 2/3] Marvell/Cn9131Db: Add DeviceTree Date: Thu, 10 Oct 2019 07:41:17 +0200 Message-Id: <1570686078-25140-3-git-send-email-mw@semihalf.com> In-Reply-To: <1570686078-25140-1-git-send-email-mw@semihalf.com> References: <1570686078-25140-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686114; bh=MN6OhjM+Xklf84dV7IWBqZ54QIDaOv2bfzmbw2VEGLI=; h=Cc:Date:From:Reply-To:Subject:To; b=itq7kCgv1G0nYoMgdgc3sus6Lzb/IVCHoTdIE2Pcp5xiTb9Pp4r2CeVJVtcquafrs9P a8be2e0ukOstfHh/TRAYnI8W8JwSKCcoCutHpm6RI3VaRE/FlszNKxSI8fNjqeOla1CeM nU2ii/V45wRSDUkyVFN8Mo+cjtdTByl4gI0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adjusts the top device tree for the CN9131 development board (variant A), based on the sources which are common for the Cn913x SoCs. Also an .inf file is added to allow its compilation. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf | 22 ++++++++++++++= +++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 26 +++++++++++---= ------ 2 files changed, 36 insertions(+), 12 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf new file mode 100644 index 0000000..8108197 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9131DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9131-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi index c8e425a..9c9dfb6 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi @@ -6,15 +6,23 @@ */ =20 #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE =20 /* CP110-1 Settings */ +#define CP110_NAME cp1 #define CP110_NUM 1 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1= 000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) +#define CP110_BASE f4000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) =20 #include "armada-cp110.dtsi" =20 @@ -93,12 +101,6 @@ =20 &cp1_sata0 { status =3D "okay"; - /* CON32 */ - sata-port@1 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 1>; - }; }; =20 /* U24 */ @@ -138,7 +140,7 @@ =20 &cp1_syscon0 { cp1_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; + compatible =3D "marvell,armada-7k-pinctrl"; =20 cp1_i2c0_pins: cp1-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48691): https://edk2.groups.io/g/devel/message/48691 Mute This Topic: https://groups.io/mt/34471893/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 13:43:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48693+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48693+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1570686116; cv=none; d=zoho.com; s=zohoarc; b=Uda8YTAwgfQ+n5iruzosDrgfCGnL8/SrLwC2wKBEj72+AF+CR/zHPOIhcc8Th7kdQK+h5qo2NeGO1Dvmo0x6fnb1KokJu3xQJzfu3qduHZZNEJJ+5mklMiaeOscVkeoBoELoLtvoFvV6rWFbPuZcA6wR0NZHn9jSQE5Vwu0q1pE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570686116; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Wkuy8nmFKqJJ9Ee4xloO3ef9ov+bqKNbQcydS0pNNaE=; b=BKhGFLPpI4pWpix/Wxr4kkEYqJON1Ebn1G2qCbOp9/YRUtl161Qk2NHECppgHyxF1TwiP+HeSNX4IP4ip2qwPPu05ZbNPCdd12CujXujNHW/sCIDoMo/08iHthnwkeJzJgrvuJY3MSgpwWijVMOD8R3ci3vs7xXkJGNab36lLNA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48693+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570686116107732.3779784237248; Wed, 9 Oct 2019 22:41:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Wed, 09 Oct 2019 22:41:55 -0700 X-Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by mx.groups.io with SMTP id smtpd.web12.2518.1570686114555518252 for ; Wed, 09 Oct 2019 22:41:54 -0700 X-Received: by mail-lj1-f193.google.com with SMTP id m13so4810041ljj.11 for ; Wed, 09 Oct 2019 22:41:54 -0700 (PDT) X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= X-Google-Smtp-Source: APXvYqz4OaUWIPLDKss6epr/pNogYSvL6GX6x6g8TVSAQybp6Pc8+8/PQujoJ1CSSmm+XUUmK6Xlww== X-Received: by 2002:a2e:89c9:: with SMTP id c9mr4811496ljk.108.1570686112533; Wed, 09 Oct 2019 22:41:52 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27sm950028ljd.55.2019.10.09.22.41.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:41:51 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-non-osi: PATCH 3/3] Marvell/Cn9132Db: Add DeviceTree Date: Thu, 10 Oct 2019 07:41:18 +0200 Message-Id: <1570686078-25140-4-git-send-email-mw@semihalf.com> In-Reply-To: <1570686078-25140-1-git-send-email-mw@semihalf.com> References: <1570686078-25140-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570686115; bh=RgBTEevxXmPdr/tBlLu8eVOW5awAYmH5Ga3EVfFSgMY=; h=Cc:Date:From:Reply-To:Subject:To; b=gcm13fN3FSVsvp4rwy8tw7Z1amhcz9GnpLs3cQP2MABj6gPVUVOx0a6J7+A3jCvK07i ElC9MbgYIBKqgsApT8i/RKom/CIxk5+IcP78brrhPuXgBj0Zz0/6pnrrdqRx5xwEJoJ/s AYYuLGI3pN5Sz5kGs03DS1wFCfSqOLcqKvk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adjusts the top device tree for the CN9132 development board (variant A), based on the sources which are common for the Cn913x SoCs. Also an .inf file is added to allow its compilation. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 +++++++++++++= +++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++++++++++++-= ----- 3 files changed, 36 insertions(+), 12 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf new file mode 100644 index 0000000..c9e3b04 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9132DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9132-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts index e9464f8..724d7dc 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -55,12 +55,6 @@ =20 &cp2_sata0 { status =3D "okay"; - /* SLM-1521-V2, CON4 */ - sata-port@0 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy2 0>; - }; }; =20 /* CON 2 on SLM-1683 - microSD */ diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi index 8613607..7dc6c6e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -6,15 +6,23 @@ */ =20 #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE =20 /* CP110-1 Settings */ +#define CP110_NAME cp2 #define CP110_NUM 2 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1= 000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) +#define CP110_BASE f6000000 +#define CP110_PCIE0_BASE f6600000 +#define CP110_PCIE1_BASE f6620000 +#define CP110_PCIE2_BASE f6640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) =20 #include "armada-cp110.dtsi" =20 @@ -124,7 +132,7 @@ =20 &cp2_syscon0 { cp2_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; + compatible =3D "marvell,armada-7k-pinctrl"; =20 cp2_i2c0_pins: cp2-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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