From nobody Mon Feb 9 09:52:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47788+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47788+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569211879; cv=none; d=zoho.com; s=zohoarc; b=RD9t3bEgATbFpNPSdTu1nTG8Jl1fq2dA4PdCq6jcTBKXCZoHDFp4/itjtcwSrEBMoQ0wSuyVlQA7hVJffaGJrI6l+23dEJB33HWhzRc1OtQsAHv49+N6UcZ/ioWYhtb5R/+zSMntpNYtNshNFS3ft4NuHhZMZqzleOvxAnqnGGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569211879; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=xRasqjbKie77SvDkpv0gtPuT26j271O1uVhmXXvzyDc=; b=eXxHH92Yo2JNIfdajfD/j6gWLqLRjvW1NIsPRK/X1ft9OZ8o4wBFoSaS1ErKIpoRXjTMqa6gASPa7k2i8MQlBpJm28zu218rjrE9M1ZwQ50U96mY8kdt4fQ0Zbm/dr4K1vXLCjrn27hcLdOapVpPfwNbbQtLhXN/LLa7Z3oZIZ4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47788+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569211879630894.6947609037958; Sun, 22 Sep 2019 21:11:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Zs9RYY1788612xvhO61wMVuE; Sun, 22 Sep 2019 21:11:19 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 21:11:18 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N4BHSH015166; Mon, 23 Sep 2019 04:11:17 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v6ha4vvm9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Sep 2019 04:11:17 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id B299B51; Mon, 23 Sep 2019 04:11:16 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 4EDAD45; Mon, 23 Sep 2019 04:11:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-devel] [platforms/devel-riscv-v2 PATCHv3 01/13] U500Pkg/OpenSbiPlatformLib: Use Fdtlib in EmbeddedPkg Date: Mon, 23 Sep 2019 11:40:25 +0800 Message-Id: <1569210037-32285-2-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569210037-32285-1-git-send-email-abner.chang@hpe.com> References: <1569210037-32285-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: H4H35EfsxO9N43vEiGuH9EdXx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569211879; bh=KMZWx0l2Jcn7YNHgPmbIz+mtC2a0Fu0YxBSfLvdeD8M=; h=Cc:Date:From:Reply-To:Subject:To; b=hsWgo/CRnavBUI0xGrCtrTp39hmIX5w2XZ2oKg9laLE4LLG/BxdT+tumLMk0lY4BqcU 04g6t/8qfJMlrPk98flXzg0nWYH81kw5XfbFmvcX/jkzKGfu72SHuBakJUiQhxkjhNctO MqfGw+Nds4y4pezgbdjThBEoJWkk4OSuNCM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use Fdtlib in EmbeddedPkg instead of using OpenSbi one. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 8 +- .../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 242 +++++++++++------= ---- 2 files changed, 127 insertions(+), 123 deletions(-) diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenS= biPlatformLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/OpenSbiPlatformLib.inf index 473386d..1b20b89 100644 --- a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatf= ormLib.inf +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatf= ormLib.inf @@ -30,16 +30,18 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec RiscVPkg/RiscVPkg.dec + EmbeddedPkg/EmbeddedPkg.dec Platform/RiscV/RiscVPlatformPkg.dec =20 [LibraryClasses] BaseLib - DebugLib BaseMemoryLib - PcdLib + DebugLib DebugAgentLib - RiscVCpuLib + FdtLib + PcdLib PrintLib + RiscVCpuLib =20 [FixedPcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platf= orm.c b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c index 4dca75f..eaaa2d5 100644 --- a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c @@ -1,7 +1,9 @@ /* - * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+ * + * SPDX-License-Identifier: BSD-2-Clause + * * Copyright (c) 2019 Western Digital Corporation or its affiliates. * * Authors: @@ -22,193 +24,193 @@ =20 =20 #define U500_HART_COUNT FixedPcdGet32(PcdHartCount) -#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) +#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) #define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) =20 -#define U500_SYS_CLK 100000000 +#define U500_SYS_CLK 100000000 =20 #define U500_CLINT_ADDR 0x2000000 =20 -#define U500_PLIC_ADDR 0xc000000 -#define U500_PLIC_NUM_SOURCES 0x35 -#define U500_PLIC_NUM_PRIORITIES 7 +#define U500_PLIC_ADDR 0xc000000 +#define U500_PLIC_NUM_SOURCES 0x35 +#define U500_PLIC_NUM_PRIORITIES 7 =20 -#define U500_UART_ADDR 0x54000000 +#define U500_UART_ADDR 0x54000000 =20 -#define U500_UART_BAUDRATE 115200 +#define U500_UART_BAUDRATE 115200 =20 /** * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode. * HARTs 1 is selected as boot HART */ #ifndef U500_ENABLED_HART_MASK -#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID) +#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID) #endif =20 -#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK) +#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK) =20 /* PRCI clock related macros */ //TODO: Do we need a separate driver for this ? #define U500_PRCI_BASE_ADDR 0x10000000 #define U500_PRCI_CLKMUXSTATUSREG 0x002C -#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) +#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) =20 static void U500_modify_dt(void *fdt) { - u32 i, size; - int chosen_offset, err; - int cpu_offset; - char cpu_node[32] =3D ""; - const char *mmu_type; - - for (i =3D 0; i < U500_HART_COUNT; i++) { - sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); - cpu_offset =3D fdt_path_offset(fdt, cpu_node); - mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); - if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") || - !strcmp(mmu_type,"riscv,sv48"))) - continue; - else - fdt_setprop_string(fdt, cpu_offset, "status", "masked"); - memset(cpu_node, 0, sizeof(cpu_node)); - } - size =3D fdt_totalsize(fdt); - err =3D fdt_open_into(fdt, fdt, size + 256); - if (err < 0) - sbi_printf("Device Tree can't be expanded to accmodate new node"); - - chosen_offset =3D fdt_path_offset(fdt, "/chosen"); - fdt_setprop_string(fdt, chosen_offset, "stdout-path", - "/soc/serial@10010000:115200"); - - plic_fdt_fixup(fdt, "riscv,plic0"); + u32 i, size; + int chosen_offset, err; + int cpu_offset; + char cpu_node[32] =3D ""; + const char *mmu_type; + + for (i =3D 0; i < U500_HART_COUNT; i++) { + sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); + cpu_offset =3D fdt_path_offset(fdt, cpu_node); + mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); + if (mmu_type && (!sbi_strcmp(mmu_type, "riscv,sv39") || + !sbi_strcmp(mmu_type,"riscv,sv48"))) + continue; + else + fdt_setprop_string(fdt, cpu_offset, "status", "masked"); + sbi_memset(cpu_node, 0, sizeof(cpu_node)); + } + size =3D fdt_totalsize(fdt); + err =3D fdt_open_into(fdt, fdt, size + 256); + if (err < 0) + sbi_printf("Device Tree can't be expanded to accmodate new node"); + + chosen_offset =3D fdt_path_offset(fdt, "/chosen"); + fdt_setprop_string(fdt, chosen_offset, "stdout-path", + "/soc/serial@10010000:115200"); + + plic_fdt_fixup(fdt, "riscv,plic0"); } =20 static int U500_final_init(bool cold_boot) { - void *fdt; + void *fdt; =20 - if (!cold_boot) - return 0; + if (!cold_boot) + return 0; =20 - fdt =3D sbi_scratch_thishart_arg1_ptr(); - U500_modify_dt(fdt); + fdt =3D sbi_scratch_thishart_arg1_ptr(); + U500_modify_dt(fdt); =20 - return 0; + return 0; } =20 static u32 U500_pmp_region_count(u32 hartid) { - return 1; + return 1; } =20 static int U500_pmp_region_info(u32 hartid, u32 index, - ulong *prot, ulong *addr, ulong *log2size) + ulong *prot, ulong *addr, ulong *log2size) { - int ret =3D 0; - - switch (index) { - case 0: - *prot =3D PMP_R | PMP_W | PMP_X; - *addr =3D 0; - *log2size =3D __riscv_xlen; - break; - default: - ret =3D -1; - break; - }; - - return ret; + int ret =3D 0; + + switch (index) { + case 0: + *prot =3D PMP_R | PMP_W | PMP_X; + *addr =3D 0; + *log2size =3D __riscv_xlen; + break; + default: + ret =3D -1; + break; + }; + + return ret; } =20 static int U500_console_init(void) { - unsigned long peri_in_freq; + unsigned long peri_in_freq; =20 - peri_in_freq =3D U500_SYS_CLK/2; - return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRAT= E); + peri_in_freq =3D U500_SYS_CLK/2; + return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRA= TE); } =20 static int U500_irqchip_init(bool cold_boot) { - int rc; - u32 hartid =3D sbi_current_hartid(); - - if (cold_boot) { - rc =3D plic_cold_irqchip_init(U500_PLIC_ADDR, - U500_PLIC_NUM_SOURCES, - U500_HART_COUNT); - if (rc) - return rc; - } - - return plic_warm_irqchip_init(hartid, - (hartid) ? (2 * hartid - 1) : 0, - (hartid) ? (2 * hartid) : -1); + int rc; + u32 hartid =3D sbi_current_hartid(); + + if (cold_boot) { + rc =3D plic_cold_irqchip_init(U500_PLIC_ADDR, + U500_PLIC_NUM_SOURCES, + U500_HART_COUNT); + if (rc) + return rc; + } + + return plic_warm_irqchip_init(hartid, + (hartid) ? (2 * hartid - 1) : 0, + (hartid) ? (2 * hartid) : -1); } =20 static int U500_ipi_init(bool cold_boot) { - int rc; + int rc; =20 - if (cold_boot) { - rc =3D clint_cold_ipi_init(U500_CLINT_ADDR, - U500_HART_COUNT); - if (rc) - return rc; + if (cold_boot) { + rc =3D clint_cold_ipi_init(U500_CLINT_ADDR, + U500_HART_COUNT); + if (rc) + return rc; =20 - } + } =20 - return clint_warm_ipi_init(); + return clint_warm_ipi_init(); } =20 static int U500_timer_init(bool cold_boot) { - int rc; + int rc; =20 - if (cold_boot) { - rc =3D clint_cold_timer_init(U500_CLINT_ADDR, - U500_HART_COUNT); - if (rc) - return rc; - } + if (cold_boot) { + rc =3D clint_cold_timer_init(U500_CLINT_ADDR, + U500_HART_COUNT); + if (rc) + return rc; + } =20 - return clint_warm_timer_init(); + return clint_warm_timer_init(); } =20 static int U500_system_down(u32 type) { - /* For now nothing to do. */ - return 0; + /* For now nothing to do. */ + return 0; } =20 const struct sbi_platform_operations platform_ops =3D { - .pmp_region_count =3D U500_pmp_region_count, - .pmp_region_info =3D U500_pmp_region_info, - .final_init =3D U500_final_init, - .console_putc =3D sifive_uart_putc, - .console_getc =3D sifive_uart_getc, - .console_init =3D U500_console_init, - .irqchip_init =3D U500_irqchip_init, - .ipi_send =3D clint_ipi_send, - .ipi_sync =3D clint_ipi_sync, - .ipi_clear =3D clint_ipi_clear, - .ipi_init =3D U500_ipi_init, - .timer_value =3D clint_timer_value, - .timer_event_stop =3D clint_timer_event_stop, - .timer_event_start =3D clint_timer_event_start, - .timer_init =3D U500_timer_init, - .system_reboot =3D U500_system_down, - .system_shutdown =3D U500_system_down + .pmp_region_count =3D U500_pmp_region_count, + .pmp_region_info =3D U500_pmp_region_info, + .final_init =3D U500_final_init, + .console_putc =3D sifive_uart_putc, + .console_getc =3D sifive_uart_getc, + .console_init =3D U500_console_init, + .irqchip_init =3D U500_irqchip_init, + .ipi_send =3D clint_ipi_send, + .ipi_sync =3D clint_ipi_sync, + .ipi_clear =3D clint_ipi_clear, + .ipi_init =3D U500_ipi_init, + .timer_value =3D clint_timer_value, + .timer_event_stop =3D clint_timer_event_stop, + .timer_event_start =3D clint_timer_event_start, + .timer_init =3D U500_timer_init, + .system_reboot =3D U500_system_down, + .system_shutdown =3D U500_system_down }; =20 const struct sbi_platform platform =3D { - .opensbi_version =3D OPENSBI_VERSION, // The OpenSBI= version this platform table is built bassed on. - .platform_version =3D SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI = Platform version 1.0 - .name =3D "SiFive Freedom U500", - .features =3D SBI_PLATFORM_DEFAULT_FEATURES, - .hart_count =3D U500_HART_COUNT, - .hart_stack_size =3D U500_HART_STACK_SIZE, - .disabled_hart_mask =3D U500_HARTID_DISABLED, - .platform_ops_addr =3D (unsigned long)&platform_ops + .opensbi_version =3D OPENSBI_VERSION, // The O= penSBI version this platform table is built bassed on. + .platform_version =3D SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI P= latform version 1.0 + .name =3D "SiFive Freedom U500", + .features =3D SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count =3D U500_HART_COUNT, + .hart_stack_size =3D U500_HART_STACK_SIZE, + .disabled_hart_mask =3D U500_HARTID_DISABLED, + .platform_ops_addr =3D (unsigned long)&platform_ops }; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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