From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47751+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47751+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200555; cv=none; d=zoho.com; s=zohoarc; b=MrxEIOPGnj8w6TapRHtYs6bE2hz5CVBQ992qms9QhLIUf/e0OEHlhd6TGYiennLuMGWRFiUm6dp8cDJtBo4Bfmt4PqJc6KZeHURbfOPaSfIhAmICQMltkuDlpqU+3gfWZzceamJNq7yPcNXrw+dhiH91njM421wmQFu+/vqqlj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200555; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=h8M8Iiankom7YHPThiUk00XFZrR8ihn9l3qiejzG2Ws=; b=hDJAsaT86hfM7P+KunLij0nxL01tluFLV/NivpeJG9uLSE9TxgI9ywuYoOP7kJi5yz81sDmoH7H+q2tdbsgw+Cuscz4PvIQhazUEVe9K5xDLCqpOyEnsMjepvIinbB4pjMY5Ry9SLFdNSloQl1cEtEF6uT5BCRYuUeuJ9qXlcJI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47751+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200555532144.094150428513; Sun, 22 Sep 2019 18:02:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BLHQYY1788612xOjOwajzvL9; Sun, 22 Sep 2019 18:02:35 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:34 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N116jO017331 for ; Mon, 23 Sep 2019 01:02:34 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5sxd7gvn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:33 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 540575C for ; Mon, 23 Sep 2019 01:02:33 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 39AD345; Mon, 23 Sep 2019 01:02:32 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package. Date: Mon, 23 Sep 2019 08:31:26 +0800 Message-Id: <1569198715-31552-2-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: En0oGmE1wSIAwzoYL1P4dhm3x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200555; bh=z+/wohi+nK1s+toy9dR07WOVi1puiQBUg1bKPJfHEb8=; h=Cc:Date:From:Reply-To:Subject:To; b=GBARTb/MM+tpvhuwHBSNPDs8NGOkndsrBUKM7glokCsHWPhHxIJncwZRjBAshZCwKhU WfikHy6zVT+JzcpjPRpPVP1GSw4E6bC4rYbzNZ3OEQMdoTttbBL9zdh5HZu5b9TutSNvH sJ3h//OCFM0C+VS/jVLOmxWZJyCxr44uDbc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Add RiscVPkg package which provides RISC-V processor related drivers and libraries. - Support RISC-V OpenSBI and RISC-V platforms Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- RiscVPkg/RiscVPkg.dec | 27 +++++++++++++++++++++++++++ RiscVPkg/RiscVPkg.uni | 13 +++++++++++++ RiscVPkg/RiscVPkgExtra.uni | 13 +++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 RiscVPkg/RiscVPkg.dec create mode 100644 RiscVPkg/RiscVPkg.uni create mode 100644 RiscVPkg/RiscVPkgExtra.uni diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec new file mode 100644 index 0000000..74314e8 --- /dev/null +++ b/RiscVPkg/RiscVPkg.dec @@ -0,0 +1,27 @@ +## @file RiscVPkg.dec +# This Package provides UEFI RISC-V modules and libraries. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001b + PACKAGE_NAME =3D RiscVPkg + PACKAGE_UNI_FILE =3D RiscVPkg.uni + PACKAGE_GUID =3D 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1 + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + opensbi # OpebSBI header file reference ("include/= sbi/...") + opensbi/include # Header file reference from opensbi files= , ("sbi/...") + opensbi/lib/utils/libfdt + +[Guids] + gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPkgExtra.uni diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni new file mode 100644 index 0000000..5ec7a99 --- /dev/null +++ b/RiscVPkg/RiscVPkg.uni @@ -0,0 +1,13 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI com= patible RISC-V modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package prov= ides UEFI compatible RISC-V modules and libraries." + diff --git a/RiscVPkg/RiscVPkgExtra.uni b/RiscVPkg/RiscVPkgExtra.uni new file mode 100644 index 0000000..b50a6b4 --- /dev/null +++ b/RiscVPkg/RiscVPkgExtra.uni @@ -0,0 +1,13 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"RiscV package" + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47751): https://edk2.groups.io/g/devel/message/47751 Mute This Topic: https://groups.io/mt/34258191/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47752+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47752+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200556; cv=none; d=zoho.com; s=zohoarc; b=Ntr1qerYo67QXnmzLDP7iudg8MnEX9a0zQFzFHhbkt6HVZ2FUE7Zg0+m4lTjOflD5YT7KN6MDDDlKCt2wxKigmQXAlDxivEbhpO2WJTblZxTTFNARUz7pc7du+OJpnuPkc8l3zjj2va7YZhqUNYBHJwVTFsbsU064+w4lEsHEJU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200556; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=71wwVK+VvCjsiLB2Gf8H8iYnZa4WP3RrseTQwbBXA4A=; b=Hw7Vn2dhWfMgHnDo596uPRwku0rTXb7EV2NwsGEG437JcpTcjxcnfw/f2MvGwxf/uAdB+8uqSeT5wSa0P+Dt5v+5D8I3OPkYb8Phxw8+/w0gPgvWmvmPWkOXPF4QAVU7F3Hr+WKatd6tou9fwKq68vIITHOoAOg/p1rACjXIKaw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47752+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200556907712.7199623276678; Sun, 22 Sep 2019 18:02:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aKUCYY1788612xuScGA27f4U; Sun, 22 Sep 2019 18:02:36 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:36 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114PA006835 for ; Mon, 23 Sep 2019 01:02:35 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb1u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:35 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 74B645C for ; Mon, 23 Sep 2019 01:02:34 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8917F45; Mon, 23 Sep 2019 01:02:33 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Date: Mon, 23 Sep 2019 08:31:27 +0800 Message-Id: <1569198715-31552-3-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 5nkh5zzYgdlqpu530cVYgS1dx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200556; bh=i2XWVSEafCe9cbDsyeiPTC2+7WasXvjYhxx7eo72hMk=; h=Cc:Date:From:Reply-To:Subject:To; b=ZMVr+EzZpQEhBgQ1IoflyxL+Hyfbk0suw5+WcQ4kztWE2n1btasQr2UmvHJNjQE8FfN EuxxRQHANBB22NjKHBd81+n9ULjg4ReMWxQ4SjIvRzBS713OBpTKL83U2cHwv9y87Jmu6 QhlcG+EFTj9byrRqdjQhBPlfK61xwoqVFfk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" RISC-V package library definitions. IndustryStandard/RiscV.h -Add RiscV.h which conform with RISC-V Privilege Spec v1.10. RiscV.h -Definition of EDK2 RISC-V implementation. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- RiscVPkg/Include/IndustryStandard/RiscV.h | 102 ++++++++++++++++++++++++++= ++++ RiscVPkg/Include/RiscV.h | 72 +++++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h create mode 100644 RiscVPkg/Include/RiscV.h diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/I= ndustryStandard/RiscV.h new file mode 100644 index 0000000..d4d5002 --- /dev/null +++ b/RiscVPkg/Include/IndustryStandard/RiscV.h @@ -0,0 +1,102 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RISCV_INDUSTRY_STANDARD_H_ +#define _RISCV_INDUSTRY_STANDARD_H_ + +#if defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x0000000= 1 << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +//#define RISCV_CSR_MACHINE_MTIME 0x701 +//#define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +#endif diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h new file mode 100644 index 0000000..1c3ab55 --- /dev/null +++ b/RiscVPkg/Include/RiscV.h @@ -0,0 +1,72 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RISCV_H_ +#define _RISCV_H_ + +#include + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap ha= ndler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap= handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap= handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handl= er. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine = mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47752): https://edk2.groups.io/g/devel/message/47752 Mute This Topic: https://groups.io/mt/34258192/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47753+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47753+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200557; cv=none; d=zoho.com; s=zohoarc; b=hCMLv7Y0kq9CDRWdZCqkvrlGxzo45P27Ylq+yvcrijBXlbAWQvc6LvzFfMUnu97cBcncWGpiMuqW+/ns0ABGIxUiOsnL6aAiUSZaFO2ngvn1hpRjx7Sn5H1pVcn1kQ0ujrrSYd+8RNLBo6mkHomZzOrmjJSZYHk4qLx+ZZZyVSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200557; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SGL6RWGqmFZhxYm6TtHhSPkbAszPvnrHbJGf8rdIBto=; b=PNYOsAJpI9nCJU1COvBA/7IvhFIzboZD0JF4duUg/Omv52gsJCJzqRtZyGWo7ygFLauDfMSEDoX175UPkCKriV65RnSzenjay3Fumgf6Wl5aZ4DEPF8UWUPmBf1rqMPVLUMB6JK+YtaBCDpRoX6+ebySW1igWHbL+kQzzJptswU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47753+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200557964791.4035102214408; Sun, 22 Sep 2019 18:02:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cJSjYY1788612xDHp2RBsnMM; Sun, 22 Sep 2019 18:02:37 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:37 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114RG007656 for ; Mon, 23 Sep 2019 01:02:36 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7tq7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:36 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id C55BC5C for ; Mon, 23 Sep 2019 01:02:35 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id DCFC645; Mon, 23 Sep 2019 01:02:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Date: Mon, 23 Sep 2019 08:31:28 +0800 Message-Id: <1569198715-31552-4-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: NjGPdD9z0xkH03NLxKM3jKQcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200557; bh=Ly5yN5wc9BSM2ob7l6XEaC9XnoFuQWsOut776bTo7ok=; h=Cc:Date:From:Reply-To:Subject:To; b=ed8Vw70gSHN87Uz/nALr7zkfVgorcA2XF2By27WXun/GYcPgPF1hq56UgWV6sZd5xSI l6TM+4OuYzPTeVSdfFrAdJ3UWAKGEna8LhFy/EIQkGI1q4qy5/bkaFRtePNPopgER8vJH e1/qYBmwqqh9uhzzOOdNBMwBgkwOO7xgu5M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add EDK2 RISC-V OpenSBI header files and opensbi-HOWTO.txt for users to bui= ld RISC-V platform with RISC-V OpenSBI library. Signed-off-by: Abner Chang --- RiscVPkg/Include/sbi/SbiFirmwareContext.h | 38 ++++++++++++ RiscVPkg/Include/sbi/sbi.h | 96 +++++++++++++++++++++++++++= ++++ RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++ RiscVPkg/Include/sbi/sbi_types.h | 18 ++++++ 4 files changed, 169 insertions(+) create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h create mode 100644 RiscVPkg/Include/sbi/sbi_types.h diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/s= bi/SbiFirmwareContext.h new file mode 100644 index 0000000..498faf4 --- /dev/null +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h @@ -0,0 +1,38 @@ +/** @file + RISC-V OpesbSBI Platform Firmware context definition + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SBI_FIRMWARE_CONTEXT_H_ +#define _SBI_FIRMWARE_CONTEXT_H_ + +#include + +#define RISC_V_MAX_HART_SUPPORTED 16 + +// +// keep the structure member in 64-bit alignment. +// +#pragma pack(push) +#pragma pack(8) + +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension this core= supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture ID + RISCV_UINT128 MachineImplId; // Machine Implementation ID +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; + +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7) + +typedef struct { + VOID *PeiServiceTable; // PEI Service table + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +#pragma pack(pop) +#endif + diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index 0000000..89d5016 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi.h @@ -0,0 +1,96 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SBI_H_ +#define _SBI_H_ + +#include // Reference to header file wrapper +#include // Reference to header file in opensbi + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CALL(which, arg0, arg1, arg2) ({ \ + register uintptr_t a0 asm ("a0") =3D (uintptr_t)(arg0); \ + register uintptr_t a1 asm ("a1") =3D (uintptr_t)(arg1); \ + register uintptr_t a2 asm ("a2") =3D (uintptr_t)(arg2); \ + register uintptr_t a7 asm ("a7") =3D (uintptr_t)(which); \ + asm volatile ("ecall" \ + : "+r" (a0) \ + : "r" (a1), "r" (a2), "r" (a7) \ + : "memory"); \ + a0; \ +}) + +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0) +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0) + +static inline void sbi_console_putchar(int ch) +{ + SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch); +} + +static inline int sbi_console_getchar(void) +{ + return SBI_CALL_0(SBI_CONSOLE_GETCHAR); +} + +static inline void sbi_set_timer(uint64_t stime_value) +{ +#if __riscv_xlen =3D=3D 32 + SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32); +#else + SBI_CALL_1(SBI_SET_TIMER, stime_value); +#endif +} + +static inline void sbi_shutdown(void) +{ + SBI_CALL_0(SBI_SHUTDOWN); +} + +static inline void sbi_clear_ipi(void) +{ + SBI_CALL_0(SBI_CLEAR_IPI); +} + +static inline void sbi_send_ipi(const unsigned long *hart_mask) +{ + SBI_CALL_1(SBI_SEND_IPI, hart_mask); +} + +static inline void sbi_remote_fence_i(const unsigned long *hart_mask) +{ + SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask); +} + +static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, + unsigned long start, + unsigned long size) +{ + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask); +} + +static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_ma= sk, + unsigned long start, + unsigned long size, + unsigned long asid) +{ + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask); +} + +#endif diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bit= s.h new file mode 100644 index 0000000..1e6bda3 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_bits.h @@ -0,0 +1,17 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _EDK2_SBI_BITS_H_ +#define _EDK2_SBI_BITS_H_ + +#undef MAX +#undef MIN + +#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi + +#endif diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_ty= pes.h new file mode 100644 index 0000000..d7ff227 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_types.h @@ -0,0 +1,18 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _EDK2_SBI_TYPES_H_ +#define _EDK2_SBI_TYPES_H_ + +#undef TRUE +#undef FALSE +#undef NULL + +#include "opensbi/include/sbi/sbi_types.h" // Reference to header file in = opensbi + +#endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47753): https://edk2.groups.io/g/devel/message/47753 Mute This Topic: https://groups.io/mt/34258194/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47754+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47754+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200560; cv=none; d=zoho.com; s=zohoarc; b=BP9RU+8+HNm86YTuh0wo1ZX1ZWK3gbOvwrcdNy39DYx+gCjpgqOlytMRCQupyo19Gegutot8l5G4awptkoEOTnRZbBFiNfO6zRlNWSxyHQXA3o1csxzKLXY0jxzuPYuvAo/X95Ofcs2LqIs/QsY0OzY8ity0tdIyO0GggWLblx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200560; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=XRhAYXi9FFE/X5NpmIuYwG/EkEOnGZD6dF2/AmIavcs=; b=ke/9MxmoJfSdWHQ5mCmQy6J8lWw+aGJ/Mpky3aBMgMa7k2SdcmimAMD8IhYr+6l3tFzEp1B/mbfL2xa9aiipb5VdYpLinpPzAO50UMNDgSvG75ZW/e4nqOBpEulwMDtybdGw85Dxw+58RX6wMdvbcNW9byu33tgg3Txo3aHXAcc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47754+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156920056034369.24753982865286; Sun, 22 Sep 2019 18:02:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BDWsYY1788612xEap8BDq5hz; Sun, 22 Sep 2019 18:02:39 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:38 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N11B9Z003245 for ; Mon, 23 Sep 2019 01:02:37 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v6ha4te0t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:37 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 2360A54 for ; Mon, 23 Sep 2019 01:02:37 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 396EC45; Mon, 23 Sep 2019 01:02:36 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Date: Mon, 23 Sep 2019 08:31:29 +0800 Message-Id: <1569198715-31552-5-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: TimV0EyK8t4FvO93zvdf7nSJx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200559; bh=dKJKu/2UIuzQFUJm9kL3hrgfHbn0yervQPaQSJcI0Aw=; h=Cc:Date:From:Reply-To:Subject:To; b=mcojgrZcc58ZnVddzMxxHI42ESgcl3dVjwfDH80Xy+DZn1sYsRButP18rWfe2WRVpDg HivvchMIYn3f5ztnVCIalCtMMvYw6LeWA/mBNIGIgaPDOJa5j38ie53isDmPf0tCplJyD Se8lkDpEcfP8JuxVV02Ash9nOOEC27NZwbo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++++++= ++++ MdePkg/MdePkg.dec | 5 +- 2 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV6= 4/ProcessorBind.h new file mode 100644 index 0000000..c3d4ef7 --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choic= es +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +/// +/// 8-byte unsigned value +/// +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); +/// +/// 8-byte signed value +/// +typedef long long INT64 __attribute__ ((aligned (8))); +/// +/// 4-byte unsigned value +/// +typedef unsigned int UINT32 __attribute__ ((aligned (4))); +/// +/// 4-byte signed value +/// +typedef int INT32 __attribute__ ((aligned (4))); +/// +/// 2-byte unsigned value +/// +typedef unsigned short UINT16 __attribute__ ((aligned (2))); +/// +/// 2-byte Character. Unless otherwise specified all strings are stored i= n the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 sta= ndards. +/// +typedef unsigned short CHAR16 __attribute__ ((aligned (2))); +/// +/// 2-byte signed value +/// +typedef short INT16 __attribute__ ((aligned (2))); +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE.= Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processo= r instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN __attribute__ ((aligned (8))); +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor = instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN __attribute__ ((aligned (8))); + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal RV64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages in Super= visor mode) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAP= I. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization le= vel + /// The GCC support assumes a GCC compiler that supports the EFI ABI. Th= e EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-= 64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used f= or + /// x64. Warning the assembly code in the MDE x64 does not follow the co= rrect + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EF= I ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a functi= on pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a funct= ion pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 3fd7d16..1aaa97d 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -6,7 +6,7 @@ # # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +39,9 @@ [Includes.AARCH64] Include/AArch64 =20 +[Includes.RISCV64] + Include/RiscV64 + [LibraryClasses] ## @libraryclass Provides most usb APIs to support the Hid requests de= fined in Usb Hid 1.1 spec # and the standard requests defined in Usb 1.1 spec. --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47754): https://edk2.groups.io/g/devel/message/47754 Mute This Topic: https://groups.io/mt/34258195/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47756+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47756+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200564; cv=none; d=zoho.com; s=zohoarc; b=PZvBEbdzASjXnfaFEOe69EwDBRIvBM8b6GxgGRVe55gX9o/KQZ9PnGC7RMzbnFnZ9qfh+zo+fLN1ulzHENorKovlcRg9nqiETnlxqxpgW3lUE7sP9PvQaeDjhrV4cnDE1wEutJVdX3XEwXdBkoz4oSPC2RCweJJMoyBefoGnMu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200564; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=QKGU2vAOBtGVVW7khVd9S3THqjkrXMSlUcmCzc0I2RE=; b=QvqffnQKYU0usUvIZ2vGPKzdO1XdgQngDoioxD6Jcj3gDAuqtVFSY1EtXRdaQJqnXQjjNv6e+SnW4OJ6dQws37m9WzAwvFrfeW0mhdIoRs5zPhLrBxDLKuAMZXRfKH0m4InQSokIqdLW2kFk/OTY3I08cyAKZfErni/szDNeitk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47756+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200564553788.6598587294874; Sun, 22 Sep 2019 18:02:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Ryg1YY1788612xyqIoID6Bdk; Sun, 22 Sep 2019 18:02:44 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:43 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N1138a021557 for ; Mon, 23 Sep 2019 01:02:39 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay2y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:39 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 7487E62 for ; Mon, 23 Sep 2019 01:02:38 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8AE6746; Mon, 23 Sep 2019 01:02:37 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions. Date: Mon, 23 Sep 2019 08:31:30 +0800 Message-Id: <1569198715-31552-6-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: YQIAbNB4HtczKsYW6jd1b9czx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200564; bh=cK8wtuP2FtdCTFAy6RDiWJRbUU8LpmgzEsujzOoduOQ=; h=Cc:Date:From:Reply-To:Subject:To; b=o6SjBNMacfqrM4jWZMIxWmOQ2KvbR38Q0UskYUWxXb1bjs18TqNZDwa4Pk/0RDp8WA3 f52Hrw8B8LP1tisdW37C6vZkkOv5I7H3s2mGELf2+qyKy2vScSHPYw8k/ZgBgdAOy/aVF NTCA+0GlF/FhZ+KzjsrspCEOqBrCyTkdfLk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V processor related definitions. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++ MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++++++= ++++ MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++ MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++ MdePkg/Include/Uefi/UefiSpec.h | 5 +++ 5 files changed, 89 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/Ind= ustryStandard/PeImage.h index 720bb08..ca3fd0b 100644 --- a/MdePkg/Include/IndustryStandard/PeImage.h +++ b/MdePkg/Include/IndustryStandard/PeImage.h @@ -9,6 +9,8 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMAGE_FILE_MACHINE_X64 0x8664 #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 #define IMAGE_FILE_MACHINE_ARM64 0xAA64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 =20 // // EXE file formats @@ -494,6 +499,13 @@ typedef struct { #define EFI_IMAGE_REL_BASED_DIR64 10 =20 /// +/// Relocation types of RISC-V processor. +/// +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 + +/// /// Line number format. /// typedef struct { diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index 800e771..1a29cc0 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -7,6 +7,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -603,6 +604,59 @@ typedef struct { UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; =20 +/// +/// RISC-V processor exception types. +/// +#define EXCEPT_RISCV_INST_MISALIGNED 0 +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 +#define EXCEPT_RISCV_ILLEGAL_INST 2 +#define EXCEPT_RISCV_BREAKPOINT 3 +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 + +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 +#define EXCEPT_RISCV_TIMER_INT 0x1 + +typedef struct { + UINT64 X0; + UINT64 X1; + UINT64 X2; + UINT64 X3; + UINT64 X4; + UINT64 X5; + UINT64 X6; + UINT64 X7; + UINT64 X8; + UINT64 X9; + UINT64 X10; + UINT64 X11; + UINT64 X12; + UINT64 X13; + UINT64 X14; + UINT64 X15; + UINT64 X16; + UINT64 X17; + UINT64 X18; + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 X29; + UINT64 X30; + UINT64 X31; +} EFI_SYSTEM_CONTEXT_RISCV64; =20 /// /// Universal EFI_SYSTEM_CONTEXT definition. @@ -614,6 +668,7 @@ typedef union { EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; } EFI_SYSTEM_CONTEXT; =20 // diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protoco= l/PxeBaseCode.h index b02d270..8a9e4a1 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -3,6 +3,8 @@ devices for network access and network booting. =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A #elif defined (MDE_CPU_AARCH64) #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B +#elif defined (MDE_CPU_RISCV64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B #endif =20 =20 diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiB= aseType.h index a62f13d..d979412 100644 --- a/MdePkg/Include/Uefi/UefiBaseType.h +++ b/MdePkg/Include/Uefi/UefiBaseType.h @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All = rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -240,6 +241,12 @@ typedef union { /// #define EFI_IMAGE_MACHINE_AARCH64 0xAA64 =20 +/// +/// PE32+ Machine type for RISC-V 32/64/128 +/// +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 =20 #if defined (MDE_CPU_IA32) =20 @@ -268,6 +275,12 @@ typedef union { =20 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) =20 +#elif defined (MDE_CPU_RISCV64) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV64) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + #elif defined (MDE_CPU_EBC) =20 /// diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 44a0a6a..e2d4539 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -6,6 +6,8 @@ by this include file. =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -2178,6 +2180,7 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.E= FI" =20 #if defined (MDE_CPU_IA32) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA= 32 @@ -2188,6 +2191,8 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM #elif defined (MDE_CPU_AARCH64) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AA= RCH64 +#elif defined (MDE_CPU_RISCV64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RI= SCV64 #else #error Unknown Processor Type #endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47756): https://edk2.groups.io/g/devel/message/47756 Mute This Topic: https://groups.io/mt/34258199/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47755+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47755+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200561; cv=none; d=zoho.com; s=zohoarc; b=d4y1eEbx9N6DcutbqwK2y0eMxOqOMBJFPcOT2k/anGLWboBcooCUi/aWAU4uOx93Im97gXVh+Kzc+w6KY7sPiO6nZ3k6xKQYN4Y/u3eTVuW5KNYRd+klBQgkCIenqvs8qa6OLi/MhPpGjg69DZ7w5WLEDfJJncmFaIflCe0ns8M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200561; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=6Af4dOmEtyJpQdXSb4gRZQ35yFFOcyn5IJi3I36Day0=; b=a48pqoPRmIZncI4NZGQpfyIBs3UE9MAvqgNmsxYY74BzSnnS2YC0cS+yfZaZPb8u11qpMLqKpN1uRr4ju4EpBllUsHKaK21giE4anIVXOUmr510yTRgog0nTZBytWkN5t3UPX4EcSkdAHkDNZGSk6CZscoYs/sIGA4oNsxA2qfI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47755+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200561795373.4020664671749; Sun, 22 Sep 2019 18:02:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id q5aQYY1788612xemxa7Fw4Dl; Sun, 22 Sep 2019 18:02:41 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:41 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N113W2007622 for ; Mon, 23 Sep 2019 01:02:40 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7trn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:40 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id C09E55C for ; Mon, 23 Sep 2019 01:02:39 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id D952F46; Mon, 23 Sep 2019 01:02:38 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch. Date: Mon, 23 Sep 2019 08:31:31 +0800 Message-Id: <1569198715-31552-7-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: LCmovRjF6QxCSG2aMKMUeJVJx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200561; bh=nt+mPGed8z9+JlRcoMoZKxw2m6+YRkTAvpqfUVbeed8=; h=Cc:Date:From:Reply-To:Subject:To; b=WVMgNUC9NC95RpDsSXDrjsO3pmYihYZW6gW/AqzwZrbXs2P7ac5rKNfF4VMWjSXaGFt Dx5neCccQlET+JKgLKPAsUDY2QpOeu6D6UYblj9C6fbFQDDOE2l8xxpkM75nIkFI5a+s6 Wh7jLvw/w2OmKfGRLMVXqGYf7eOuXF7+KWA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++--= -- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf= b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf index 9da4507..84f3688 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -5,6 +5,7 @@ # the capsule runtime services are ready. # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -21,20 +22,20 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] CapsuleService.c CapsuleService.h =20 -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64] +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64] SaveLongModeContext.c =20 -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64] +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64] CapsuleCache.c =20 -[Sources.Ia32, Sources.X64, Sources.EBC] +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64] CapsuleReset.c =20 [Sources.ARM, Sources.AARCH64] --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47755): https://edk2.groups.io/g/devel/message/47755 Mute This Topic: https://groups.io/mt/34258197/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47757+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47757+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200564; cv=none; d=zoho.com; s=zohoarc; b=MmB5/epMHZjO8z1moCt4odR0kYd9iA0jGC0ODS+st940mAWwezm6n1H0duWF0euHhIuytmy3X6V6VCpboRjdsBU6OnNuOStFpPz8f70d44OJwbFVPHc9MvpSiBBKbOxe79marH1MTU0oBVsZjsHMrnQruXGTO1sViEgGjej1f6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200564; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=hqxePeN2NjWySnDeu2GonaaU0u6MzN7Im0HTuYD0Otg=; b=CnjlT2OH9Z7LNgm5ngmAqE7Mivn21P9/xOQQdc2lKIcFMAiqv+aadU/p7HNFIRi4wqjOqcL7YXBPzHCkAj/qDWWdL+JvoaeAtb6PGh0JMCo1hAsMDskVU/hOn6A1xfuQskabx+hXLZiGMGXtDNm2uWwIP0XA3Tmhu388c3Jbx90= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47757+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200564501416.90421065364785; Sun, 22 Sep 2019 18:02:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3FSkYY1788612xvwQB9bB6C9; Sun, 22 Sep 2019 18:02:44 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:43 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N113oj021551 for ; Mon, 23 Sep 2019 01:02:41 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay3f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:41 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 1DE615A for ; Mon, 23 Sep 2019 01:02:41 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 3611545; Mon, 23 Sep 2019 01:02:39 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. Date: Mon, 23 Sep 2019 08:31:32 +0800 Message-Id: <1569198715-31552-8-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: whWhpfesMCuSNYqyOLCr3Efxx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200564; bh=Yt7zzBxm6XN6elsclg7rW+jK1Y95si9JjuA9qvXn/b4=; h=Cc:Date:From:Reply-To:Subject:To; b=oPoOVDjeagidX/BnXF5M+ovIKuuybkrunxhBoNrJfMsEuUKPBEaBJGhl7hSC0+gFP8i jxDaKtbyYRW933FYhd1KpnpN8t0PGHOc2XkirKD3LXusKgcZjWx0UElvNMUYIWvoXUdaM gwhjjgUKp3Lm+5iZqeIPQPB2weuwMKuMbyI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V RV64 BaseLib functions. Signed-off-by: Abner Chang --- MdePkg/Include/Library/BaseLib.h | 26 ++ MdePkg/Library/BaseLib/BaseLib.inf | 18 +- MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++ MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +++ MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++ MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++ MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++ MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 +++ .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++ MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++ .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++ MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++ MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++ .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++ MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 264 +++++++++++++++++= ++++ 15 files changed, 670 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 2a75bc0..b8c8512 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4,6 +4,8 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -124,6 +126,30 @@ typedef struct { =20 #endif // defined (MDE_CPU_AARCH64) =20 +#if defined (MDE_CPU_RISCV64) +/// +/// The RISC-V architecture context buffer used by SetJump() and LongJump(= ). +/// +typedef struct { + UINT64 RA; + UINT64 S0; + UINT64 S1; + UINT64 S2; + UINT64 S3; + UINT64 S4; + UINT64 S5; + UINT64 S6; + UINT64 S7; + UINT64 S8; + UINT64 S9; + UINT64 S10; + UINT64 S11; + UINT64 SP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_RISCV64) =20 // // String Services diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb..28d5795 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -381,6 +382,21 @@ AArch64/CpuBreakpoint.asm | MSFT AArch64/SpeculationBarrier.asm | MSFT =20 +[Sources.RISCV64] + Math64.c + RiscV64/Unaligned.c + RiscV64/InternalSwitchStack.c + RiscV64/CpuBreakpoint.c + RiscV64/GetInterruptState.c + RiscV64/DisableInterrupts.c + RiscV64/EnableInterrupts.c + RiscV64/CpuPause.c + RiscV64/RiscVSetJumpLongJump.S | GCC + RiscV64/RiscVCpuBreakpoint.S | GCC + RiscV64/RiscVCpuPause.S | GCC + RiscV64/RiscVInterrupt.S | GCC + RiscV64/FlushCache.S | GCC + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Librar= y/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 0000000..d82b1d5 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,27 @@ +/** @file + CPU breakpoint for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuBreakpoint (VOID); + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + RiscVCpuBreakpoint (); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/Bas= eLib/RiscV64/CpuPause.c new file mode 100644 index 0000000..8eb6b65 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,29 @@ +/** @file + CPU pause for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuPause (VOID); + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + RiscVCpuPause (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Li= brary/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 0000000..7ee5eb1 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,24 @@ +/** @file + CPU disable interrupt function for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BaseLibInternals.h" + +extern VOID RiscVDisableSupervisorModeInterrupts (VOID); + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + RiscVDisableSupervisorModeInterrupts (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Lib= rary/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 0000000..9aa0d9a --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,25 @@ +/** @file + CPU enable interrupt function for RISC-V + + Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVEnableSupervisorModeInterrupt (VOID); + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + RiscVEnableSupervisorModeInterrupt (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S new file mode 100644 index 0000000..0ef0213 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,21 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) + +ASM_PFX(RiscVInvalidateInstCacheAsm): + fence.i + ret + +ASM_PFX(RiscVInvalidateDataCacheAsm): + fence + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Li= brary/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 0000000..8f764fb --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file + CPU get interrupt state function for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID); + +/** + Retrieves the current CPU interrupt state. + + Returns TRUE is interrupts are currently enabled. Otherwise + returns FALSE. + + @retval TRUE CPU interrupts are enabled. + @retval FALSE CPU interrupts are disabled. + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ) +{ + unsigned long RetValue; + + RetValue =3D RiscVGetSupervisorModeInterrupts (); + return RetValue? TRUE: FALSE; +} + + diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/= Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 0000000..1082d4e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,55 @@ +/** @file + Switch stack function for RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param Marker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + ) +{ + BASE_LIBRARY_JUMP_BUFFER JumpBuffer; + + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Con= text2:%x NewStack%x\n", \ + EntryPoint, Context1, Context2, NewStack)); + JumpBuffer.RA =3D (UINTN)EntryPoint; + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *); + JumpBuffer.S0 =3D (UINT64)(UINTN)Context1; + JumpBuffer.S1 =3D (UINT64)(UINTN)Context2; + LongJump (&JumpBuffer, (UINTN)-1); + ASSERT(FALSE); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/Bas= eLib/RiscV64/LongJump.c new file mode 100644 index 0000000..a62b882 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c @@ -0,0 +1,32 @@ +/** @file + Long jump implementation of RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + + +/** + Restores the CPU context that was saved with SetJump(). + + Restores the CPU context from the buffer specified by JumpBuffer. + This function never returns to the caller. + Instead is resumes execution based on the state of JumpBuffer. + + @param JumpBuffer A pointer to CPU context buffer. + @param Value The value to return when the SetJump() context is = restored. + +**/ +VOID +EFIAPI +InternalLongJump ( + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, + IN UINTN Value + ) +{ + ASSERT (FALSE); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/L= ibrary/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 0000000..1a45e2a --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuBreakpoint for RISC-V +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint) +ASM_PFX(RiscVCpuBreakpoint): + ebreak + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 0000000..ceba0c0 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuPause for RISC-V +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuPause) +ASM_PFX(RiscVCpuPause): + nop + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 0000000..8fdb544 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,32 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V Supervisor Mode interrupt enable/disable +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) + +# define MSTATUS_SIE 0x00000002 +# define CSR_SSTATUS 0x100 + +ASM_PFX(RiscVDisableSupervisorModeInterrupts): + li a1, MSTATUS_SIE + csrc CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVEnableSupervisorModeInterrupt): + li a1, MSTATUS_SIE + csrs CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVGetSupervisorModeInterrupts): + csrr a0, CSR_SSTATUS + andi a0, a0, MSTATUS_SIE + ret + diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg= /Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 0000000..e72dd7f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------= ------ +// +// Set/Long jump for RISC-V +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +# define REG_S sd +# define REG_L ld +# define SZREG 8 +.align 3 + .globl SetJump + +SetJump: + REG_S ra, 0*SZREG(a0) + REG_S s0, 1*SZREG(a0) + REG_S s1, 2*SZREG(a0) + REG_S s2, 3*SZREG(a0) + REG_S s3, 4*SZREG(a0) + REG_S s4, 5*SZREG(a0) + REG_S s5, 6*SZREG(a0) + REG_S s6, 7*SZREG(a0) + REG_S s7, 8*SZREG(a0) + REG_S s8, 9*SZREG(a0) + REG_S s9, 10*SZREG(a0) + REG_S s10,11*SZREG(a0) + REG_S s11,12*SZREG(a0) + REG_S sp, 13*SZREG(a0) + li a0, 0 + ret + + .globl InternalLongJump +InternalLongJump: + REG_L ra, 0*SZREG(a0) + REG_L s0, 1*SZREG(a0) + REG_L s1, 2*SZREG(a0) + REG_L s2, 3*SZREG(a0) + REG_L s3, 4*SZREG(a0) + REG_L s4, 5*SZREG(a0) + REG_L s5, 6*SZREG(a0) + REG_L s6, 7*SZREG(a0) + REG_L s7, 8*SZREG(a0) + REG_L s8, 9*SZREG(a0) + REG_L s9, 10*SZREG(a0) + REG_L s10,11*SZREG(a0) + REG_L s11,12*SZREG(a0) + REG_L sp, 13*SZREG(a0) + + add a0, s0, 0 + add a1, s1, 0 + add a2, s2, 0 + add a3, s3, 0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c b/MdePkg/Library/Ba= seLib/RiscV64/Unaligned.c new file mode 100644 index 0000000..012d913 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c @@ -0,0 +1,264 @@ +/** @file + RISC-V specific functionality for (un)aligned memory read/write. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +/** + Reads a 16-bit value from memory that may be unaligned. + + This function returns the 16-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 16-bit value that may be unaligned. + + @return The 16-bit value read from Buffer. + +**/ +UINT16 +EFIAPI +ReadUnaligned16 ( + IN CONST UINT16 *Buffer + ) +{ + UINT16 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D sizeof (UINT16) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 16-bit value to memory that may be unaligned. + + This function writes the 16-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 16-bit value that may be unaligned. + @param Value 16-bit value to write to Buffer. + + @return The 16-bit value to write to Buffer. + +**/ +UINT16 +EFIAPI +WriteUnaligned16 ( + OUT UINT16 *Buffer, + IN UINT16 Value + ) +{ + INT8 Count; + UINT16 ValueTemp; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT16) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 24-bit value from memory that may be unaligned. + + This function returns the 24-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 24-bit value that may be unaligned. + + @return The 24-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned24 ( + IN CONST UINT32 *Buffer + ) +{ + UINT32 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 2, Value =3D 0; Count >=3D 0 ; Count --) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 24-bit value to memory that may be unaligned. + + This function writes the 24-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 24-bit value that may be unaligned. + @param Value 24-bit value to write to Buffer. + + @return The 24-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned24 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ) +{ + INT8 Count; + UINT32 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < 3 ; Count ++) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 32-bit value from memory that may be unaligned. + + This function returns the 32-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 32-bit value that may be unaligned. + + @return The 32-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned32 ( + IN CONST UINT32 *Buffer + ) +{ + UINT32 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D sizeof (UINT32) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 32-bit value to memory that may be unaligned. + + This function writes the 32-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 32-bit value that may be unaligned. + @param Value The 32-bit value to write to Buffer. + + @return The 32-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned32 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ) +{ + INT8 Count; + UINT32 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT32) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 64-bit value from memory that may be unaligned. + + This function returns the 64-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 64-bit value that may be unaligned. + + @return The 64-bit value read from Buffer. + +**/ +UINT64 +EFIAPI +ReadUnaligned64 ( + IN CONST UINT64 *Buffer + ) +{ + UINT64 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + for (Count =3D sizeof (UINT64) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 64-bit value to memory that may be unaligned. + + This function writes the 64-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 64-bit value that may be unaligned. + @param Value The 64-bit value to write to Buffer. + + @return The 64-bit value to write to Buffer. + +**/ +UINT64 +EFIAPI +WriteUnaligned64 ( + OUT UINT64 *Buffer, + IN UINT64 Value + ) +{ + INT8 Count; + UINT64 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT64) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47757): https://edk2.groups.io/g/devel/message/47757 Mute This Topic: https://groups.io/mt/34258200/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47758+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47758+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200564; cv=none; d=zoho.com; s=zohoarc; b=Vvk4vf/VGFj6vxdsTxgHkfjl0AdYk/wX8+hC1/oRJDZcAa3/YaJPK/7/y64KuSGVBI+XSS5QL1J7d7THYfoeQcUy9z30licE36B20PjAGwGzQOJiG+mbFBUgwr0PX0g6+lMDfOMlsER5rufFS2vuTbGitU/GZsI1LbmVjrTr7cc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200564; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=vTtWZtT7E+MNQ6OWFut9COhrjW6AWO1vxqhxNr+iCis=; b=gG/dXIHER50CPLhJKPphhLqWvNgfYX3zMa9k0Uxabf6ZjNBhyRRgjPeqKcsCGVOKOLsKw5+7Syfx9Z2FylgG8/IpfKXiKyDwZtpzdd5ACAtBLGudvS2oJPHjg8Zu1udhZ7vt2PdNKMrjdc7nNWVAYWjDFJX/Vb9HGCfAzG6SdsI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47758+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156920056493095.9390185060779; Sun, 22 Sep 2019 18:02:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MyxKYY1788612xnQCFm6PdTb; Sun, 22 Sep 2019 18:02:44 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:43 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114il006844 for ; Mon, 23 Sep 2019 01:02:43 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb4e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:42 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 6C31A59 for ; Mon, 23 Sep 2019 01:02:42 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 85F0F45; Mon, 23 Sep 2019 01:02:41 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Date: Mon, 23 Sep 2019 08:31:33 +0800 Message-Id: <1569198715-31552-9-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: kyYHPKXGO8H5QUHSGiQ8lTrKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200564; bh=cP+Rb9spYeGnNvtvtFSyrAISNZHETvIz28iR2Sgrf7E=; h=Cc:Date:From:Reply-To:Subject:To; b=OOrNr590cQFt5YezDOp0gZPlzeNUy/lALcJ9gW2XYQ5IgsBDyTqooTB1qPktHw8zTFv hSeKyZ5q37B+1XAh/VVZb1SFybBmuBV1WqIFHUJLd4199Xq3fUBgSBUx8S7JTNStQvtcD z3cUhPaDL9tn+IcM2ZH60+BA2GReL6fP0lI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Signed-off-by: Abner Chang --- .../BaseCacheMaintenanceLib.inf | 4 + .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++= ++++ 2 files changed, 254 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feec..d9bfa04 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ [Sources.AARCH64] ArmCache.c =20 +[Sources.RISCV64] + RiscVCache.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000..d8e4665 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,250 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvalidateInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvalidateDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47758): https://edk2.groups.io/g/devel/message/47758 Mute This Topic: https://groups.io/mt/34258201/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47759+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47759+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200566; cv=none; d=zoho.com; s=zohoarc; b=LajPHFSNw0xxJhOQhAkhTUZj6HQxWQTAobecbNliO7Lms29vHX6GeXjBJqKX3vB2/rFNFSuDvZMiGviE9VKByVfet9sfS6OZFEQ8OUbAo8mcCfdfw9hGFzQvYjl/Pr6Kx50z+BC0g8uz1ghEruo+1q1dGFHLbTXFz+jcIHOFzEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200566; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=1izFYb39z9ol5hROHYMWVMGYe2t72q+3dnn1gtsnkYY=; b=lIffim0v0dwSP8BqEoFF8n+JcjTCBELZEkwPSaCsVWwaTgXttNpTlClDCbl4hdeLpH68iO8a1zk9kx1qr3OV5vTF7CIoUA5HWTz4OrQq/SZmaqstaF2eVGvMgLJ1oyaElqf5jFriQ2mwsvTmOThI6y1Kzla6by+aFSnydZHjlRw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47759+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200566890615.8219934969305; Sun, 22 Sep 2019 18:02:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZXAAYY1788612x6kZeInjwUm; Sun, 22 Sep 2019 18:02:46 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:45 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N115gd000547 for ; Mon, 23 Sep 2019 01:02:44 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v5wffe02t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:44 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id BDD785C for ; Mon, 23 Sep 2019 01:02:43 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id D452545; Mon, 23 Sep 2019 01:02:42 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Date: Mon, 23 Sep 2019 08:31:34 +0800 Message-Id: <1569198715-31552-10-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: Kkqb6q2ZXOGCZfxQ10Q6qfnTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200566; bh=1w1YfkpJy/QX7zBsj9XZ2wMfVo8ssyIvaW0ijtW4wQU=; h=Cc:Date:From:Reply-To:Subject:To; b=t2atAi5F3n1VsFZtkdPSU/dBGRbmwLi1yfjZ9gDooVfaSti7ixKUvV58jXExZmYs5m/ 6KqGwPaJ+ihLVl6azRhqvioMSFkmNdIdLwhnfQIxVf79VVWaVUyBUTirLgVdof2yhbHRh 66eboCvE4o3fxxsz/wHgusdlMq9gSWhdk4I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Signed-off-by: Abner Chang Acked-by: Leif Lindholm --- .../BaseCacheMaintenanceLib.inf | 4 + .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++= ++++ 2 files changed, 254 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feec..d9bfa04 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ [Sources.AARCH64] ArmCache.c =20 +[Sources.RISCV64] + RiscVCache.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000..d8e4665 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,250 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvalidateInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvalidateDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + return Address; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47759): https://edk2.groups.io/g/devel/message/47759 Mute This Topic: https://groups.io/mt/34258202/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47760+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47760+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200567; cv=none; d=zoho.com; s=zohoarc; b=aJXPljrQQ6lPyStacVAP4o9vgmT8/jHi8hrtdG2h98osOtGA98vRtXgDxuymzZ6RaBvpIlxzWxgIQCaTZ+9ZLAbfa1v1c/EnTByMEBBamwtiLgbDbmTqcVNugP8jZ4AKYhaL2kmgusWoZuOtdzz2HWObcfD/U2csq8F24/hfa8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200567; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+Kau4x3+xZ01XStH5Cu7/deubgrGScy1eLC8Dwk4uR0=; b=f9WGse2Vdqg9O1igw1uNHdg2weu8DbJ5pVjTQSWyKzJz6BOCiigXDqwkfgUYPUzY/fPg2WDcc18X+ETnUUqs+vUH6/yV7L9Z1yYyBgzg8orN9fZU/GyEVsRjz8L2JpTOJIbtjNE6RTFOjgSkZo2xPyr2aaEqrfVLcQ4S8sBZruc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47760+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200567387273.02176926117204; Sun, 22 Sep 2019 18:02:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WusKYY1788612xERmGCNhS0A; Sun, 22 Sep 2019 18:02:47 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:46 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N11dVl018109 for ; Mon, 23 Sep 2019 01:02:45 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5sxd7gyn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:45 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 1430B54 for ; Mon, 23 Sep 2019 01:02:45 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 2E6F545; Mon, 23 Sep 2019 01:02:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. Date: Mon, 23 Sep 2019 08:31:35 +0800 Message-Id: <1569198715-31552-11-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: EleMspi1q53lV3kfgAlAmm31x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200567; bh=gKi77RuQoI1p0eypIH0e6fB2nBrh03RhtLs2jB+qmgs=; h=Cc:Date:From:Reply-To:Subject:To; b=vCbFzr6f3Ym3RMUyzLicrBD+fvKQ4kqgkzzI4NkdidnS+AvXeHV81+HozMEhN3HmSkG BfvY0f5CRg8ESX+q3eX4WgfBxeUfnYUDYxY9IfwbjuSr09gshGO3khRYGwUD3pYisQ8eH vCTDJmU/qF4qfat7UARVTuCzwMhyQ5rTndE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V MMIO library instance. RISC-V only supports memory map I/O. Signed-off-by: Abner Chang --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +- MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 601 +++++++++++++++++= ++++ 2 files changed, 607 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 457cce9..fbb568e 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -2,13 +2,14 @@ # Instance of I/O Library using compiler intrinsics. # # I/O Library that uses compiler intrinsics to perform IN and OUT instruc= tions -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO = requests. +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated in= to MMIO requests. # MMIO requests are forwarded directly to memory. For EBC, I/O port requ= ests # ASSERT(). # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP.= All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -55,6 +56,9 @@ [Sources.AARCH64] IoLibArm.c =20 +[Sources.RISCV64] + IoLibRiscV.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Librar= y/BaseIoLibIntrinsic/IoLibRiscV.c new file mode 100644 index 0000000..789928b --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c @@ -0,0 +1,601 @@ +/** @file + Common I/O Library routines for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseIoLibIntrinsicInternal.h" + +/** + Reads an 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +MmioRead8 ( + IN UINTN Address + ) +{ + return *(volatile UINT8*)Address; +} + +/** + Writes an 8-bit MMIO register. + + Writes the 8-bit MMIO register specified by Address with the value speci= fied + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +MmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + *(volatile UINT8 *)Address =3D Value; + return Value; +} + +/** + Reads a 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address. The 16-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +MmioRead16 ( + IN UINTN Address + ) +{ + return *(volatile UINT16 *)Address; +} + +/** + Writes a 16-bit MMIO register. + + Writes the 16-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +MmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + *(volatile UINT16 *)Address =3D Value; + return Value; +} + +/** + Reads a 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address. The 32-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +MmioRead32 ( + IN UINTN Address + ) +{ + return *(volatile UINT32 *)Address; +} + +/** + Writes a 32-bit MMIO register. + + Writes the 32-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The valu return *(volatile UINT8*)Address; + to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +MmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + *(volatile UINT32 *)Address =3D Value; + return Value; +} + +/** + Reads a 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address. The 64-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +MmioRead64 ( + IN UINTN Address + ) +{ + return *(volatile UINT64 *)Address; +} + +/** + Writes a 64-bit MMIO register. + + Writes the 64-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + *(volatile UINT64 *)Address =3D Value; + return Value; +} + +/** + Reads an 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port. The 8-bit read value is retu= rned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +IoRead8 ( + IN UINTN Port + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit I/O port. + + Writes the 8-bit I/O port specified by Port with the value specified by = Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ + +UINT8 +EFIAPI +IoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port. The 16-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +IoRead16 ( + IN UINTN Port + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit I/O port. + + Writes the 16-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +IoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port. The 32-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +IoRead32 ( + IN UINTN Port + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit I/O port. + + Writes the 32-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +IoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Reads a 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port. The 64-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +IoRead64 ( + IN UINTN Port + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Writes a 64-bit I/O port. + + Writes the 64-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written to the I/O port. + +**/ +UINT64 +EFIAPI +IoWrite64 ( + IN UINTN Port, + IN UINT64 Value + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + ASSERT (FALSE); +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47760): https://edk2.groups.io/g/devel/message/47760 Mute This Topic: https://groups.io/mt/34258203/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47761+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47761+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200568; cv=none; d=zoho.com; s=zohoarc; b=HDjcuUMh/SQrK0v3XR3UmfKRq4aJJsa7onucH4wi9fdpaOV4UbG2mUloj+VevsU4lN04f9/vbcWB729nlk5iAZk/3TyfyHUSi4Lh6t5SUCkOA1M88fjhyOLiTpxWbZbCLFOOnqJyAOMjXh71TyGoTOWry20BJKoL36feFyxgzGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200568; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=wu6uZ84s13Tm5aJw/mAe83viNnsC5yGUiKPL9PT7YY4=; b=Z5D0mfo8t2XAkWGGXZcoE39bkHZJt3f7f0VGh6qM6If3/B4+rtJHRGoXtHA70zTFprQ0kFUcQdVIf3aeL5QhrwNYcGaQhPOiZBf8ZJnJmW5KymRletH+1ZBvCTAnn6MWSpezZkadCUK+yUHF2BMBBeMBV6q54ofmksGtR36OAZU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47761+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200568457971.048732196127; Sun, 22 Sep 2019 18:02:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RAmuYY1788612x4GHEYyKePj; Sun, 22 Sep 2019 18:02:48 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:47 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N119YS017661 for ; Mon, 23 Sep 2019 01:02:46 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5sxd7gyv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:46 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 6941D57 for ; Mon, 23 Sep 2019 01:02:46 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 7D20D45; Mon, 23 Sep 2019 01:02:45 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Date: Mon, 23 Sep 2019 08:31:36 +0800 Message-Id: <1569198715-31552-12-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: YehFN7j5FPradjfNjy5tJfzNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200568; bh=/ReLlvDffDd+JV97Cy8art6ngw3/euxlYpZAodaWdzs=; h=Cc:Date:From:Reply-To:Subject:To; b=T1RHOuwKSjqLTEJpNjYBkVDFZAr6UszH4hn3G5UFFWd1BddbO5L7ZCPNC8kEhDbbB6H u9Ak0NrfZIYl74i+vsK/0c9NY+TEhSFzOFDdPmBfOU+BMwXCqJ6/QLNbmSi8NWzTTt7Da 4YvZQDBk50SGhXgv67REXOJ4WG2M8M58xu8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Support RISC-V image relocation. Signed-off-by: Abner Chang --- MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 + .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++++++++++++++= ++++ 5 files changed, 152 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/Bas= ePeCoffLib/BasePeCoff.c index 07bb62f..97e0ff4 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c @@ -1,6 +1,6 @@ /** @file Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but - only supports relocating IA32, x64, IPF, and EBC images. + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images. =20 Caution: This file requires additional review when modified. This library will have external input - PE/COFF image. @@ -17,6 +17,7 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. = All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.inf index 395c140..b190494 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -3,6 +3,7 @@ # The IPF version library supports loading IPF and EBC PE/COFF image. # The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. # The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. +# The RISC-V version library support loading RISC-V images. # # Caution: This module requires additional review when modified. # This library will have external input - PE/COFF image. @@ -11,6 +12,7 @@ # # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@ [Sources.ARM] Arm/PeCoffLoaderEx.c =20 +[Sources.RISCV64] + RiscV/PeCoffLoaderEx.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.uni index b0ea702..8616ca3 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -4,6 +4,7 @@ // The IPF version library supports loading IPF and EBC PE/COFF image. // The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. // The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COF= F images. // // Caution: This module requires additional review when modified. // This library will have external input - PE/COFF image. @@ -12,6 +13,7 @@ // // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg= /Library/BasePeCoffLib/BasePeCoffLibInternals.h index b74277f..9c33703 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h @@ -2,6 +2,7 @@ Declaration of internal functions in PE/COFF Lib. =20 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/L= ibrary/BasePeCoffLib/RiscV/PeCoffLoaderEx.c new file mode 100644 index 0000000..8eb37f9 --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c @@ -0,0 +1,142 @@ +/** @file + PE/Coff loader for RISC-V PE image + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BasePeCoffLibInternals.h" +#include + +// +// RISC-V definition. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + *(UINT64 *)(*FixupData) =3D (UINT64)(UINTN)Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) |\ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) |\ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25))); + } + break; + + default: + return RETURN_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} + +/** + Returns TRUE if the machine type of PE/COFF image is supported. Supported + does not mean the image can be executed it means the PE/COFF loader supp= orts + loading and relocating of the image type. It's up to the caller to suppo= rt + the entry point. + + @param Machine Machine type from the PE Header. + + @return TRUE if this PE/COFF loader can load the image + +**/ +BOOLEAN +PeCoffLoaderImageFormatSupported ( + IN UINT16 Machine + ) +{ + if ((Machine =3D=3D IMAGE_FILE_MACHINE_RISCV32) || (Machine =3D=3D IMAG= E_FILE_MACHINE_RISCV64)) { + return TRUE; + } + + return FALSE; +} + +/** + Performs an Itanium-based specific re-relocation fixup and is a no-op on= other + instruction sets. This is used to re-relocated the image into the EFI vi= rtual + space for runtime calls. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeHotRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + return RETURN_UNSUPPORTED; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47761): https://edk2.groups.io/g/devel/message/47761 Mute This Topic: https://groups.io/mt/34258204/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47762+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47762+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200569; cv=none; d=zoho.com; s=zohoarc; b=PkC87bBX29h/Mj3+zFFeyAbwWASKNRfkX598VeO7tFd+VNurYqceQjb/8yIeVXJQGZsJakzsEtZIGRSYoM9SKMHR8HK0pWvdWxXBt3pJyDIfP1DMpaAt1+Aib/8zrkvxSFiNwCEQDQobwnLWQ/qqpMmIE0p9ymXV3xjWRpfXC08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200569; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=FqAfTsOHHLcF6uCe8Hx7afRyxSs03y+lBoy3/+xGf54=; b=THSc1BpP4c5XpO/paBU/KJsUbXNGXe3TKzbOisUOTxPoXudc4E1n+hcCj4Kfw1Q+fLF8PfQ2NDUTel+eevCmkHkc9I+KfSCS2S5304wa9EKoYgXpaLExrHI3VvvdIWrQkUSmC/jcKkq/BCFW2pWzlF1SZ/p7iyxKsgt0HDvRsZ8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47762+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15692005699611006.7836708979256; Sun, 22 Sep 2019 18:02:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sRT3YY1788612x8YZQGcwu26; Sun, 22 Sep 2019 18:02:49 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:49 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N116FQ006954 for ; Mon, 23 Sep 2019 01:02:48 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb5d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:48 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id B3A9D54 for ; Mon, 23 Sep 2019 01:02:47 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id CC1F345; Mon, 23 Sep 2019 01:02:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Date: Mon, 23 Sep 2019 08:31:37 +0800 Message-Id: <1569198715-31552-13-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: d0FD12x7N6k2dzcEAbwDAfUXx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200569; bh=OreTgdadLl//tTcigiPvsW7YVz1QtLBaE5VyczGeBaU=; h=Cc:Date:From:Reply-To:Subject:To; b=ZoW58+yqjRyNZPTsdDTXW6zhvYlj7hzykBPucPyQEDGkl3WmsGFc2bw8snVy86ogd6o PCUWg2CdqMf+AxLQzRnjjON3C17DeM1k+Jw7ZuF/FvBoNwz/ZjCshFiBJPS0D5ujmUfgy 3r8dVQp7oRaaSZP8hUdWNgYL8zTKsOBxqwQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement RISC-V CPU related functions in BaseCpuLib. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++- MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++-- MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index a7cb381..a95d8a0 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -24,7 +25,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources.IA32] @@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT AArch64/CpuSleep.asm | MSFT =20 +[Sources.RISCV64] + RiscV/Cpu.S + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/Base= CpuLib/BaseCpuLib.uni index fc95cda..85d56ce 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,12 +1,13 @@ // /** @file // Instance of CPU Library for various architecture. // -// CPU Library implemented using ASM functions for IA-32 and X64, +// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, // PAL CALLs for IPF, and empty functions for EBC. // // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -15,5 +16,5 @@ =20 #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU L= ibrary for various architectures" =20 -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty = functions for EBC." +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, a= nd empty functions for EBC." =20 diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpu= Lib/RiscV/Cpu.S new file mode 100644 index 0000000..703b1e8 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------= ------ +// +// CpuSleep for RISC-V +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +.data +.align 3 +.section .text + +.global ASM_PFX(_CpuSleep) + +ASM_PFX(_CpuSleep): + wfi + ret + + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47762): https://edk2.groups.io/g/devel/message/47762 Mute This Topic: https://groups.io/mt/34258206/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47763+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47763+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200571; cv=none; d=zoho.com; s=zohoarc; b=Xgyu0ILo3nTgna3N/xepaE0J0Cx1ssNDKhZf8JiIBHZ5F81XBEgKyZsMKLo8khzYG7QcNlHZAZeoSKDahaAKKGkMmNwHg3HODBl7Iz4CX8XSMEz+WWO8J5dl7JKAU2U00NYN2RSAOXVUwvmAwd7OyALF5K6hJ8jJnA2ek9+IwIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200571; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=puDo6IkLvICz4GQ19bEnh1/PByutPEzbrLpGFLHo5I8=; b=UGn/n/QPiX+MHUDkhe1em4sORjW+0jCRSfmNTcqtI22dBZ4ZlXgvsZPFw893MrE/ZKZ7BdydO8aA60ZxqSlHpVtOlu9OC2Ny020MZHt7bXIMMMoW/TO+ufHoJwtp0cgfOq/u6oGRneyudLwf7HIDWZjqjTPYfrbLid2/KJhhVTU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47763+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156920057135497.69836227580379; Sun, 22 Sep 2019 18:02:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DdCcYY1788612xylvvt7X1NA; Sun, 22 Sep 2019 18:02:51 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:50 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N1147J006848 for ; Mon, 23 Sep 2019 01:02:49 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb5k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:49 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 0FFBF54 for ; Mon, 23 Sep 2019 01:02:49 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 290C049; Mon, 23 Sep 2019 01:02:47 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Date: Mon, 23 Sep 2019 08:31:38 +0800 Message-Id: <1569198715-31552-14-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: JjhbDxdnpN3jjohakdpbMcPFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200571; bh=G5aRJ8l5uPiy+4co7mVQHoAhq378meiyzkEZe7q1rSI=; h=Cc:Date:From:Reply-To:Subject:To; b=pu9dk0Cpk7zhYCwZzKp/ZjkvR065pNJFjeowaP6Qk3tzfGtQWElBu8xNXqOLfNWgyfj zaoJ+dUWYbltBHXkIyyeJBp2d/mNFNS5PeOtGGhsN4y6LOsaJADhbs0mc0iIv5J2uqrWG /LKOJVaLQKy9xxaR+HKFLApzsjoF0TDa2Ic= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Support RISC-V cache related functions. Signed-off-by: Abner Chang --- .../BaseSynchronizationLib.inf | 6 + .../RiscV64/Synchronization.c | 183 +++++++++++++++++= ++++ .../RiscV64/SynchronizationAsm.S | 78 +++++++++ 3 files changed, 267 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zation.c create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19..c16ef9d 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,11 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT =20 +[Sources.RISCV64] + Synchronization.c + RiscV64/Synchronization.c | GCC + RiscV64/SynchronizationAsm.S + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.= c b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c new file mode 100644 index 0000000..e210b74 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c @@ -0,0 +1,183 @@ +/** @file + Implementation of synchronization functions on RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +UINT32 +SyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue +); + +UINT64 +SyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue +); + +UINT32 +SyncSyncIncrement32 ( + IN volatile UINT32 *Value + ); + +UINT32 +SyncSyncDecrement32 ( + IN volatile UINT32 *Value + ); + +/** + Performs an atomic compare exchange operation on a 16-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 16-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 16-bit value for the + compare exchange operation. + @param CompareValue 16-bit value used in compare operation. + @param ExchangeValue 16-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT16 +EFIAPI +InternalSyncCompareExchange16 ( + IN volatile UINT16 *Value, + IN UINT16 CompareValue, + IN UINT16 ExchangeValue + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO operation\n",= __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Performs an atomic compare exchange operation on a 32-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 32-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 32-bit value for the + compare exchange operation. + @param CompareValue 32-bit value used in compare operation. + @param ExchangeValue 32-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT32 +EFIAPI +InternalSyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue + ) +{ + + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange32(Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic compare exchange operation on a 64-bit unsigned integ= er. + + Performs an atomic compare exchange operation on the 64-bit unsigned int= eger specified + by Value. If Value is equal to CompareValue, then Value is set to Excha= ngeValue and + CompareValue is returned. If Value is not equal to CompareValue, then V= alue is returned. + The compare exchange operation must be performed using MP safe mechanism= s. + + @param Value A pointer to the 64-bit value for the compare exch= ange + operation. + @param CompareValue 64-bit value used in compare operation. + @param ExchangeValue 64-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT64 +EFIAPI +InternalSyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ) +{ + if (((UINTN)Value % sizeof (UINT64)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange64 (Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic increment of an 32-bit unsigned integer. + + Performs an atomic increment of the 32-bit unsigned integer specified by + Value and returns the incremented value. The increment operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to increment. + + @return The incremented value. + +**/ +UINT32 +EFIAPI +InternalSyncIncrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncIncrement32 (Value); +} + +/** + Performs an atomic decrement of an 32-bit unsigned integer. + + Performs an atomic decrement of the 32-bit unsigned integer specified by + Value and returns the decrement value. The decrement operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to decrement. + + @return The decrement value. + +**/ +UINT32 +EFIAPI +InternalSyncDecrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncDecrement32 (Value); +} diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationA= sm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S new file mode 100644 index 0000000..943e274 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V synchronization functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(SyncCompareExchange32) +.global ASM_PFX(SyncCompareExchange64) +.global ASM_PFX(SyncSyncIncrement32) +.global ASM_PFX(SyncSyncDecrement32) + +// +// ompare and xchange a 32-bit value. +// +// @param a0 : Pointer to 32-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange32): + lr.w a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.w a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit: + mv a0, a3 + ret + +.global ASM_PFX(SyncCompareExchange64) + +// +// Compare and xchange a 64-bit value. +// +// @param a0 : Pointer to 64-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange64): + lr.d a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.d a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit2: + mv a0, a3 + ret + +// +// Performs an atomic increment of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncIncrement32): + li a1, 1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret + +// +// Performs an atomic decrement of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncDecrement32): + li a1, -1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47763): https://edk2.groups.io/g/devel/message/47763 Mute This Topic: https://groups.io/mt/34258207/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47764+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47764+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200572; cv=none; d=zoho.com; s=zohoarc; b=RjPON/7cIO4E1uaFMMzpjeG7gjJvELfqVTnNjNDlzfgluKfPEnjlUBVs3q0YPbqw53YJHwRNTqWojMcKGWp/x/jvYQDDmX9P9wO0KRLnHhS5IBqdiwyOB84YNC4p15JIV5JnLqGt6ZIMhLq8DJ6pcuJO8qPFkGXco0fFxwH+0c8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200572; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=rZdeFVsZisrUm2jR0j7zh0A+oYpmIPkfgfJpk9LuCkI=; b=HjJ5ozkyrSJBTTIHkUsURSv/t5GYONFiBNe+KM7Z8nwydhHvHfkxVd0zYi2+bTNxx9lW0xBd1gTWHqzSdORJHQ9v3s7XFhY+vOUuSWvqCaXC/A6rVajLXbeJrw/wmufHUULGrUArYSuCt0WkZE20s1jjCaBvFRNzTRKeijQPMTQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47764+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200572643394.98961388394184; Sun, 22 Sep 2019 18:02:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8DzMYY1788612x6lUIjU6Qmb; Sun, 22 Sep 2019 18:02:52 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:51 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N119dY003214 for ; Mon, 23 Sep 2019 01:02:51 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v6ha4te41-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:50 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 66C9F5C for ; Mon, 23 Sep 2019 01:02:50 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 7813649; Mon, 23 Sep 2019 01:02:49 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Date: Mon, 23 Sep 2019 08:31:39 +0800 Message-Id: <1569198715-31552-15-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: rcc25yxipS3c24Hp8u6m3ziqx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200572; bh=WHzhKXhH4CwgCvAQ+Gzrp3dvP8as9KI9ldLwI6aGdFc=; h=Cc:Date:From:Reply-To:Subject:To; b=XMUuPwc1vYhVXosrP1pKpAJwwRuFR4szWXOjBQ0b0rWppikKXm7om96T5a0lvv4B4DX FuRqCot+8IUX5Bo2HJ9oOcQqZjyFg8lTsZpNBRjCMvEj479xS3cxQx53/V7B7W5ovQ6TY wsxAsny2jqMBc0uiV2hiBnwZx9+WKOXdR7E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISCV64 Arch. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- MdeModulePkg/Logo/Logo.inf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf index 0182025..243748c 100644 --- a/MdeModulePkg/Logo/Logo.inf +++ b/MdeModulePkg/Logo/Logo.inf @@ -19,7 +19,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Binaries] --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47764): https://edk2.groups.io/g/devel/message/47764 Mute This Topic: https://groups.io/mt/34258209/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47765+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47765+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200573; cv=none; d=zoho.com; s=zohoarc; b=EDam0YtrP2IlUy3udQuAu9g3brWdZUN+El3A0Ls1rSPQ763xVarmdBOzJDRWQ6wzNmT4rf+Gc1sfsq/+8O8TsLNu97OoYb1CSNWB5UPwONSv/y6V5Ia/v4NCCY+n+sOONm1uQNMS4qMHGnFEBCivQ8VS8kvdkS/HNt4yLyLhwF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200573; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=UTfxXPoMGWPI2rj9J5xmqO6Fes6OrQG/S4oxAC0IEjI=; b=eXtCdboNM9zA2Wtig7ekZ4RPjDiA3TAKnz0wLEsPONzrvGNmH6xeo4gTHUPY6Ky1J8CGzw+CqN6Km5H0y98Dw+03QU6W/Z5z5EdT5IHGqT0zhBZX2WgKO1Lx7Nq92uXzHFDku7VSXvL4s3UOVIt1R/4rCyk41GXzofHTjMU5g9o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47765+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200573964744.9575918042506; Sun, 22 Sep 2019 18:02:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3kDkYY1788612xlBFDcxODuo; Sun, 22 Sep 2019 18:02:53 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:53 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N1142P007664 for ; Mon, 23 Sep 2019 01:02:52 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7tu2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:52 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id C334E54 for ; Mon, 23 Sep 2019 01:02:51 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id D0F2B49; Mon, 23 Sep 2019 01:02:50 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Date: Mon, 23 Sep 2019 08:31:40 +0800 Message-Id: <1569198715-31552-16-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 70XU1yuS5g8EMOv1d6TzVyS1x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200573; bh=t92Zv9rqLkjSoYpajegtOuClZXqkYeASB2ku04KsSik=; h=Cc:Date:From:Reply-To:Subject:To; b=j/aVMmZJNLw+pRvAveL3NOcM7XTJbOVX4W3LMnB5fumQof6lifCIMP8qjuBWy1xfgyr qTDy7C35JUyJTuEDd2tU/P2rbAx9A33fZ485Q8oKmFuxLoK9ZInJoIXH78UUTFcIjFnhL 5VOGd+UYTUuhdV6xabdt16In1WcZLrWlyKI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISCV64 Arch. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- NetworkPkg/Network.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc index c7f4328..b484f9b 100644 --- a/NetworkPkg/Network.dsc.inc +++ b/NetworkPkg/Network.dsc.inc @@ -34,7 +34,7 @@ !include NetworkPkg/NetworkComponents.dsc.inc =20 !else -[Components.IA32, Components.X64, Components.ARM, Components.AARCH64] +[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Comp= onents.RISCV64] !include NetworkPkg/NetworkComponents.dsc.inc =20 !endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47765): https://edk2.groups.io/g/devel/message/47765 Mute This Topic: https://groups.io/mt/34258211/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47766+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47766+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200575; cv=none; d=zoho.com; s=zohoarc; b=FlLB48xPMBxqHxWvyrqi2XoFyURJP6IzYMxIN0NAcNSkIOpHP08E6bQQLvlmTFPvRsrHtO+yCakUsAqJe8XrOHNHt3vnyRFWOrsNnuER6d9UuiL43ETY8uhe0sMCUO9T17d666PqinCMi1TMHEx4DHalOZVESZrAR/xxBbaHQ84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200575; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=2Vzsh/Mc5kgYs3+97DVG5ag+HI9VXyG2jd+qCT7faVk=; b=kb6e+oW+YbHAU45TfeI1gBgZqiUSVu6cl9YN1afSDF7sDcF42FUjbQVody95Acq0djTCmMjpR2RuoKtfJpW+GcfNyT1Txn4lOR2n4hZZ6nZ3mA4n0XwT7JNhHQBwFGd1u7MVb4HFvq8bvuP/qf6mUj6KX/bpB7px04hDLWb1HmE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47766+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15692005757931023.7231571288169; Sun, 22 Sep 2019 18:02:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id uTu5YY1788612xYxCGxYjHCJ; Sun, 22 Sep 2019 18:02:55 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:55 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N113iV007643 for ; Mon, 23 Sep 2019 01:02:54 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7tu6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:54 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 6FFF657 for ; Mon, 23 Sep 2019 01:02:53 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 3A13B45; Mon, 23 Sep 2019 01:02:52 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Date: Mon, 23 Sep 2019 08:31:41 +0800 Message-Id: <1569198715-31552-17-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 15l2O5Di1ZurJseC0ORCdF4Ux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200575; bh=202cTSSUTVTkuKmv7GhK13K3UFJRLgtIeAVIDhoXs5A=; h=Cc:Date:From:Reply-To:Subject:To; b=RWFajRVq5AW6Xyay4mo9I6kdjiXWwve7ZiF41H21Qu0CPXNm5kGiqlzMLNXcjmTyfO+ 2Pnrt+qphufto8ptV8fyGhPM8QdgQtrGhAGZ63mS9TZz4I8duPDnHoxmiOKMyf+EGyVLG D/4Wvp9uBM+C9c+wd/fiao944bI9uSZs17c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This library provides CSR assembly functions to read/write RISC-V specific Control and Status registers. Signed-off-by: Abner Chang --- RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++ RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 +++++++++++++++++++++++= ++++ RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++ 3 files changed, 217 insertions(+) create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Libr= ary/RiscVCpuLib.h new file mode 100644 index 0000000..c84d599 --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h @@ -0,0 +1,68 @@ +/** @file + RISC-V CPU library definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _RISCV_CPU_LIB_H_ +#define _RISCV_CPU_LIB_H_ + +#include "RiscV.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext); + +UINT32 +RiscVGetScratch (VOID); + +UINT32 +RiscVGetTrapCause (VOID); + +UINT64 +RiscVReadMachineTimer (VOID); + +VOID +RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp(VOID); + +UINT64 +RiscVReadMachineIE(VOID); + +UINT64 +RiscVReadMachineIP(VOID); + +UINT64 +RiscVReadMachineStatus(VOID); + +VOID +RiscVWriteMachineStatus(UINT64); + +UINT64 +RiscVReadMachineTvec(VOID); + +UINT64 +RiscVReadMisa (VOID); + +UINT64 +RiscVReadMVendorId (VOID); + +UINT64 +RiscVReadMArchId (VOID); + +UINT64 +RiscVReadMImplId (VOID); + +#endif diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpu= Lib/Cpu.S new file mode 100644 index 0000000..f372397 --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V CPU functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVSetScratch) +.global ASM_PFX(RiscVGetScratch) +.global ASM_PFX(RiscVGetMachineTrapCause) +.global ASM_PFX(RiscVReadMachineIE) +.global ASM_PFX(RiscVReadMachineIP) +.global ASM_PFX(RiscVReadMachineStatus) +.global ASM_PFX(RiscVWriteMachineStatus) +.global ASM_PFX(RiscVReadMachineTvec) +.global ASM_PFX(RiscVReadMisa) +.global ASM_PFX(RiscVReadMVendorId) +.global ASM_PFX(RiscVReadMArchId) +.global ASM_PFX(RiscVReadMImplId) +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVSetScratch): + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVGetScratch): + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_PFX (RiscVGetMachineTrapCause): + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_PFX (RiscVReadMachineIE): + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_PFX (RiscVReadMachineIP): + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_PFX(RiscVReadMachineStatus): + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_PFX(RiscVWriteMachineStatus): + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_PFX(RiscVReadMachineTvec): + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_PFX(RiscVReadMisa): + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_PFX(RiscVReadMVendorId): + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_PFX(RiscVReadMArchId): + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_PFX(RiscVReadMImplId): + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Librar= y/RiscVCpuLib/RiscVCpuLib.inf new file mode 100644 index 0000000..fc9131b --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -0,0 +1,34 @@ +## @file +# RISC-V RV64 CPU library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVCpuLib + FILE_GUID =3D 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVCpuLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + +[Sources.RISCV64] + Cpu.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47766): https://edk2.groups.io/g/devel/message/47766 Mute This Topic: https://groups.io/mt/34258212/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47767+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47767+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200577; cv=none; d=zoho.com; s=zohoarc; b=lLb2GRKLC3Chkqjn7KQuQKVYl0VstVhm/VvM9KeEbhnUHYnbLXg8fHF7EEgd9xoY6rnxD23gmmo6j37yMoE4BQefTP/rn23UuKNWO77xpNn2qDJMpeHh6mQ/GMiBN/tqaneAsK8cYuAg+XRHNsIrxJ3moK3PHk8sZ9anV+Bse+g= ARC-Message-Signature: i=1; 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Sun, 22 Sep 2019 18:02:56 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N112Ox002914 for ; Mon, 23 Sep 2019 01:02:56 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2v6ha4te4u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:55 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id F29EC57 for ; Mon, 23 Sep 2019 01:02:54 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8B1AB49; Mon, 23 Sep 2019 01:02:53 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Date: Mon, 23 Sep 2019 08:31:42 +0800 Message-Id: <1569198715-31552-18-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 78mQlAZHJ3BMRVHrmdszWRXrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200577; bh=7EMckRDdvNXN003FQKWNYsvbBIELI10tIiQ3Ki1P6kU=; h=Cc:Date:From:Reply-To:Subject:To; b=Ao/05psPlH4fg+o2ZLB91UbNlpO591Eeer3yw0Ui9u2fp2P3SexOW63Y9vm0gaMFF3B 3s9cqej27nRgKHpe4sa5JQzvJp4D6HycbdD17bnbf97oCnLD1ed8EgqcTpFROncpYHX6O cDtqeUwqQ++hRvrtD6KaS6JaK45J+u2gWsU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Initial RISC-V Supervisor Mode trap handler Signed-off-by: Abner Chang --- .../RiscVExceptionLib/CpuExceptionHandler.S | 88 ++++++++++ .../CpuExceptionHandlerDxeLib.inf | 42 +++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 182 +++++++++++++++++= ++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 ++ 4 files changed, 325 insertions(+) create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerD= xeLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerL= ib.c create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerL= ib.uni diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S b/Ris= cVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S new file mode 100644 index 0000000..cffe485 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S @@ -0,0 +1,88 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + + .align 3 + .section .entry, "ax", %progbits + .globl _strap_handler +_strap_handler: + addi sp, sp, -34*8 + /* Save all general regisers except SP and T0 */ + sd ra, 1*8(sp) + sd gp, 2*8(sp) + sd tp, 3*8(sp) + sd t1, 4*8(sp) + sd t2, 5*8(sp) + sd s0, 6*8(sp) + sd s1, 7*8(sp) + sd a0, 8*8(sp) + sd a1, 9*8(sp) + sd a2, 10*8(sp) + sd a3, 11*8(sp) + sd a4, 12*8(sp) + sd a5, 13*8(sp) + sd a6, 14*8(sp) + sd a7, 15*8(sp) + sd s2, 16*8(sp) + sd s3, 17*8(sp) + sd s4, 18*8(sp) + sd s5, 19*8(sp) + sd s6, 20*8(sp) + sd s7, 21*8(sp) + sd s8, 22*8(sp) + sd s9, 23*8(sp) + sd s10, 24*8(sp) + sd s11, 25*8(sp) + sd t3, 26*8(sp) + sd t4, 27*8(sp) + sd t5, 28*8(sp) + sd t6, 29*8(sp) + + /* Call C routine */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP and T0 */ + ld ra, 1*8(sp) + ld gp, 2*8(sp) + ld tp, 3*8(sp) + ld t1, 4*8(sp) + ld t2, 5*8(sp) + ld s0, 6*8(sp) + ld s1, 7*8(sp) + ld a0, 8*8(sp) + ld a1, 9*8(sp) + ld a2, 10*8(sp) + ld a3, 11*8(sp) + ld a4, 12*8(sp) + ld a5, 13*8(sp) + ld a6, 14*8(sp) + ld a7, 15*8(sp) + ld s2, 16*8(sp) + ld s3, 17*8(sp) + ld s4, 18*8(sp) + ld s5, 19*8(sp) + ld s6, 20*8(sp) + ld s7, 21*8(sp) + ld s8, 22*8(sp) + ld s9, 23*8(sp) + ld s10, 24*8(sp) + ld s11, 25*8(sp) + ld t3, 26*8(sp) + ld t4, 27*8(sp) + ld t5, 28*8(sp) + ld t6, 29*8(sp) + addi sp, sp, 34*8 + sret diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.i= nf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf new file mode 100644 index 0000000..e5871dc --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf @@ -0,0 +1,42 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D CpuExceptionHandlerLib + MODULE_UNI_FILE =3D CpuExceptionHandlerLib.uni + FILE_GUID =3D 16309FCF-E900-459C-B071-052118394D11 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuExceptionHandlerLib + CONSTRUCTOR =3D CpuExceptionHandlerLibConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources.RISCV64] + CpuExceptionHandler.S + +[Sources.common] + CpuExceptionHandlerLib.c + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + DebugLib + RiscVCpuLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/= RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c new file mode 100644 index 0000000..8c75be0 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c @@ -0,0 +1,182 @@ +/** @file + RISC-V Exception Handler library implementition. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + + +extern void _strap_handler(void); +EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2]; +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Initializes all CPU interrupt/exceptions entries and provides the defaul= t interrupt/exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS All CPU interrupt/exception entries have b= een successfully initialized + with default interrupt/exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuInterruptHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + + DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n"= , InterruptType, InterruptHandler)); + gInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} +/** + Machine mode trap handler. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + VOID + ) +{ + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + // + // Check scasue register. + // + if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] !=3D NULL) { + gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CO= NST EFI_SYSTEM_CONTEXT)RiscVSystemContext); + } +} + +/** + Initializes all CPU exceptions entries with optional extra initializatio= ns. + + By default, this method should include all functionalities implemented by + InitializeCpuExceptionHandlers(), plus extra initialization works, if an= y. + This could be done by calling InitializeCpuExceptionHandlers() directly + in this method besides the extra works. + + InitData is optional and its use and content are processor arch dependen= t. + The typical usage of it is to convey resources which have to be reserved + elsewhere and are necessary for the extra initializations of exception. + + @param[in] VectorInfo Pointer to reserved vector list. + @param[in] InitData Pointer to data optional for extra initializat= ions + of exception. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid + content. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlersEx ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + ) +{ + return InitializeCpuExceptionHandlers (VectorInfo); +} + +/** + The constructor function to initial interrupt handlers in + RISCV_MACHINE_MODE_CONTEXT. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The destructor completed successfully. + @retval Other value The destructor did not complete successfully. + +**/ +EFI_STATUS +EFIAPI +CpuExceptionHandlerLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Set Superviosr mode trap handler. + // + csr_write(CSR_STVEC, _strap_handler); + + return EFI_SUCCESS; +} diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni = b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni new file mode 100644 index 0000000..00cca22 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni @@ -0,0 +1,13 @@ +// /** @file +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Except= ion Handler Librarys." + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Except= ion Handler Librarys." + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47767): https://edk2.groups.io/g/devel/message/47767 Mute This Topic: https://groups.io/mt/34258213/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47768+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47768+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200578; cv=none; d=zoho.com; s=zohoarc; b=J9xhZnnBzyNYVi4A5+1Rux81wWMlB2+qWJR1cgiqorgf/goBiugGfUJXttdCAMkgz4emnQQvG5f3OK78q/okyyoKxN1zRHI0kwLF1WuxAi7aaFxFUDdAQD1PBlphplSfbbwC6kC/CixBYL3osCJeuzvl3J7WKG4VeXo6bAjO+oc= ARC-Message-Signature: i=1; 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Sun, 22 Sep 2019 18:02:57 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N11534007742 for ; Mon, 23 Sep 2019 01:02:56 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7tug-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:56 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id C8DA951 for ; Mon, 23 Sep 2019 01:02:55 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id DDB4D45; Mon, 23 Sep 2019 01:02:54 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Date: Mon, 23 Sep 2019 08:31:43 +0800 Message-Id: <1569198715-31552-19-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: vYGnbFOnS7P3PqTc0CNnyLsNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200577; bh=99+jhICPeaPJuHMFXT/U447JfMXFF9P6PkC+fCzJlGs=; h=Cc:Date:From:Reply-To:Subject:To; b=S+nZUuFiF+MkhgHbfE0Sl0PFvVzeRyXAZfdrrKZa4jnC6956okiworhdHOg3CUfq9qa 8sMZHihCOIAte3A3olkisdGRXIW0wVfg/Cwf/tV28hIq1Rpwxn82txcGU/tuF+5hUiBdo KS10DoN5VzBb5TI4p88XD0AePCD0Lo4ggEs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Timer library for RISC-V Signed-off-by: Abner Chang --- .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++++++++++++= ++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +++ RiscVPkg/RiscVPkg.dec | 9 + 4 files changed, 259 insertions(+) create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPk= g/Library/RiscVTimerLib/BaseRiscVTimerLib.inf new file mode 100644 index 0000000..af27049 --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf @@ -0,0 +1,34 @@ +## @file +# RISC-V Timer Library Instance. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D BaseRiscVTimerLib + FILE_GUID =3D FB648CF5-91BE-4737-9023-FD807AC6D96D + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + +[Sources] + RiscVTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + RiscVPlatformTimerLib + diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Libr= ary/RiscVTimerLib/RiscVTimerLib.c new file mode 100644 index 0000000..acb8c77 --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -0,0 +1,195 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D RiscVReadMachineTimer () + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPA= RE_BITS - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadMachineTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRisc= VMachineTimerFrequencyInHerz), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u)= , PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)); + + return NanoSeconds; +} diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Libr= ary/RiscVTimerLib/RiscVTimerLib.h new file mode 100644 index 0000000..bac3a70 --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h @@ -0,0 +1,21 @@ +/** @file + RISC-V timer library definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _RISCV_TIMER_LIB_INTERNAL_H_ +#define _RISCV_TIMER_LIB_INTERNAL_H_ + +#include +#include +#include +#include + +#include + +#endif // _RISCV_TIMER_LIB_INTERNAL_H_ diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec index 74314e8..a91392f 100644 --- a/RiscVPkg/RiscVPkg.dec +++ b/RiscVPkg/RiscVPkg.dec @@ -23,5 +23,14 @@ [Guids] gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} =20 +[PcdsFixedAtBuild] + # + # 1000000000 + # PcdRiscVMachineTimerTickInNanoSecond =3D -----------------------------= ---------- + # PcdRiscVMachineTimerFrequency= InHerz + # + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UIN= T64|0x00001010 + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000= |UINT64|0x00001011 + [UserExtensions.TianoCore."ExtraFiles"] RiscVPkgExtra.uni --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47768): https://edk2.groups.io/g/devel/message/47768 Mute This Topic: https://groups.io/mt/34258214/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47769+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47769+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200579; cv=none; d=zoho.com; s=zohoarc; b=K46VusemHvca3ZJmxuQ6FnuHpmIymNm2sETZJSNX+9e6Hk9Yq4At2n+IMUmTvNUuCKuFJUJhSuAED1nS24uim0beatQMVUcgoXfAgQfHbKlidb0otZXrhiOhb/bKGlEv3N2ebSfmgMiZYAkHKXcirZ1jY98zoC9voR4bFRsKTd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200579; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=dz2ifae9yk2KA/lINQQSVE8VcztEiBgSO2ltjoO5lyE=; b=F1vXeiIpgFAYiejJZGGRmo4EKjB/vDFcQW8zarFi/PKxdBSYUDuxjHwr382i5AXI7P5zKQUJgeyURu96PKIRO6vJnHyHbbl8re7597OO20FQNgziGeHzNBk3RWhgS0ALns1T9tTd9+adY4qiiraV2kdXkuL9Q405ofBlcXHyafE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47769+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200579312206.9286328497161; Sun, 22 Sep 2019 18:02:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WxOoYY1788612xAwrt5RyHxv; Sun, 22 Sep 2019 18:02:59 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:58 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N1140k010085 for ; Mon, 23 Sep 2019 01:02:57 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5984pmqv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:57 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 2C18851 for ; Mon, 23 Sep 2019 01:02:57 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 3B07345; Mon, 23 Sep 2019 01:02:56 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library. Date: Mon, 23 Sep 2019 08:31:44 +0800 Message-Id: <1569198715-31552-20-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: UzbEhbqJsnx7ADtuxek7TtP4x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200579; bh=ssFU6E6Ebb+B1quAmSVqeRstE4tj7kCFlZl921dn6Vk=; h=Cc:Date:From:Reply-To:Subject:To; b=RfQebRn444ciFFmbNg/6T71trzgLYplFVgTf4uxQ9oMyrHLPsXA5iJqNgT7Td7Zc+uO YXQyTd1knIdA758vyoN/GaEQ+cEjhR9JdXTGJ1DdX/nf+7wh3/wHTFBExwqRBlYYDbKIf Op+x1cDR7lTrEZzFOuHDlBktZCWoKXb2Sfw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" EDK2 RISC-V OpenSBI library which pull in external source files under RiscVPkg/opensbi to the build process. Signed-off-by: Abner Chang --- .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPk= g/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000..640ffba --- /dev/null +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,52 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVOpensbiLib + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVOpensbiLib + +[Sources] + ../../opensbi/lib/sbi/riscv_asm.c + ../../opensbi/lib/sbi/riscv_atomic.c + ../../opensbi/lib/sbi/riscv_hardfp.S + ../../opensbi/lib/sbi/riscv_locks.c + ../../opensbi/lib/sbi/riscv_unpriv.c + ../../opensbi/lib/sbi/sbi_console.c + ../../opensbi/lib/sbi/sbi_ecall.c + ../../opensbi/lib/sbi/sbi_emulate_csr.c + ../../opensbi/lib/sbi/sbi_fifo.c + ../../opensbi/lib/sbi/sbi_hart.c + ../../opensbi/lib/sbi/sbi_illegal_insn.c + ../../opensbi/lib/sbi/sbi_init.c + ../../opensbi/lib/sbi/sbi_ipi.c + ../../opensbi/lib/sbi/sbi_misaligned_ldst.c + ../../opensbi/lib/sbi/sbi_scratch.c + ../../opensbi/lib/sbi/sbi_string.c + ../../opensbi/lib/sbi/sbi_system.c + ../../opensbi/lib/sbi/sbi_timer.c + ../../opensbi/lib/sbi/sbi_tlb.c + ../../opensbi/lib/sbi/sbi_trap.c + ../../opensbi/lib/utils/sys/clint.c + ../../opensbi/lib/utils/irqchip/plic.c + ../../opensbi/lib/utils/serial/sifive-uart.c + ../../opensbi/lib/utils/serial/uart8250.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47769): https://edk2.groups.io/g/devel/message/47769 Mute This Topic: https://groups.io/mt/34258215/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47770+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47770+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200580; cv=none; d=zoho.com; s=zohoarc; b=ck+qcRqmh1p20Hq6cpH2WL8ER31d2W8nTDgjQhaSwE/NZeO0DF23B5b37LbnyqoxQ7uUmRl0zjDbpOss7CocABrFVjVJ9uKEuWbG3WftI/ytF0PCgW9f3t9lvU61EmulYC5/pREvbcyb2hLf0uHsw/jgSkdQSvnz/6u5f8WQayQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200580; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=mG0llqzLI39xkc0EFNzWGqawQZu1U9E5ppsLj8s0Vrs=; b=ONhsXgZVhfrNOMQkxG+/zLzLQuZ+gtjr0cCROhHtn31uY2IAzPbo9zU1NFNmc2PEZby5OLPos+X1uZEnVCX11j+CvvL5f36DYPPf0VXQOs82/bxi267Z1hMhgH4PQFe7spPgS2olBeDBh/1Um4wZItlGZMNY3eE479J9n4qY4f0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47770+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200580581502.43468380880574; Sun, 22 Sep 2019 18:03:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Rd5uYY1788612xdC08IbfYm2; Sun, 22 Sep 2019 18:03:00 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:59 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N115aY006863 for ; Mon, 23 Sep 2019 01:02:59 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb6u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:58 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 7720B57 for ; Mon, 23 Sep 2019 01:02:58 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8F5C149; Mon, 23 Sep 2019 01:02:57 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries. Date: Mon, 23 Sep 2019 08:31:45 +0800 Message-Id: <1569198715-31552-21-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: D6pVqRAlBuFqBpveYReJc90vx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200580; bh=J3I3IpCCJb2emDlrZ7YeAN/FQjDaOxKRJujW+qyJsYE=; h=Cc:Date:From:Reply-To:Subject:To; b=c0bALhepz255957IcMpHRSOBwKJnjkzZHq4YY7KbK1AlDpHFfJ3diyTKUSB4Na2ZBAD iD9Tegwde/eFvpBydJw9frWdDWrod0EB0d310f2ezZGt/sdoK2biy8LAekRBeBJaWQKUJ Hhj2Cc/scGqBvZ3PiOWFIRYODx37wrkc6vQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE phase. RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI interface. Signed-off-by: Abner Chang --- .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++ .../RiscVDxeIplHandoffLib.inf | 32 +++++++ .../RiscVDxeIplHandoffOpenSbiLib.c | 102 +++++++++++++++++= ++++ .../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++ 4 files changed, 208 insertions(+) create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHando= ffLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHando= ffLib.inf create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeI= plHandoffOpenSbiLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeI= plHandoffOpenSbiLib.inf diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c= b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c new file mode 100644 index 0000000..211b4e8 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c @@ -0,0 +1,41 @@ +/** @file + RISC-V platform level DXE core hand off library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + + // + // Transfer the control to the entry point of DxeCore. + // + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint, + HobList.Raw, + NULL, + TopOfStack + ); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.i= nf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf new file mode 100644 index 0000000..986db1d --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf @@ -0,0 +1,32 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVPlatformDxeIplLib + FILE_GUID =3D 2A77EE71-9F55-43F9-8773-7854A5B56086 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVDxeIplHandoffLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHando= ffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplH= andoffOpenSbiLib.c new file mode 100644 index 0000000..c640fd2 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS= biLib.c @@ -0,0 +1,102 @@ +/** @file + RISC-V DXE IPL to DXE core handoff platform library using OpenSBI + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/** + RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler. + This function is executed in RISC-V Supervisor mode. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVDxeIplHandoffOpenSbiHandler ( + IN UINTN HardId, + IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext + ) +{ + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff hand= ler entry\n")); + + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint, + ThisSwitchContext->HobList.Raw, + NULL, + ThisSwitchContext->TopOfStack + ); + + // + // Shold never came back. + // + __builtin_unreachable(); +} + + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + struct sbi_scratch *ThisScratch; + OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext; + + DEBUG ((DEBUG_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n")); + // + // Setup next address in OpenSBI scratch + // + OpenSbiSwitchModeContext.BaseOfStack =3D BaseOfStack; + OpenSbiSwitchModeContext.TopOfStack =3D TopOfStack; + OpenSbiSwitchModeContext.HobList =3D HobList; + OpenSbiSwitchModeContext.DxeCoreEntryPoint =3D DxeCoreEntryPoint; + ThisScratch =3D sbi_scratch_thishart_ptr (); + ThisScratch->next_arg1 =3D (unsigned long)(UINTN)&OpenSbiSwitchModeConte= xt; + ThisScratch->next_addr =3D (unsigned long)(UINTN)RiscVDxeIplHandoffOpenS= biHandler; + ThisScratch->next_mode =3D PRV_S; + + DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfSta= ck)); + DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack= )); + DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList)); + DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreE= ntryPoint)); + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN= )&OpenSbiSwitchModeContext)); + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x= \n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler)); + DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n",= PRV_S)); + sbi_init (ThisScratch); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHando= ffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIp= lHandoffOpenSbiLib.inf new file mode 100644 index 0000000..262071d --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS= biLib.inf @@ -0,0 +1,33 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library using O= penSBI +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVPlatformDxeIplLib + FILE_GUID =3D 906A4BB9-8DE2-4CE0-A609-23818A8FF514 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVDxeIplHandoffOpenSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47770): https://edk2.groups.io/g/devel/message/47770 Mute This Topic: https://groups.io/mt/34258216/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47771+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47771+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200582; cv=none; d=zoho.com; s=zohoarc; b=VTEy1phsEorqT5WGitel6onkMfbHkbB9BDrJaHhJFHDeb5BNUcK9IHz3oy9KcOBjP37dgVCKCRrEHK7AeCAreCHRKV2Iq24+6AV9GFmPru8L+/k4DYAOBedXv1P3GL8wh1fca1iFbouOka1HkeXzwAnHxQ5nq1JDVgfRvHnhbB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200582; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=qM2L50GIy3omqvvC72T0XiwwAyJ7f3LSSmGVOWmmb4g=; b=OIMCpn65W48ELfV4EQwSLjcNvE1uLI+67wz+nJmDot7JWb76vu3sORyjmYLtYwwcQK56REGrizYjbAOvtZxcSlCIPgiBgHEWqdw8ToIKsJM/+md/MYEumgdbWCvbDhlcf+x79KjpRwsOrauRkVYez+iRh4nVK7stG/0O3YPJdAw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47771+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15692005822931023.4490220669197; Sun, 22 Sep 2019 18:03:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZjbdYY1788612xv5MTpSqWHA; Sun, 22 Sep 2019 18:03:01 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:01 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114TO007723 for ; Mon, 23 Sep 2019 01:03:00 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5d2j7tv0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:00 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id C644A57 for ; Mon, 23 Sep 2019 01:02:59 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id DFD2345; Mon, 23 Sep 2019 01:02:58 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Date: Mon, 23 Sep 2019 08:31:46 +0800 Message-Id: <1569198715-31552-22-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: tKkoPWZ2vPS4kSSBcvw9vPwpx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200581; bh=qGx4YjPHWfj90dIMtipo05bKZhfn4X8sDhDyIyn1YNo=; h=Cc:Date:From:Reply-To:Subject:To; b=j79pU3cwexc3jLO81NI1nrYNrW2H+J88Ps/2idZRQtJh6mLrswgq2ZjnY0Yt8fkLFuj WqDlKFPDG+Lho2TuUEDjF7srCrdvyTmQ6xeXixh5RFEg3p/fLIOtKGInIKzS2+T0ZPMVW VezzIIVFqzX4vyoJ2TkJUr+cOYT4tBvIWng= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implementation of RISC-V platform level DxeIPL Signed-off-by: Abner Chang --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++- MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 ++++++++++++++++++= ++++ RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 +++++++++++++ 3 files changed, 124 insertions(+), 1 deletion(-) create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 98bc17f..5532323 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -7,6 +7,7 @@ # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 RISCV64 # =20 [Sources] @@ -49,6 +50,9 @@ [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c =20 +[Sources.RISCV64] + RiscV64/DxeLoadFunc.c + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -56,6 +60,9 @@ [Packages.ARM, Packages.AARCH64] ArmPkg/ArmPkg.dec =20 +[Packages.RISCV64] + RiscVPkg/RiscVPkg.dec + [LibraryClasses] PcdLib MemoryAllocationLib @@ -75,6 +82,10 @@ [LibraryClasses.ARM, LibraryClasses.AARCH64] ArmMmuLib =20 +[LibraryClasses.RISCV64] + RiscVPlatformDxeIplLib + RiscVOpensbiLib + [Ppis] gEfiDxeIplPpiGuid ## PRODUCES gEfiPeiDecompressPpiGuid ## PRODUCES diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModule= Pkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c new file mode 100644 index 0000000..d3c7f9d --- /dev/null +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c @@ -0,0 +1,71 @@ +/** @file + RISC-V specific functionality for DxeLoad. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeIpl.h" +#include "Library/RiscVPlatformDxeIpl.h" + +typedef +VOID* +(EFIAPI *DXEENTRYPOINT) ( + IN VOID *HobStart + ); + +/** + Transfers control to DxeCore. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +HandOffToDxeCore ( + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + VOID *BaseOfStack; + VOID *TopOfStack; + EFI_STATUS Status; + // + // + // Allocate 128KB for the Stack + // + BaseOfStack =3D AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE)); + ASSERT (BaseOfStack !=3D NULL); + + // + // Compute the top of the stack we were allocated. Pre-allocate a UINTN + // for safety. + // + TopOfStack =3D (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_= SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); + TopOfStack =3D ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); + + // + // End of PEI phase signal + // + Status =3D PeiServicesInstallPpi (&gEndOfPeiSignalPpi); + ASSERT_EFI_ERROR (Status); + + // + // Update the contents of BSP stack HOB to reflect the real stack info p= assed to DxeCore. + // + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE); + + DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", B= aseOfStack, TopOfStack)); + + // + // Transfer the control to the entry point of DxeCore. + // + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoin= t, HobList); +} + diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Incl= ude/Library/RiscVPlatformDxeIpl.h new file mode 100644 index 0000000..4763397 --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h @@ -0,0 +1,41 @@ +/** @file + Header file of RISC-V platform DXE IPL + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _RISC_V_PLATFORM_DXEIPL_H_ +#define _RISC_V_PLATFORM_DXEIPL_H_ + +typedef struct { + VOID *TopOfStack; + VOID *BaseOfStack; + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint; + EFI_PEI_HOB_POINTERS HobList; +} OPENSBI_SWITCH_MODE_CONTEXT; + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ); +#endif + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47771): https://edk2.groups.io/g/devel/message/47771 Mute This Topic: https://groups.io/mt/34258218/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47772+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47772+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200583; cv=none; d=zoho.com; s=zohoarc; b=iIZxZcf08nkJxxvW8Tz1EO+xJTeNqdRmtvOD1YUJyoy9cdcKS3YoXOQn/mBxtepPbSdRLl2NrMIX9RMSuuLe5NH7BxUT7xavrsBTGofBd+30ZNciPw9zTpMqkqW5O9s2TX2nI8dlTRoWMii990jjMpAm5Jo8kU+u8Pzj70HWllo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200583; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=1dYjA6SAYJ7x/87qRPxekoaU67fye4aFbvwLJiNtXJk=; b=fhiMo4Hmj+jbfzZXdgDJWikFnoY/7KxM5kLi8I8yBnJmiig3Tv5n4Usy+oimXi9kTAWrFQJchCsvTFjmspuiZYlb6aaJoNmtx2+jGQZVcf9NVtcHjoD7m8tXt22pcau/mrjF/zuROa6gIue1AYHWK+6lHdFqA8LLruNkqxvWq4U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47772+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200583147455.4713080801338; Sun, 22 Sep 2019 18:03:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id uiSiYY1788612xiPFaGYicew; Sun, 22 Sep 2019 18:03:02 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:02 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N117mG010212 for ; Mon, 23 Sep 2019 01:03:01 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5984pmrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:01 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 275C163 for ; Mon, 23 Sep 2019 01:03:01 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 3A34649; Mon, 23 Sep 2019 01:03:00 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Date: Mon, 23 Sep 2019 08:31:47 +0800 Message-Id: <1569198715-31552-23-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: GGGT7chSY44cujzSqGLC3Tlcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200582; bh=98pviwWOuAfH9wLTObWHmPS0ip363BkRzDJgtVsNHEg=; h=Cc:Date:From:Reply-To:Subject:To; b=ESTDZv1xNZE0r41Dk8kjjFHbVpR2zzE2S1Nx/wV6UqCE2E57ilEJ3vHAetAsdlTvWJS cJLSVdiTBMu7Gm/auLBvMhVdo4vlLduX/YgcDsy66gVeye6LZnA2YkT6LdxcqOXxhpF0M TyRzuBe8vQhoJ6SGc5HkcPBbKDj7OqTRgZI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implementation of RISC-V PEI Service Table Pointer library using RISC-V OpenSbi. Signed-off-by: Abner Chang --- .../PeiServicesTablePointerLibOpenSbi.inf | 38 +++++++ .../PeiServicesTablePointerLibOpenSbi.uni | 23 ++++ .../PeiServicesTablePointerOpenSbi.c | 121 +++++++++++++++++= ++++ 3 files changed, 182 insertions(+) create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerLibOpenSbi.inf create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerLibOpenSbi.uni create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerOpenSbi.c diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServices= TablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpe= nSbi/PeiServicesTablePointerLibOpenSbi.inf new file mode 100644 index 0000000..0b029ae --- /dev/null +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePo= interLibOpenSbi.inf @@ -0,0 +1,38 @@ +## @file +# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI Firm= wareContext. +# +# PEI Services Table Pointer Library implementation that retrieves a poin= ter to the +# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context = structure. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PeiServicesTablePointerLibOpenSbi + MODULE_UNI_FILE =3D PeiServicesTablePointerLibOpenSbi.uni + FILE_GUID =3D B4054E46-FE75-4290-B442-4836B1265D8F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiServicesTablePointerLib|PEIM PEI_C= ORE + + CONSTRUCTOR =3D PeiServicesTablePointerLibOpenSbiCons= tructor + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PeiServicesTablePointerOpenSbi.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServices= TablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpe= nSbi/PeiServicesTablePointerLibOpenSbi.uni new file mode 100644 index 0000000..f6fad8b --- /dev/null +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePo= interLibOpenSbi.uni @@ -0,0 +1,23 @@ +// /** @file +// +// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI Fir= mwareContext. +// +// PEI Services Table Pointer Library implementation that retrieves a poin= ter to the +// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context = structure. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may b= e found at +// http://opensource.org/licenses/bsd-license.php. +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI S= ervices Table Pointer Library using global variable for the table pointer" + +#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services = Table Pointer Library implementation that retrieves a pointer to the PEI Se= rvices Table from a global variable. Not available to modules that execute = from read-only memory." + diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServices= TablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/= PeiServicesTablePointerOpenSbi.c new file mode 100644 index 0000000..915964f --- /dev/null +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePo= interOpenSbi.c @@ -0,0 +1,121 @@ +/** @file + PEI Services Table Pointer Library. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Caches a pointer PEI Services Table. + + Caches the pointer to the PEI Services Table specified by PeiServicesTab= lePointer + in a CPU specific manner as specified in the CPU binding section of the = Platform Initialization + Pre-EFI Initialization Core Interface Specification. + + If PeiServicesTablePointer is NULL, then ASSERT(). + + @param PeiServicesTablePointer The address of PeiServices pointer. +**/ +VOID +EFIAPI +SetPeiServicesTablePointer ( + IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatfor= m->firmware_context; + FirmwareContext->PeiServiceTable =3D (VOID *)(UINTN)PeiServicesTablePoin= ter; + + DEBUG ((DEBUG_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Contex= t at 0x%x\n", + PeiServicesTablePointer, + ThisSbiPlatform->firmware_context + )); +} + +/** + Retrieves the cached value of the PEI Services Table pointer. + + Returns the cached value of the PEI Services Table pointer in a CPU spec= ific manner + as specified in the CPU binding section of the Platform Initialization P= re-EFI + Initialization Core Interface Specification. + + If the cached PEI Services Table pointer is NULL, then ASSERT(). + + @return The pointer to PeiServices. + +**/ +CONST EFI_PEI_SERVICES ** +EFIAPI +GetPeiServicesTablePointer ( + VOID + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatfor= m->firmware_context; + return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable; +} + +/** + The constructor function caches the pointer to PEI services. + + The constructor function caches the pointer to PEI services. + It will always return EFI_SUCCESS. + + @param FileHandle The handle of FFS header the loaded driver. + @param PeiServices The pointer to the PEI services. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +PeiServicesTablePointerLibOpenSbiConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + SetPeiServicesTablePointer (PeiServices); + return EFI_SUCCESS; +} + +/** + Perform CPU specific actions required to migrate the PEI Services Table + pointer from temporary RAM to permanent RAM. + + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in + a dedicated CPU register. This means that there is no memory storage + associated with storing the PEI Services Table pointer, so no additional + migration actions are required for Itanium or ARM CPUs. + +**/ +VOID +EFIAPI +MigratePeiServicesTablePointer ( + VOID + ) +{ + // + // PEI Services Table pointer is cached in the global variable. No addi= tional + // migration actions are required. + // + return; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47772): https://edk2.groups.io/g/devel/message/47772 Mute This Topic: https://groups.io/mt/34258219/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47773+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47773+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200584; cv=none; d=zoho.com; s=zohoarc; b=ULBq4P+y7yLeBxpUfBinYAvbiUvnc7+gszkRK6Tuh3cStHhoYLm7Vri9BS20jpOV0WDE62HYsqJmsoj14kkd/dzBeb7VVoHMXjY5Ycz1N9lyP/paXmaPrgY0sLwyIgZm5Xv+DNaW3eLPyrvrgV9j1E4ykWEdKELGr108IUdIjcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200584; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=36qq6oUM8z0ozaK7vQw0yoTr2jr2aAmrvYpdQs0CLjs=; b=C9ir5of4ZHgsM57jYtM3b5ypbsvhcvuVm5P7U+Bq8JexiJVKy7NUERsalP8teCCKOAQmR1dl+iTq3Ci7sUXjQnGC75nBMGMNAOfppUi6hk2sZJbu9a8pnYTzpZOjbdK5RhQYg8Su+4kmGeU1Hl38u2Hdpb1XuvnVrlecLelv+5I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47773+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200584981917.552921178512; Sun, 22 Sep 2019 18:03:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mKjiYY1788612xUpgwnb6C4I; Sun, 22 Sep 2019 18:03:04 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:04 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114Qc006829 for ; Mon, 23 Sep 2019 01:03:03 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb76-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:03 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 7771D51 for ; Mon, 23 Sep 2019 01:03:02 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 88FE945; Mon, 23 Sep 2019 01:03:01 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Date: Mon, 23 Sep 2019 08:31:48 +0800 Message-Id: <1569198715-31552-24-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: gfQIoeIQSsPX7jbHEoKaDF8Hx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200584; bh=FWbLZUVoGyF5EI0H56hTRP7ukOqnE4BeEwD2XOlzBhc=; h=Cc:Date:From:Reply-To:Subject:To; b=CUycGfpw2pBZ+8eECIzygXC6/2lrqT+tAVJM6pfI5lNh27y0jm5cemXAXV9KBv07VPI LLgi+GFCxT3M5gSgS1qJQeJNocZwVYQUC8BcisEdNojWvjPZ3pDj0FCZvHbBdJ78tfkqW 7+BkLXqxPv6YskFQuocCnrNDdx68nfR8aZE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" NULL instance of RISC-V Platform Temporary Memory library. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm --- .../Library/RiscVPlatformTempMemoryInitLib.h | 17 +++++++++++ .../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++++++++++++++++++= ++++ .../Riscv64/TempMemInit.S | 26 +++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib= .h create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Ris= cVPlatformTempMemoryInitLibNull.inf create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Ris= cv64/TempMemInit.S diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/Ri= scVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h new file mode 100644 index 0000000..11dfcfb --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h @@ -0,0 +1,17 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _RISCV_PLATFORM_TEMP_MEM_LIB_H_ +#define _RISCV_PLATFORM_TEMP_MEM_LIB_H_ + +#include "RiscV.h" + +VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID); +#endif diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatf= ormTempMemoryInitLibNull.inf b/RiscVPkg/Library/RiscVPlatformTempMemoryInit= LibNull/RiscVPlatformTempMemoryInitLibNull.inf new file mode 100644 index 0000000..12fa497 --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTemp= MemoryInitLibNull.inf @@ -0,0 +1,34 @@ +## @file +# RISC-V platform temporary memory library. +# +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVPlatformTempMemoryInitLibNull + FILE_GUID =3D 67294857-C0F8-4ACB-8237-D91FE506B710 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformTempMemoryInitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + +[Sources.RISCV64] + Riscv64/TempMemInit.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/Te= mpMemInit.S b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/T= empMemInit.S new file mode 100644 index 0000000..61a9923 --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemIn= it.S @@ -0,0 +1,26 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V RiscVPlatformTemporaryMemInit. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVPlatformTemporaryMemInit) + +// +// @retval a0 Temporary memory base. +// a1 Temporary memory size. +// +ASM_PFX(RiscVPlatformTemporaryMemInit): + li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase) + li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize) + ret --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47773): https://edk2.groups.io/g/devel/message/47773 Mute This Topic: https://groups.io/mt/34258220/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47774+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47774+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200586; cv=none; d=zoho.com; s=zohoarc; b=jozii1zZfrdEaWWbNj55xhbkaENDucXwYTiOQrnBKQ45Zx391wSxwLH1FdkxNifqcnPj+UmWGJ82CzHRT4dqLWwkV1AgN1xGlNSKb6JsFgbeagSilzzOE4SrPfCY/tcIQr6xO8ydfIV2fMwRamWZ/Z5lvO0eqCAQJ4kwLvaLvzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200586; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=IKoIOoxNzxVSDPbg9002GgIiYo/TsVgcjGu5a7aRZ48=; b=D4PUGEgpdRltov7oJT+yeWYiMVDYDU0XiAglUU7cMaPQakxH5MsYAHrHG8WXm4T5JicxnKLcaeg/ZnkVa53GuB1dUv7l91pwBzn+T7P+VfgPwfiHB92Lc1QwsgXi8VRRUhwKauRbnmhqSrY1R/y8pzmsU5gBdJ9hjC0yAWuaYmM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47774+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200586141948.490265237906; Sun, 22 Sep 2019 18:03:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GZlsYY1788612xpxNRz656BE; Sun, 22 Sep 2019 18:03:05 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:05 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N11A4P021921 for ; Mon, 23 Sep 2019 01:03:04 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay6x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:04 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id C48CC51 for ; Mon, 23 Sep 2019 01:03:03 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id D93A458; Mon, 23 Sep 2019 01:03:02 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver. Date: Mon, 23 Sep 2019 08:31:49 +0800 Message-Id: <1569198715-31552-25-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: DU6vsJzJPuoHMbW4oAEbGajNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200585; bh=lF01BwkOYjURYVOiGcs5eEeyYcLCTLheSPFW0fydPU4=; h=Cc:Date:From:Reply-To:Subject:To; b=Cq1b9PRaLDDF37uuJLxZCyirxX+Ch/Q8RuwIMroZ5/kZsVRIoiLnDAii9eOQAC6rJDW +E8YPAb/jSUT73ukI+oKAObvyevpwQbfk85jov10NhDShGl0pMO1/kcDatbCWyjVj0Hud 50vty77V0pU4yT/2SEq6ijaRjibMUjGeQ2w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V platform level timer library. Due to RISC-V timer CSR is platform implementation specific, RISC-V CPU DXE driver invokes platform level timer library to access to timer CSRs. Signed-off-by: Abner Chang --- RiscVPkg/Universal/CpuDxe/CpuDxe.c | 318 ++++++++++++++++++++++++++= ++++ RiscVPkg/Universal/CpuDxe/CpuDxe.h | 206 +++++++++++++++++++ RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 56 ++++++ RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 ++ RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 ++ 5 files changed, 607 insertions(+) create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe= /CpuDxe.c new file mode 100644 index 0000000..30d1115 --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.c @@ -0,0 +1,318 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuDxe.h" + +// +// Global Variables +// +BOOLEAN InterruptState =3D FALSE; +EFI_HANDLE mCpuHandle =3D NULL; +BOOLEAN mIsFlushingGCD; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + InterruptState =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + InterruptState =3D FALSE; + return EFI_SUCCESS; +} + + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D InterruptState; + return EFI_SUCCESS; +} + + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + if (TimerValue =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (TimerIndex !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + *TimerValue =3D (UINT64)RiscVReadMachineTimer (); + if (TimerPeriod !=3D NULL) { + *TimerPeriod =3D DivU64x32 ( + 1000000000000000u, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ); + } + return EFI_SUCCESS; +} + + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a:Set memory attributes not supported yet\n", __FU= NCTION__)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Machine mode handler is initiated in CpuExceptionHandlerLibConstructo= r in + // CpuExecptionHandlerLib. + // + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe= /CpuDxe.h new file mode 100644 index 0000000..e423fae --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.h @@ -0,0 +1,206 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_DXE_H_ +#define _CPU_DXE_H_ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif + diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuD= xe/CpuDxe.inf new file mode 100644 index 0000000..1931f45 --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf @@ -0,0 +1,56 @@ +## @file +# RISC-V CPU DXE module. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D CpuDxe + MODULE_UNI_FILE =3D CpuDxe.uni + FILE_GUID =3D 1A1E4886-9517-440e-9FDE-3BE44CEE2136 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializeCpu + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + CpuExceptionHandlerLib + TimerLib + SynchronizationLib + HobLib + ReportStatusCodeLib + RiscVCpuLib + RiscVPlatformTimerLib + +[Sources] + CpuDxe.c + CpuDxe.h + +[Protocols] + gEfiCpuArchProtocolGuid ## PRODUCES + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + CpuDxeExtra.uni diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuD= xe/CpuDxe.uni new file mode 100644 index 0000000..460141a --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni @@ -0,0 +1,13 @@ +// /** @file +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V C= PU Architecture Protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver= installs CPU Architecture Protocol." + diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal= /CpuDxe/CpuDxeExtra.uni new file mode 100644 index 0000000..6f819f0 --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// CpuDxe Localized Strings and Content +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"RISC-V Architectural DXE Driver" + + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47774): https://edk2.groups.io/g/devel/message/47774 Mute This Topic: https://groups.io/mt/34258221/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47775+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47775+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200587; cv=none; d=zoho.com; s=zohoarc; b=lg4xodDiiRexezOHTojFKR3X3GupvbZDoZVeM3coobUF77lXHxW5dVEBvix19PJDiPZ7LjCj1iovgibXxCuyvTFoT0Ez279oOKsRwwvEFI1L//inK4EKemwMj4Cirgxf6e5xKGoXLSQ+vQD3Nf+thj5TCxjtJ7w0bx3ksjwi0Co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200587; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=EhRD7MqvSIOOPnJP1x+fV6qV1aeQO1Yp5QBLd9Tfi0U=; b=ODvlER9WQuVt02C2lSnDvArNor3+u9CEN3f/746VRWs+0n6BjgOQ0KA7PlV172jYcUrsDLutfABNsT0dJpiGjB9QcecmmRQHcqVdxtJKO0JnLrlEellHGOlMJG6HpnBhxl9NaA+m3katan8vVODWfI7/PDFVyZB+4is/BDBM5Pc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47775+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200587696163.8580355904154; Sun, 22 Sep 2019 18:03:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BJywYY1788612xS0uelVJTku; Sun, 22 Sep 2019 18:03:07 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:06 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N115Ct006914 for ; Mon, 23 Sep 2019 01:03:06 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb7p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:05 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 515EB57 for ; Mon, 23 Sep 2019 01:03:05 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 352B358; Mon, 23 Sep 2019 01:03:03 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform. Date: Mon, 23 Sep 2019 08:31:50 +0800 Message-Id: <1569198715-31552-26-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: DWWpaICkIPJlpyAd9nvpOKOgx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200587; bh=uaaAnVb0JNhcSy2nqxU3cDS2mNASatghs0ji1LueE7A=; h=Cc:Date:From:Reply-To:Subject:To; b=u59Qrm373UUZ4gMxZcd0c92Slo42r82+Xz3dsPcSm62VFJt8MtoXtMXdsDWbEBu4FVO 3k7EEjKqEz9hp82gCSiIDpe9AFagJTXB32blFP4IOkS4VxoDmyyybC/6MbAz9WPz55XCu Z75++rm0qmvLcb46eoQmXX8UQ0xPEFArkXI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BaseTools changes for building EDK2 RISC-V platform. The changes made to build_rule.template is to avoid build errors cause by GCC711RISCV tool chain. Signed-off-by: Abner Chang --- BaseTools/Conf/build_rule.template | 62 ++--- BaseTools/Conf/tools_def.template | 64 ++++- BaseTools/Source/C/Common/BasePeCoff.c | 15 +- BaseTools/Source/C/Common/PeCoffLoaderEx.c | 95 ++++++++ BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++- BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +- BaseTools/Source/C/GenFw/Elf64Convert.c | 260 +++++++++++++++++= +++- BaseTools/Source/C/GenFw/elf_common.h | 62 +++++ .../Source/C/Include/IndustryStandard/PeImage.h | 6 + BaseTools/Source/Python/Common/DataType.py | 7 +- 10 files changed, 659 insertions(+), 45 deletions(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index db06d3a..fab3926 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -1,6 +1,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development LP.= All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # =20 @@ -145,14 +146,6 @@ "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src} =20 -[C-Header-File] - - *.h, *.H - - - - - [Assembly-Code-File.COMMON.COMMON] ?.asm, ?.Asm, ?.ASM @@ -266,10 +259,10 @@ $(RM) ${dst} "$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST) - =20 + "$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST) - =20 + # $(OBJECT_FILES_LIST) has wrong paths for cygwin "$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES) @@ -304,8 +297,8 @@ =20 "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STA= TIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS) - =20 - =20 + + [Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64, St= atic-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-= File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM] *.lib @@ -321,6 +314,21 @@ "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst} =20 =20 +[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32] + + *.lib + + + $(MAKE_FILE) + + + $(DEBUG_DIR)(+)$(MODULE_NAME).dll + + + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @= $(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS) + "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst} + + [Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION] *.lib @@ -346,8 +354,8 @@ =20 "$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(ST= ATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS) - =20 - =20 + + [Dynamic-Library-File] ?.dll @@ -360,7 +368,7 @@ $(CP) ${dst} $(DEBUG_DIR) $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR) - -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)=20 + -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR) $(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug $(OBJCOPY) --strip-unneeded -R .eh_frame ${src} @@ -375,7 +383,7 @@ $(CP) ${dst} $(DEBUG_DIR) $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR) - =20 + # tool to convert Mach-O to PE/COFF "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src} $(DEBU= G_DIR)(+)$(MODULE_NAME).pecoff @@ -414,13 +422,13 @@ Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC= _LIST) ${src} "$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path} $(OUTPUT_DIR)(+)${s_d= ir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii= $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii=20 + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii= $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_di= r}(+)${s_base}.iiii =20 Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC= _LIST) ${src} "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_d= ir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii= $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii=20 + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii= $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_di= r}(+)${s_base}.iiii =20 [C-Code-File.AcpiTable] @@ -462,14 +470,14 @@ "$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(CC_FLA= GS) $(ASLCC_FLAGS) $(INC) ${src} "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLI= NK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $= (GENFW_FLAGS) - =20 - =20 + + "$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASLCC_FL= AGS) $(INC) ${src} "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLI= NK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) $(OUTPUT_DIR)(+= )${s_dir}(+)${s_base}.dll $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecof= f $(GENFW_FLAGS) - =20 - =20 + + [Masm16-Code-File] ?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16 @@ -492,14 +500,14 @@ Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base= }.i "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(= INC) ${d_path}(+)${s_base}.iii "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) $(L= IBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group - =20 + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base= }.i "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(= INC) ${d_path}(+)${s_base}.iii "$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib = $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${ds= t} - =20 + =20 [Nasm-to-Binary-Code-File] @@ -635,8 +643,8 @@ "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUI= D) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS) "$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst} - =20 + GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --= hiibinpackage $(HII_BINARY_PACKAGES) - =20 - =20 + + diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 8f0e6cb..54c3dc5 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -3,7 +3,7 @@ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -231,11 +231,12 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Intel(r) ACPI Compiler from # https://acpica.org/downloads # GCC5 -Linux,Windows- Requires: -# GCC 5 with LTO support, targeting x86_64-lin= ux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi +# GCC 5 with LTO support, targeting x86_64-lin= ux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu # Optional: # Required to build platforms or ACPI tables: # Intel(r) ACPI Compiler from # https://acpica.org/downloads +# # CLANG35 -Linux,Windows- Requires: # Clang v3.5 or later, and GNU binutils target= ing aarch64-linux-gnu or arm-linux-gnueabi # Optional: @@ -1735,6 +1736,7 @@ DEFINE GCC_IA32_RC_FLAGS =3D -I binary -O e= lf32-i386 -B i386 DEFINE GCC_X64_RC_FLAGS =3D -I binary -O elf64-x86-64 -B= i386 --rename-section .data=3D.hii DEFINE GCC_ARM_RC_FLAGS =3D -I binary -O elf32-littlearm -B= arm --rename-section .data=3D.hii DEFINE GCC_AARCH64_RC_FLAGS =3D -I binary -O elf64-littleaarch64 -B= aarch64 --rename-section .data=3D.hii +DEFINE GCC_RISCV64_RC_FLAGS =3D -I binary -O elf64-littleriscv - B= riscv64 --rename-section .data=3D.hii =20 DEFINE GCC48_ALL_CC_FLAGS =3D -g -fshort-wchar -fno-builtin -fn= o-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdat= a-sections -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=3D$(BASE_NAME= )Strings DEFINE GCC48_IA32_X64_DLINK_COMMON =3D -nostdlib -Wl,-n,-q,--gc-sections= -z common-page-size=3D0x20 @@ -1806,6 +1808,21 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D DEF(GCC49_A= RM_ASLDLINK_FLAGS) DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D DEF(GCC49_AARCH64_ASLDLINK_FLAGS) DEFINE GCC5_ASLCC_FLAGS =3D DEF(GCC49_ASLCC_FLAGS) -fno-lto =20 +DEFINE GCC5_RISCV_ALL_CC_FLAGS =3D -g -fshort-wchar -fn= o-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdat= a-sections -c -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=3D$(BASE_N= AME)Strings +DEFINE GCC5_RISCV_ALL_DLINK_COMMON =3D -nostdlib -n -q --gc= -sections -z common-page-size=3D0x40 +DEFINE GCC5_RISCV_ALL_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_D= LINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DE= ST_DIR_DEBUG)/$(BASE_NAME).map +DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS =3D --defsym=3DPECOFF_HE= ADER_SIZE=3D0x220 --script=3D$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds +DEFINE GCC5_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -ima= cros $(DEST_DIR_DEBUG)/AutoGen.h +DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-co= mpare -Wno-pointer-compare + +DEFINE GCC5_RISCV64_ARCH =3D rv64imafdc +DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable +DEFINE GCC5_RISCV32_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_= DEBUG)/$(BASE_NAME).map +DEFINE GCC5_RISCV64_CC_FLAGS =3D DEF(GCC5_RISCV_ALL_CC_FLAGS= ) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) -march=3DDEF(GCC5_RISCV64_AR= CH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno= -asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=3D8 = -mcmodel=3Dmedany -mabi=3Dlp64 +DEFINE GCC5_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_FL= AGS) -melf64lriscv --oformat=3Delf64-littleriscv --no-relax +DEFINE GCC5_RISCV64_DLINK2_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK2_F= LAGS) +DEFINE GCC5_ASM_FLAGS =3D DEF(GCC5_RISCV_ALL_ASM_FLAG= S) -march=3DDEF(GCC5_RISCV64_ARCH) -mcmodel=3Dmedany -mabi=3Dlp64 + ##########################################################################= ########## # # GCC 4.8 - This configuration is used to compile under Linux to produce @@ -2247,6 +2264,49 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-pa= ge-size=3D0x20 NOOPT_GCC5_AARCH64_DLINK_FLAGS =3D DEF(GCC5_AARCH64_DLINK_FLAGS) -O0 NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-page-size=3D0x20 -O0 =20 +##########################################################################= ######### +##########################################################################= ########## +# +# GCC RISC-V This configuration is used to compile under Linux to produce +# PE/COFF binaries using GCC RISC-V tool chain +# +##########################################################################= ########## + +#*_GCC5_*_*_FAMILY =3D GCC + +#*_GCC5_*_MAKE_PATH =3D DEF(GCC49_IA32_PREFIX)make +#*_GCC5_*_PP_FLAGS =3D DEF(GCC_PP_FLAGS) +#*_GCC5_*_ASLPP_FLAGS =3D DEF(GCC_ASLPP_FLAGS) +#*_GCC5_*_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS) +#*_GCC5_*_VFRPP_FLAGS =3D DEF(GCC_VFRPP_FLAGS) +#*_GCC5_*_APP_FLAGS =3D +#*_GCC5_*_ASL_FLAGS =3D DEF(IASL_FLAGS) +#*_GCC5_*_ASL_OUTFLAGS =3D DEF(IASL_OUTFLAGS) + +################## +# GCC5 RISCV64 definitions +################## +*_GCC5_RISCV64_OBJCOPY_PATH =3D ENV(GCC5_RISCV64_PREFIX)objcopy +*_GCC5_RISCV64_CC_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_SLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc-ar +*_GCC5_RISCV64_DLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)ld +*_GCC5_RISCV64_ASLDLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)ld +*_GCC5_RISCV64_ASM_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_PP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_VFRPP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_ASLCC_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_ASLPP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc +*_GCC5_RISCV64_RC_PATH =3D ENV(GCC5_RISCV64_PREFIX)objcopy + +*_GCC5_RISCV64_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS) +*_GCC5_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV32_RISCV64_ASLDLINK_= FLAGS) +*_GCC5_RISCV64_ASM_FLAGS =3D DEF(GCC5_ASM_FLAGS) +*_GCC5_RISCV64_CC_FLAGS =3D DEF(GCC5_RISCV64_CC_FLAGS) -save-t= emps +*_GCC5_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV64_DLINK_FLAGS) +*_GCC5_RISCV64_DLINK2_FLAGS =3D DEF(GCC5_RISCV64_DLINK2_FLAGS) +*_GCC5_RISCV64_RC_FLAGS =3D DEF(GCC_RISCV64_RC_FLAGS) +*_GCC5_RISCV64_OBJCOPY_FLAGS =3D + ##########################################################################= ########## # # CLANG35 - This configuration is used to compile under Linux to produce diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Co= mmon/BasePeCoff.c index e7566b3..640f7a1 100644 --- a/BaseTools/Source/C/Common/BasePeCoff.c +++ b/BaseTools/Source/C/Common/BasePeCoff.c @@ -4,6 +4,7 @@ =20 Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage ( IN UINT64 Adjust ); =20 +RETURN_STATUS +PeCoffLoaderRelocateRiscVImage ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ); + STATIC RETURN_STATUS PeCoffLoaderGetPeHeader ( @@ -174,7 +183,8 @@ Returns: ImageContext->Machine !=3D EFI_IMAGE_MACHINE_X64 && \ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \ - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64) { + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \ + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) { if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) { // // There are two types of ARM images. Pure ARM and ARM/Thumb. @@ -802,6 +812,9 @@ Returns: case EFI_IMAGE_MACHINE_ARMT: Status =3D PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupDa= ta, Adjust); break; + case EFI_IMAGE_MACHINE_RISCV64: + Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupD= ata, Adjust); + break; default: Status =3D RETURN_UNSUPPORTED; break; diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/= C/Common/PeCoffLoaderEx.c index e367836..36797d9 100644 --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c @@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups =20 Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All = rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 --*/ @@ -61,6 +62,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMM64_SIGN_INST_WORD_POS_X 27 #define IMM64_SIGN_VAL_POS_X 63 =20 +// +// RISC-V definition. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + RiscVHi20Fixup =3D (UINT32 *) Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) | \ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + RiscVHi20Fixup =3D NULL; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25))); + } + RiscVHi20Fixup =3D NULL; + break; + + default: + return EFI_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} =20 /** Pass in a pointer to an ARM MOVT or MOVW immediate instruction and diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source= /C/GenFv/GenFvInternalLib.c index 908740d..fdbdd42 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -4,6 +4,7 @@ This file contains the internal functions required to gener= ate a Firmware Volume Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
Portions Copyright (c) 2016 HP Development Company, L.P.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 =20 BOOLEAN mArm =3D FALSE; +BOOLEAN mRiscV =3D FALSE; STATIC UINT32 MaxFfsAlignment =3D 0; BOOLEAN VtfFileFlag =3D FALSE; =20 @@ -2274,6 +2276,104 @@ Returns: } =20 EFI_STATUS +UpdateRiscvResetVectorIfNeeded ( + MEMORY_FILE *FvImage, + FV_INFO *FvInfo + ) +/*++ + +Routine Description: + This parses the FV looking for SEC and patches that address into the + beginning of the FV header. + + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h + +Arguments: + FvImage Memory file for the FV memory image/ + FvInfo Information read from INF file. + +Returns: + + EFI_SUCCESS Function Completed successfully. + EFI_ABORTED Error encountered. + EFI_INVALID_PARAMETER A required parameter was NULL. + EFI_NOT_FOUND PEI Core file not found. + +--*/ +{ + EFI_STATUS Status; + UINT16 MachineType; + EFI_FILE_SECTION_POINTER SecPe32; + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress; + + UINT32 bSecCore; + UINT32 tmp; + + + // + // Verify input parameters + // + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Initialize FV library + // + InitializeFvLib (FvImage->FileImage, FvInfo->Size); + + // + // Find the Sec Core + // + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FI= LETYPE_SECURITY_CORE, &SecPe32); + if(EFI_ERROR(Status)) { + printf("skip because Secutiry Core not found\n"); + return EFI_SUCCESS; + } + + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL); + + Status =3D GetCoreMachineType(SecPe32, &MachineType); + if(EFI_ERROR(Status)) { + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type f= or SEC core."); + return EFI_ABORTED; + } + + if (MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) { + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Mac= hine type is not RiscV."); + return EFI_ABORTED; + } + + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32,= &SecCoreEntryAddress); + if(EFI_ERROR(Status)) { + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point ad= dress for SEC Core."); + return EFI_ABORTED; + } + + VerboseMsg("SecCore entry point Address =3D 0x%llX", (unsigned long long= ) SecCoreEntryAddress); + VerboseMsg("BaseAddress =3D 0x%llX", (unsigned long long) FvInfo->BaseAd= dress); + bSecCore =3D (SecCoreEntryAddress - FvInfo->BaseAddress); + VerboseMsg("offset =3D 0x%llX", bSecCore); + + if(bSecCore > 0x0fffff) { + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of= start of the FV"); + return EFI_ABORTED; + } + + tmp =3D bSecCore; + bSecCore =3D 0; + //J-type + bSecCore =3D (tmp&0x100000)<<11; //imm[20] at bit[31] + bSecCore |=3D (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21] + bSecCore |=3D (tmp&0x000800)<<9; //imm[11] at bit[20] + bSecCore |=3D (tmp&0x0FF000); //imm[19:12] at bit[19:12] + bSecCore |=3D 0x6F; //JAL opcode + + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore)); + + return EFI_SUCCESS; +} + +EFI_STATUS GetPe32Info ( IN UINT8 *Pe32, OUT UINT32 *EntryPoint, @@ -2365,7 +2465,8 @@ Returns: // Verify machine type is supported // if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D EF= I_IMAGE_MACHINE_X64) && (*MachineType !=3D EFI_IMAGE_MACHINE_EBC) && - (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64)) { + (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64) && + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) { Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE3= 2 file."); return EFI_UNSUPPORTED; } @@ -2808,7 +2909,8 @@ Returns: Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad = file between the last file and the VTF file."); goto Finish; } - if (!mArm) { + + if (!mArm && !mRiscV) { // // Update reset vector (SALE_ENTRY for IPF) // Now for IA32 and IA64 platform, the fv which has bsf file must ha= ve the @@ -2843,6 +2945,22 @@ Returns: FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16)); } =20 + if (mRiscV) { + // + // Update RISCV reset vector. + // + Status =3D UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDa= taInfo); + if (EFI_ERROR (Status)) { + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector= for RISC-V."); + goto Finish; + } + // + // Update Checksum for FvHeader + // + FvHeader->Checksum =3D 0; + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16)); + } + // // Update FV Alignment attribute to the largest alignment of all the FFS= files in the FV // @@ -3430,6 +3548,10 @@ Returns: mArm =3D TRUE; } =20 + if (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_RISCV64) { + mRiscV =3D TRUE; + } + // // Keep Image Context for PE image in FV // @@ -3583,7 +3705,7 @@ Returns: ImageContext.DestinationAddress =3D NewPe32BaseAddress; Status =3D PeCoffLoaderRelocateImage (&ImageC= ontext); if (EFI_ERROR (Status)) { - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s", FileName); + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s Status=3D%d", FileName, Status); free ((VOID *) MemoryImagePointer); return Status; } diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/G= enFw/Elf32Convert.c index 46089ff..4095b7c 100644 --- a/BaseTools/Source/C/GenFw/Elf32Convert.c +++ b/BaseTools/Source/C/GenFw/Elf32Convert.c @@ -3,6 +3,7 @@ Elf32 Convert solution =20 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -141,8 +142,8 @@ InitializeElf32 ( Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN= "); return FALSE; } - if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M))) { - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_A= RM"); + if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M) || (mEhdr->e_machine =3D=3D EM_RISCV))) { + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32 machi= ne."); return FALSE; } if (mEhdr->e_version !=3D EV_CURRENT) { diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index 3d6319c..2aa09fd 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -3,6 +3,7 @@ Elf64 convert solution =20 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise Development = LP. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "ElfConvert.h" #include "Elf64Convert.h" =20 +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) { + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machi= ne."); return FALSE; } if (mEhdr->e_version !=3D EV_CURRENT) { @@ -481,6 +488,7 @@ ScanSections64 ( switch (mEhdr->e_machine) { case EM_X86_64: case EM_AARCH64: + case EM_RISCV64: mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64); break; default: @@ -690,6 +698,11 @@ ScanSections64 ( NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_AARCH64; NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC; break; + case EM_RISCV64: + NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64; + NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC; + break; + default: VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_m= achine); NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_X64; @@ -769,6 +782,11 @@ WriteSections64 ( Elf_Shdr *SecShdr; UINT32 SecOffset; BOOLEAN (*Filter)(Elf_Shdr *); + UINT32 Value; + UINT32 Value2; + UINT8 *Pass1Targ =3D NULL; + Elf_Shdr *Pass1Sym =3D NULL; + Elf64_Half Pass1SymSecIndex =3D 0; Elf64_Addr GOTEntryRva; =20 // @@ -893,13 +911,14 @@ WriteSections64 ( if (SymName =3D=3D NULL) { SymName =3D (const UINT8 *)""; } + if (mEhdr->e_machine !=3D EM_RISCV64) { + Error (NULL, 0, 3000, "Invalid", + "%s: Bad definition for symbol '%s'@%#llx or unsupporte= d symbol type. " + "For example, absolute and undefined symbols are not su= pported.", + mInImageName, SymName, Sym->st_value); =20 - Error (NULL, 0, 3000, "Invalid", - "%s: Bad definition for symbol '%s'@%#llx or unsupported = symbol type. " - "For example, absolute and undefined symbols are not supp= orted.", - mInImageName, SymName, Sym->st_value); - - exit(EXIT_FAILURE); + exit(EXIT_FAILURE); + } } SymShdr =3D GetShdrByIndex(Sym->st_shndx); =20 @@ -1114,6 +1133,128 @@ WriteSections64 ( default: Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE= (Rel->r_info)); } + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) { + switch (ELF_R_TYPE(Rel->r_info)) { + case R_RISCV_NONE: + break; + case R_RISCV_32: + *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymSh= dr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); + break; + case R_RISCV_64: + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoff= SectionsOffset[Sym->st_shndx]; + break; + case R_RISCV_HI20: + Pass1Targ =3D Targ; + Pass1Sym =3D SymShdr; + Pass1SymSecIndex =3D Sym->st_shndx; + break; + case R_RISCV_LO12_I: + if (Pass1Sym =3D=3D SymShdr && Pass1Targ !=3D NULL && Pass1Sym= SecIndex =3D=3D Sym->st_shndx && Pass1SymSecIndex !=3D 0) { + Value =3D (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value =3D Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx]; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)Pass1Targ =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)Pass1Targ, 0, 1= 2)); + *(UINT32 *)Targ =3D (RV_X (Value, 0, 12) << 20) | \ + (RV_X (*(UINT32 *)Targ, 0, 20)); + } + Pass1Sym =3D NULL; + Pass1Targ =3D NULL; + Pass1SymSecIndex =3D 0; + break; + + case R_RISCV_LO12_S: + if (Pass1Sym =3D=3D SymShdr && Pass1Targ !=3D NULL && Pass1Sym= SecIndex =3D=3D Sym->st_shndx && Pass1SymSecIndex !=3D 0) { + Value =3D (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UI= NT32 *)Targ, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value =3D Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx]; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)Pass1Targ =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)Pass1Targ, 0, 1= 2)); + + Value2 =3D *(UINT32 *)Targ & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Targ =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) <<= 7) | (RV_X(Value, 5, 7) << 25))); + } + Pass1Sym =3D NULL; + Pass1Targ =3D NULL; + Pass1SymSecIndex =3D 0; + break; + + case R_RISCV_PCREL_HI20: + Pass1Targ =3D Targ; + Pass1Sym =3D SymShdr; + Pass1SymSecIndex =3D Sym->st_shndx; + + Value =3D (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20)); + break; + case R_RISCV_PCREL_LO12_I: + if (Pass1Targ !=3D NULL && Pass1Sym !=3D NULL && Pass1SymSecIn= dex !=3D 0) { + int i; + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Pass1Targ, 12, 20)); + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); + if(Value & (RISCV_IMM_REACH/2)) { + Value |=3D ~(RISCV_IMM_REACH-1); + } + Value =3D Value - Pass1Sym->sh_addr + mCoffSectionsOffset[Pa= ss1SymSecIndex]; + if(-2048 > (INT32)Value) { + i =3D (-Value / 4096); + Value2 -=3D i; + Value +=3D 4096 * i; + if(-2048 > (INT32)Value) { + Value2 -=3D 1; + Value +=3D 4096; + } + } + else if( 2047 < (INT32)Value) { + i =3D (Value / 4096); + Value2 +=3D i; + Value -=3D 4096 * i; + if(2047 < (INT32)Value) { + Value2 +=3D 1; + Value -=3D 4096; + } + } + + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UIN= T32*)Targ, 0, 20)); + *(UINT32 *)Pass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*= (UINT32 *)Pass1Targ, 0, 12)); + } + Pass1Sym =3D NULL; + Pass1Targ =3D NULL; + Pass1SymSecIndex =3D 0; + break; + + case R_RISCV_ADD64: + case R_RISCV_SUB64: + case R_RISCV_ADD32: + case R_RISCV_SUB32: + case R_RISCV_BRANCH: + case R_RISCV_JAL: + case R_RISCV_GPREL_I: + case R_RISCV_GPREL_S: + case R_RISCV_CALL: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + case R_RISCV_RELAX: + case R_RISCV_SUB6: + case R_RISCV_SET6: + case R_RISCV_SET8: + case R_RISCV_SET16: + case R_RISCV_SET32: + break; + + default: + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE= (Rel->r_info)); + } } else { Error (NULL, 0, 3000, "Invalid", "Not a supported machine type"); } @@ -1133,6 +1274,7 @@ WriteRelocations64 ( UINT32 Index; EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr; EFI_IMAGE_DATA_DIRECTORY *Dir; + UINT32 RiscVRelType; =20 for (Index =3D 0; Index < mEhdr->e_shnum; Index++) { Elf_Shdr *RelShdr =3D GetShdrByIndex(Index); @@ -1237,6 +1379,108 @@ WriteRelocations64 ( default: Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s= unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF= _R_TYPE(Rel->r_info)); } + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) { + RiscVRelType =3D ELF_R_TYPE(Rel->r_info); + switch (RiscVRelType) { + case R_RISCV_NONE: + break; + + case R_RISCV_32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_HIGHLOW); + break; + + case R_RISCV_64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_DIR64); + break; + + case R_RISCV_HI20: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_HI20); + break; + + case R_RISCV_LO12_I: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_LOW12I); + break; + + case R_RISCV_LO12_S: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_LOW12S); + break; + + case R_RISCV_ADD64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_SUB64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_ADD32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_SUB32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_BRANCH: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_JAL: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_GPREL_I: + case R_RISCV_GPREL_S: + case R_RISCV_CALL: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + case R_RISCV_RELAX: + case R_RISCV_SUB6: + case R_RISCV_SET6: + case R_RISCV_SET8: + case R_RISCV_SET16: + case R_RISCV_SET32: + case R_RISCV_PCREL_HI20: + case R_RISCV_PCREL_LO12_I: + break; + + default: + printf ("Unsupported RISCV64 ELF relocation type 0x%x, offse= t: %lx\n", RiscVRelType, Rel->r_offset); + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s u= nsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R= _TYPE(Rel->r_info)); + } } else { Error (NULL, 0, 3000, "Not Supported", "This tool does not sup= port relocations for ELF with e_machine %u (processor type).", (unsigned) m= Ehdr->e_machine); } diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/Gen= Fw/elf_common.h index 15c9e33..1321f78 100644 --- a/BaseTools/Source/C/GenFw/elf_common.h +++ b/BaseTools/Source/C/GenFw/elf_common.h @@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD =20 Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development = LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 =20 @@ -178,6 +179,8 @@ typedef struct { #define EM_X86_64 62 /* Advanced Micro Devices x86-64 */ #define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */ #define EM_AARCH64 183 /* ARM 64bit Architecture */ +#define EM_RISCV64 243 /* 64bit RISC-V Architecture */ +#define EM_RISCV 244 /* 32bit RISC-V Architecture */ =20 /* Non-standard or deprecated. */ #define EM_486 6 /* Intel i486. */ @@ -979,5 +982,64 @@ typedef struct { #define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative of= fset to GOT entry without REX prefix, relaxable. */ #define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relativ= e offset to GOT entry with REX prefix, relaxable. */ =20 +/* + * RISC-V relocation types + */ + +/* Relocation types used by the dynamic linker */ +#define R_RISCV_NONE 0 +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JUMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_TPREL64 11 =20 +/* Relocation types not used by the dynamic linker */ +#define R_RISCV_BRANCH 16 +#define R_RISCV_JAL 17 +#define R_RISCV_CALL 18 +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 +#define R_RISCV_LO12_I 27 +#define R_RISCV_LO12_S 28 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GNU_VTINHERIT 41 +#define R_RISCV_GNU_VTENTRY 42 +#define R_RISCV_ALIGN 43 +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 +#define R_RISCV_RVC_LUI 46 +#define R_RISCV_GPREL_I 47 +#define R_RISCV_GPREL_S 48 +#define R_RISCV_TPREL_I 49 +#define R_RISCV_TPREL_S 50 +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 #endif /* !_SYS_ELF_COMMON_H_ */ diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTo= ols/Source/C/Include/IndustryStandard/PeImage.h index 44037d1..2ed3008 100644 --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h @@ -6,6 +6,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -41,6 +42,7 @@ #define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only #define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/T= humb 2 Little Endian #define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Lit= tle Endian +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA =20 // // Support old names for backward compatible @@ -50,6 +52,7 @@ #define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 #define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT #define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64 +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64 =20 #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE @@ -504,7 +507,10 @@ typedef struct { #define EFI_IMAGE_REL_BASED_HIGHADJ 4 #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 #define EFI_IMAGE_REL_BASED_IA64_IMM64 9 #define EFI_IMAGE_REL_BASED_DIR64 10 =20 diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/= Python/Common/DataType.py index 8ae1bd2..fc23e8c 100644 --- a/BaseTools/Source/Python/Common/DataType.py +++ b/BaseTools/Source/Python/Common/DataType.py @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Developme= nt LP. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent =20 ## @@ -52,7 +53,9 @@ TAB_ARCH_ARM =3D 'ARM' TAB_ARCH_EBC =3D 'EBC' TAB_ARCH_AARCH64 =3D 'AARCH64' =20 -ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_COMMON} +TAB_ARCH_RISCV64 =3D 'RISCV64' + +ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON} =20 SUP_MODULE_BASE =3D 'BASE' SUP_MODULE_SEC =3D 'SEC' @@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE =3D {8:'=3DQ', 0:'=3DB', 16:""} =20 -TAB_COMPILER_MSFT =3D 'MSFT' \ No newline at end of file +TAB_COMPILER_MSFT =3D 'MSFT' --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47775): https://edk2.groups.io/g/devel/message/47775 Mute This Topic: https://groups.io/mt/34258222/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47776+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47776+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200588; cv=none; d=zoho.com; s=zohoarc; b=Szz2KS7vNWa9Gqktaaa/PdSkKHVRSEj2AyF/WOkepTHRzp0Jzn4TTjid/fnaAK3k34rNvPSg5nTFIv12ezess/7ePjF61C3aISlMWmBJrDL1TUMdUTf5eOsTuLfPwcVaIDH5XJTUsv/ET3Qfc0mdIX37vgE0M1Pc4VXsHFf9Cbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200588; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+TautBippzRH1IK38bUZ2TG9nbbaNOapfsxfTtwW4eE=; b=Z2fAHj6n8C03vhqC0eL5YjDqkA1rIj7gizhh5H1oUdBAjIMRGVGp3eSz+CS1q9cGVMzBs+VCcQQK6eFlPq2Ju/MfZbbiqQR8h4dCweDyI5seVeIgK7b7qfx90xedFIsdk6EgVmPfu/9AiPCMhp983Cz1u9C7ITVC9FUKqgnsjl4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47776+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200588836718.6609992692344; Sun, 22 Sep 2019 18:03:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tHRAYY1788612x0pi3sLu0KG; Sun, 22 Sep 2019 18:03:08 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:08 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114sC000496 for ; Mon, 23 Sep 2019 01:03:07 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 2v5wffe06j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:07 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id A4CC057 for ; Mon, 23 Sep 2019 01:03:06 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id B9ABF5D; Mon, 23 Sep 2019 01:03:05 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Date: Mon, 23 Sep 2019 08:31:51 +0800 Message-Id: <1569198715-31552-27-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: rTOPr4x6uVH47uhKWmRsBEaDx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200588; bh=qKmAIMz27lr9shNAu67bBlaAqygoEuMyM/DR9cJi0is=; h=Cc:Date:From:Reply-To:Subject:To; b=LAp/VgowEOyEsQGVtvTlKGF/Z0j7eiLIUh6Hb7RblIFNLtXODHvyJGXcvWE81YwSlbB NTcryn8RfzfXvGxImKv8Wf5CCO8kFv8d+eoEsjrDffAgKBMeCmAYaO8IV8atgmRPTdYaF dX/UePU8Zwkwb+t4wSoU+va3TMxgbUD+zuw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds causes PE32 relocation error. This is the temporaty solution untill we find the root casue. Signed-off-by: Abner Chang --- BaseTools/Scripts/GccBaseRiscV.lds | 66 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBase= RiscV.lds new file mode 100644 index 0000000..7f9fae6 --- /dev/null +++ b/BaseTools/Scripts/GccBaseRiscV.lds @@ -0,0 +1,66 @@ +/** @file + + Unified linker script for GCC based builds + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +SECTIONS { + + /* + * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequenc= e of + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs + * between 32-bit and 64-bit builds). The actual start of the .text sect= ion + * will be rounded up based on its actual alignment. + */ + . =3D PECOFF_HEADER_SIZE; + + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) { + *(.text .text.* .stub .gnu.linkonce.t.*) + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.got .got.*) + + /* + * The contents of AutoGen.c files are constant from the POV of the pr= ogram, + * but most of its contents end up in .data or .bss by default since f= ew of + * the variable definitions that get emitted are declared as CONST. + */ + *:AutoGen.obj(.data.g*Guid) + } + + /* + * The alignment of the .data section should be less than or equal to the + * alignment of the .text section. This ensures that the relative offset + * between these sections is the same in the ELF and the PE/COFF version= s of + * this binary. + */ + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) { + *(.data .data.* .gnu.linkonce.d.*) + *(.bss .bss.*) + } + + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : { + KEEP (*(.eh_frame)) + } + + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : { + *(.rela .rela.*) + } + + /DISCARD/ : { + *(.note.GNU-stack) + *(.gnu_debuglink) + *(.interp) + *(.dynsym) + *(.dynstr) + *(.dynamic) + *(.hash) + *(.comment) + *(COMMON) + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47776): https://edk2.groups.io/g/devel/message/47776 Mute This Topic: https://groups.io/mt/34258223/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47777+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47777+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200590; cv=none; d=zoho.com; s=zohoarc; b=KJExiXdBpBTTtgsKmaREPiasCR9/cOULWN4wdAv3Gpit+ydjqifW7tvSx+0R2K71tljWWyInaD380C37j72XAscz3zkKbX9xDLemBn21h9yFODIyoOgytJoWCow8O3ZQGN37ew7YJqIR2fyyC7DG0952Z8BQPyJEgXWOaE82k3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200590; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+AVpGcmIeujInZxsNirj89EBFT1Zsse21fXehH6o8iQ=; b=aRrcAQBG7WoFnxYtl2niG2k0XbYH9voJ06pNmEuxXCFCgaAsQVDgrpkYYo0Le0QR5VitmHuQQcJXVJ4T6NK/9jrzvBO0ZE7x4O/aQmKlR3mB+o+2xB012n3De4HQ9Oq1VTiyoH421ectjpoimWo0hchinkuwJvL2bNxM7VJ64Qc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47777+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200590477817.4498358288719; Sun, 22 Sep 2019 18:03:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id g5EzYY1788612x8hW1lFjh4S; Sun, 22 Sep 2019 18:03:10 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:09 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N115Mf017318 for ; Mon, 23 Sep 2019 01:03:08 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5sxd7h3b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:08 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id F34C55C for ; Mon, 23 Sep 2019 01:03:07 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 1759A45; Mon, 23 Sep 2019 01:03:06 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms. Date: Mon, 23 Sep 2019 08:31:52 +0800 Message-Id: <1569198715-31552-28-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: A24FY2LJ0T2fatbdjodJV6f0x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200590; bh=F1jRJ2lHuJc16tKMCZqeslpS9K/Id5f1vOrvZrN5p2w=; h=Cc:Date:From:Reply-To:Subject:To; b=vtVL+TjB9cif0CxmglDzAdQZxh1S7HW3ZMfIO63lju6Ipo5DyOvu+uDI8WBSDdgoBlo 02rY0cuSNjKCzZezUE5k6aJVROcjixdTR+Im2HA67casRT5NzK7dpPDgeynlvuGuiN9Vr rk+li/1zqSAX5tuK0I6Rd+SlrKnd9rUUBAE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7 and type 44 records. Signed-off-by: Abner Chang --- RiscVPkg/Include/ProcessorSpecificDataHob.h | 95 ++++++ RiscVPkg/Include/SmbiosProcessorSpecificData.h | 58 ++++ RiscVPkg/RiscVPkg.dec | 6 + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 +++++++++++++++++= ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 32 ++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 58 ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 + .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 + 8 files changed, 613 insertions(+) create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include= /ProcessorSpecificDataHob.h new file mode 100644 index 0000000..6798a9d --- /dev/null +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h @@ -0,0 +1,95 @@ +/** @file + Definition of Processor Specific Data HOB. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_ +#define _RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H_ + +#include + +#define TO_BE_FILLED 0 +#define TO_BE_FILLED_BY_VENDOR 0 +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 +#define TO_BE_FILLED_BY_CODE 0 + +#pragma pack(1) + +/// +/// RISC-V processor specific data HOB +/// +typedef struct { + EFI_GUID ParentPrcessorGuid; + UINTN ParentProcessorUid; + EFI_GUID CoreGuid; + VOID *Context; // The additional information of this core whi= ch + // built in PEI phase and carried to DXE phase. + // The content is pocessor or platform specifi= c. + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; +} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB; + +/// +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE4 SmbiosType4Processor; + UINT16 EndingZero; +} RISC_V_PROCESSOR_TYPE4_DATA_HOB; + +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF + +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03 + +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3 +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIG= URATION_SOCKET_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_= CONFIGURATION_SOCKET_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5 +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONF= IGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7 +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_= CONFIGURATION_ENABLE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACH= E_CONFIGURATION_ENABLE_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8 +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE7 SmbiosType7Cache; + UINT16 EndingZero; +} RISC_V_PROCESSOR_TYPE7_DATA_HOB; + +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache; +} RISC_V_PROCESSOR_SMBIOS_DATA_HOB; + +#pragma pack() + +#endif diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Incl= ude/SmbiosProcessorSpecificData.h new file mode 100644 index 0000000..36aa4ab --- /dev/null +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h @@ -0,0 +1,58 @@ +/** @file + Industry Standard Definitions of RISC-V Processor Specific data defined = in + below link for complaiant with SMBIOS Table Specification v3.3.0. + https://github.com/riscv/riscv-smbios + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_ +#define _SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_ + +#include + +#include + +#pragma pack(1) + +typedef enum{ + RegisterUnsupported =3D 0x00, + RegisterLen32 =3D 0x01, + RegisterLen64 =3D 0x02, + RegisterLen128 =3D 0x03 +} RISC_V_REGISTER_LENGTH; + +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100 + +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0) +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2) +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3) +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7) + +/// +/// RISC-V processor specific data for SMBIOS type 44 +/// +typedef struct { + UINT16 Revision; + UINT8 Length; + RISCV_UINT128 HartId; + UINT8 BootHartId; + RISCV_UINT128 MachineVendorId; + RISCV_UINT128 MachineArchId; + RISCV_UINT128 MachineImplId; + UINT32 InstSetSupported; + UINT8 PrivilegeModeSupported; + RISCV_UINT128 MModeExcepDelegation; + RISCV_UINT128 MModeInterruptDelegation; + UINT8 HartXlen; + UINT8 MachineModeXlen; + UINT8 Reserved; + UINT8 SupervisorModeXlen; + UINT8 UserModeXlen; +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA; + +#pragma pack() +#endif + diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec index a91392f..b316223 100644 --- a/RiscVPkg/RiscVPkg.dec +++ b/RiscVPkg/RiscVPkg.dec @@ -24,6 +24,12 @@ gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} =20 [PcdsFixedAtBuild] + # Processor Specific Data GUID HOB GUID + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0= x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2= , 0xFA, 0x93}|VOID*|0x00001000 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0= x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA= , 0x6F}|VOID*|0x00001001 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x= 36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C,= 0x25, 0xB9}|VOID*|0x00001002 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0x= B4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF,= 0x71, 0x65}|VOID*|0x00001003 + # # 1000000000 # PcdRiscVMachineTimerTickInNanoSecond =3D -----------------------------= ---------- diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.c new file mode 100644 index 0000000..032f559 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -0,0 +1,339 @@ +/** @file + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and t= ype 44 records. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "RiscVSmbiosDxe.h" + +#define RISCV_SMBIOS_DEBUG_INFO 1 + +EFI_SMBIOS_PROTOCOL *Smbios; + +/** + This function builds SMBIOS type 7 record according to + the given RISC_V_PROCESSOR_TYPE7_DATA_HOB. + + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB + @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_DATA_HOB + @param SmbiosHandle Pointer to SMBIOS_HANDLE + + @retval EFI_STATUS + +**/ +static +EFI_STATUS +BuildSmbiosType7 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + IN RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob, + OUT SMBIOS_HANDLE *SmbiosHandle +) +{ + EFI_STATUS Status; + SMBIOS_HANDLE Handle; + + if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob->PrcessorGu= id) || + Type4DataHob->ProcessorUid !=3D Type7DataHob->ProcessorUid) { + return EFI_INVALID_PARAMETER; + } + Handle =3D SMBIOS_HANDLE_PI_RESERVED; + Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMATIO= N; + Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE7); + Type7DataHob->SmbiosType7Cache.Hdr.Handle =3D 0; + Type7DataHob->EndingZero =3D 0; + Status =3D Smbios->Add (Smbios, NULL, &Handle, &Type7DataHob->SmbiosType= 7Cache.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type= 7\n")); + return Status; + } + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was added. S= MBIOS Handle: 0x%x\n", Handle)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Cache belone to processor = GUID: %g\n", &Type7DataHob->PrcessorGuid)); + DEBUG ((DEBUG_INFO, " Cache belone processor UI= D: %d\n", Type7DataHob->ProcessorUid)); + DEBUG ((DEBUG_INFO, " =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((DEBUG_INFO, " Socket Designation: %d\n",= Type7DataHob->SmbiosType7Cache.SocketDesignation)); + DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\= n", Type7DataHob->SmbiosType7Cache.CacheConfiguration)); + DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n= ", Type7DataHob->SmbiosType7Cache.MaximumCacheSize)); + DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n", T= ype7DataHob->SmbiosType7Cache.InstalledSize)); + DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\= n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType)); + DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n"= , Type7DataHob->SmbiosType7Cache.CurrentSRAMType)); + DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n", Type= 7DataHob->SmbiosType7Cache.CacheSpeed)); + DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%= x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType)); + DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n"= , Type7DataHob->SmbiosType7Cache.SystemCacheType)); + DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n", Ty= pe7DataHob->SmbiosType7Cache.Associativity)); +#endif + + *SmbiosHandle =3D Handle; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 4 record according to + the given RISC_V_PROCESSOR_TYPE4_DATA_HOB. + + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB + @param SmbiosHandle Pointer to SMBIOS_HANDLE + + @retval EFI_STATUS + +**/ +static +EFI_STATUS +BuildSmbiosType4 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + OUT SMBIOS_HANDLE *SmbiosHandle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData; + SMBIOS_HANDLE Cache; + SMBIOS_HANDLE Processor; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 4.\n")); + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Ty= pe4DataHob->PrcessorGuid)); + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Typ= e4DataHob->ProcessorUid)); + + Type4DataHob->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4DataHob->SmbiosType4Processor.L2CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4DataHob->SmbiosType4Processor.L3CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType7GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS Type7 = data HOB found.\n")); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processo= rs. + // + do { + Type7HobData =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)GET_GUID_HOB_DATA = (GuidHob); + Status =3D BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache); + if (EFI_ERROR (Status)) { + return Status; + } + if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CON= FIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) { + Type4DataHob->SmbiosType4Processor.L1CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) { + Type4DataHob->SmbiosType4Processor.L2CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) { + Type4DataHob->SmbiosType4Processor.L3CacheHandle =3D Cache; + } else { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Improper cache level = of SMBIOS handle %d\n", Cache)); + } + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e7GuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + + // + // Build SMBIOS Type 4 record + // + Processor =3D SMBIOS_HANDLE_PI_RESERVED; + Type4DataHob->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_IN= FORMATION; + Type4DataHob->SmbiosType4Processor.Hdr.Length =3D sizeof(SMBIOS_TABLE_TY= PE4); + Type4DataHob->SmbiosType4Processor.Hdr.Handle =3D 0; + Type4DataHob->EndingZero =3D 0; + Status =3D Smbios->Add (Smbios, NULL, &Processor, &Type4DataHob->SmbiosT= ype4Processor.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type= 4\n")); + return Status; + } + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was added. S= MBIOS Handle: 0x%x\n", Processor)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Socket StringID: %d\n", Ty= pe4DataHob->SmbiosType4Processor.Socket)); + DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n", T= ype4DataHob->SmbiosType4Processor.ProcessorType)); + DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n",= Type4DataHob->SmbiosType4Processor.ProcessorFamily)); + DEBUG ((DEBUG_INFO, " Processor Manufacture Stri= ngID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture)); + DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n"= , \ + Type4DataHob->SmbiosType4Processor.ProcessorId.Signature, Type4D= ataHob->SmbiosType4Processor.ProcessorId.FeatureFlags)); + DEBUG ((DEBUG_INFO, " Processor Version StringID= : %d\n", Type4DataHob->SmbiosType4Processor.ProcessorVersion)); + DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4Dat= aHob->SmbiosType4Processor.Voltage)); + DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n", T= ype4DataHob->SmbiosType4Processor.ExternalClock)); + DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n", Type4D= ataHob->SmbiosType4Processor.MaxSpeed)); + DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n", Ty= pe4DataHob->SmbiosType4Processor.CurrentSpeed)); + DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4Data= Hob->SmbiosType4Processor.Status)); + DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n",= Type4DataHob->SmbiosType4Processor.ProcessorUpgrade)); + DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n", = Type4DataHob->SmbiosType4Processor.L1CacheHandle)); + DEBUG ((DEBUG_INFO, " L2 Cache Handle: 0x%x\n",T= ype4DataHob->SmbiosType4Processor.L2CacheHandle)); + DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n", = Type4DataHob->SmbiosType4Processor.L3CacheHandle)); + DEBUG ((DEBUG_INFO, " Serial Number StringID: %d= \n", Type4DataHob->SmbiosType4Processor.SerialNumber)); + DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n",= Type4DataHob->SmbiosType4Processor.AssetTag)); + DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n= ", Type4DataHob->SmbiosType4Processor.PartNumber)); + DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4Da= taHob->SmbiosType4Processor.CoreCount)); + DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n", = Type4DataHob->SmbiosType4Processor.EnabledCoreCount)); + DEBUG ((DEBUG_INFO, " Thread Count: %d\n", Type4= DataHob->SmbiosType4Processor.ThreadCount)); + DEBUG ((DEBUG_INFO, " Processor Characteristics:= 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics)); + DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n"= , Type4DataHob->SmbiosType4Processor.ProcessorFamily2)); + DEBUG ((DEBUG_INFO, " Core Count 2: %d\n", Type4= DataHob->SmbiosType4Processor.CoreCount2)); + DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n",= Type4DataHob->SmbiosType4Processor.EnabledCoreCount2)); + DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n", Typ= e4DataHob->SmbiosType4Processor.ThreadCount2)); +#endif + + *SmbiosHandle =3D Processor; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 44 record according.. + + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB + @param Type4Handle SMBIOS handle of type 4 + + @retval EFI_STATUS + +**/ +EFI_STATUS +BuildSmbiosType44 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + IN SMBIOS_HANDLE Type4Handle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData; + SMBIOS_HANDLE RiscVType44; + SMBIOS_TABLE_TYPE44 *Type44Ptr; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: Building Type 44 for...\n"= )); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Ty= pe4DataHob->PrcessorGuid)); + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Typ= e4DataHob->ProcessorUid)); +#endif + + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC_V_PROCESSOR_SPE= CIFIC_DATA_HOB found.\n")); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for multiple cores. + // + do { + ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)GET_GU= ID_HOB_DATA (GuidHob); + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4Da= taHob->PrcessorGuid) || + ProcessorSpecificData->ParentProcessorUid !=3D Type4DataHob->Process= orUid) { + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + if (GuidHob =3D=3D NULL) { + break; + } + continue; + } + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, "[ =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"= )); + DEBUG ((DEBUG_INFO, "[ Core GUID: %g\n", &Proce= ssorSpecificData->CoreGuid)); +#endif + + Type44Ptr =3D AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SM= BIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero. + if (Type44Ptr =3D=3D NULL) { + return EFI_NOT_FOUND; + } + Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION; + Type44Ptr->Hdr.Handle =3D 0; + Type44Ptr->Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA); + Type44Ptr->RefHandle =3D Type4Handle; + Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof(SMBIOS_RISC_V_PROC= ESSOR_SPECIFIC_DATA); + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =3D Type4DataHob->= SmbiosType4Processor.ProcessorFamily2 - + ProcessorFamilyR= iscvRV32 + \ + ProcessorSpecifi= cBlockArchTypeRiscVRV32; + CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->Proc= essorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA)); + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((DEBUG_INFO, "[ Core type: %d\n", Type44= Ptr->ProcessorSpecificBlock.ProcessorArchType)); + DEBUG ((DEBUG_INFO, " HartId =3D 0x%x\n", ((= SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L)= ); + DEBUG ((DEBUG_INFO, " Is Boot Hart? =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId= )); + DEBUG ((DEBUG_INFO, " PrivilegeModeSupported= =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->P= rivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " MModeExcepDelegation = =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MM= odeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " MModeInterruptDelegati= on =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-= >MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " HartXlen =3D 0x%x\n", = ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen)); + DEBUG ((DEBUG_INFO, " MachineModeXlen =3D 0x= %x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineM= odeXlen)); + DEBUG ((DEBUG_INFO, " SupervisorModeXlen =3D= 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->Super= visorModeXlen)); + DEBUG ((DEBUG_INFO, " UserModeXlen =3D 0x%x\= n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXle= n)); + DEBUG ((DEBUG_INFO, " InstSetSupported =3D 0= x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSet= Supported)); + DEBUG ((DEBUG_INFO, " MachineVendorId =3D 0x= %x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineV= endorId.Value64_L)); + DEBUG ((DEBUG_INFO, " MachineArchId =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArc= hId.Value64_L)); + DEBUG ((DEBUG_INFO, " MachineImplId =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImp= lId.Value64_L)); +#endif + + // + // Add to SMBIOS table. + // + RiscVType44 =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Ty= pe 44\n")); + return Status; + } + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was added= . SMBIOS Handle: 0x%x\n", RiscVType44)); + + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificD= ataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + return EFI_SUCCESS; +} + +/** + Entry point of RISC-V SMBIOS builder. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +RiscVSmbiosBuilderEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData; + SMBIOS_HANDLE Processor; + + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a entry\n", __FUNCTION__)= ); + + Status =3D gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&Smbios + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS Protocol = fail\n")); + return Status; + } + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType4GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS inform= ation found.\n")); + return EFI_NOT_FOUND; + } + Type4HobData =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)GET_GUID_HOB_DATA (G= uidHob); + Status =3D EFI_NOT_FOUND; + // + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processo= rs. + // + do { + Status =3D BuildSmbiosType4 (Type4HobData, &Processor); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type= 4 created.\n")); + ASSERT (FALSE); + } + Status =3D BuildSmbiosType44 (Type4HobData, Processor); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type= 44 found.\n")); + ASSERT (FALSE); + } + + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e4GuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + DEBUG ((DEBUG_INFO, "[RISC-V SMBIOS Builder]: %a exit\n", __FUNCTION__)); + return Status; +} + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.h new file mode 100644 index 0000000..dfa1fc6 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h @@ -0,0 +1,32 @@ +/** @file + RISC-V SMBIOS Builder DXE module header file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RISC_V_SMBIOS_DXE_H_ +#define _RISC_V_SMBIOS_DXE_H_ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#endif + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.inf new file mode 100644 index 0000000..59b814a --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf @@ -0,0 +1,58 @@ +## @file +# RISC-V SMBIOS DXE module. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSmbiosDxe + MODULE_UNI_FILE =3D RiscVSmbiosDxe.uni + FILE_GUID =3D 5FC01647-AADD-42E1-AD99-DF4CB89F5A92 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D RiscVSmbiosBuilderEntry + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + HobLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Sources] + RiscVSmbiosDxe.c + RiscVSmbiosDxe.h + +[Protocols] + gEfiSmbiosProtocolGuid # Consumed + +[Guids] + + +[Pcd] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + +[Depex] + gEfiSmbiosProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.uni new file mode 100644 index 0000000..1bffe09 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni @@ -0,0 +1,12 @@ +// /** @file +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor = SMBIOS Builder" + +#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Proc= essor SMBIOS Type 4, 7, 44 records." + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPk= g/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni new file mode 100644 index 0000000..4b37ca2 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni @@ -0,0 +1,13 @@ +// /** @file +// RISC-V SMBIOS Builder Localized Strings and Content +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"RISC-V SMBIOS Record Builder DXE Driver" + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47777): https://edk2.groups.io/g/devel/message/47777 Mute This Topic: https://groups.io/mt/34258224/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47778+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47778+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200591; cv=none; d=zoho.com; s=zohoarc; b=MPSmoU05JKTn58ofesymQ9PETTiSuLbNwyJR0st61CCsD90pSLzG63Ak05objgetGTFluSc/sPy9j2cwEdWeMYtdG1jY00ngth+L8LuYUc4nayQrbl3/E0bLqzXwyU2b1+JPlCoeEJittbnidh1fJgmsa0hQKM5nNdE0NOLF9SI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200591; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=QWgQoxsovuYUaeFTv4TOX/rXzbz0a4jWG9Wu/Q8dd4I=; b=lHzDXVUzJi+iCLUrlfnwtKe3SOa2iV//r+d9zWSJ27THKyMuyAZE34Z3QIRrCmWaiu3+cSl2OIP5CmAsbghXo16ZC0Pgi5ropshZEDjgPr8h0JqPXevvexS4q7sejtPXwr2bKwsabSz9vTkYwA+C8zohvTDBhzN60ogbwY0sJSs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47778+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200591635787.0853832667482; Sun, 22 Sep 2019 18:03:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aSo5YY1788612xZfS1qXvvEu; Sun, 22 Sep 2019 18:03:11 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:10 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N113d3021563 for ; Mon, 23 Sep 2019 01:03:10 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay92-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:09 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 591C460 for ; Mon, 23 Sep 2019 01:03:09 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 676734A; Mon, 23 Sep 2019 01:03:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Date: Mon, 23 Sep 2019 08:31:53 +0800 Message-Id: <1569198715-31552-29-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: vS8sUHdEMGBGyeHKP0WdQJyYx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200591; bh=SHrGUplNGMARn7TraCVYJ3oiVdzZgZxCyzC+e2Xw0Xc=; h=Cc:Date:From:Reply-To:Subject:To; b=eR62Vg9Yo4fuA6BMt6QA8P1+hsVfA8Nfbs8+G6UpEXjJysWnA1Y60mstzaDVL1XDh2R J5g0hKrb/rwQL55kY9dLb2hoHfm1DD5IxdP5InREmYDwIEgJNXxl8WxM70v3hq32t1QRW frxQHpDFix4T/of3pfby2GYs6bxB6Btqc78= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add submodule opensbi under RiscVPkg. The current supported opensbi version for RISC-V edk2 port is commit ID:ce228ee (tags/v0.4). Signed-off-by: Abner Chang --- .gitmodules | 16 ++++++++++------ RiscVPkg/opensbi | 1 + 2 files changed, 11 insertions(+), 6 deletions(-) create mode 160000 RiscVPkg/opensbi diff --git a/.gitmodules b/.gitmodules index 508f0c1..6d3e28c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,10 @@ -[submodule "CryptoPkg/Library/OpensslLib/openssl"] - path =3D CryptoPkg/Library/OpensslLib/openssl - url =3D https://github.com/openssl/openssl -[submodule "SoftFloat"] - path =3D ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3 - url =3D https://github.com/ucb-bar/berkeley-softfloat-3.git +[submodule "CryptoPkg/Library/OpensslLib/openssl"] + path =3D CryptoPkg/Library/OpensslLib/openssl + url =3D https://github.com/openssl/openssl +[submodule "SoftFloat"] + path =3D ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3 + url =3D https://github.com/ucb-bar/berkeley-softfloat-3.git +[submodule "RiscVPkg/opensbi"] + path =3D RiscVPkg/opensbi + url =3D https://github.com/riscv/opensbi.git + diff --git a/RiscVPkg/opensbi b/RiscVPkg/opensbi new file mode 160000 index 0000000..ce228ee --- /dev/null +++ b/RiscVPkg/opensbi @@ -0,0 +1 @@ +Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47778): https://edk2.groups.io/g/devel/message/47778 Mute This Topic: https://groups.io/mt/34258225/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47779+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47779+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200592; cv=none; d=zoho.com; s=zohoarc; b=CwtA3eQ55q9QSoJrpCWETktM27SQXpMUmKLSPfJJi0sJMgEU/15oJJZm6iD7Vh5foCg7OgYEYf/ppJdsl+mBsW6lf9lBUl6rbdLaoM1zRXPujzK3w/wIAWvy+YdCWdf7oYud3nAziLCclpzQ35fJvXIuOomTFcrSuOcm7BKGomU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200592; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=6b7L5SkdZSwee75AQHZpUGNcbHw2KeMEkt2YFBq7DSI=; b=DdhdCOFH18jAR/iBWKHN030VLCoFOvuicLhtpEPYTZueJt2b7O6qbhAfhZp00xggHNobdYjIVGVMrStfYgtgveiO02gagJnnWNsxJ6IvtV8hwesDKgxJWnR5xh0cTj5cOVcq1b9s0OwPT+YdFmbNhB7/zwQFCTHDAoCTq4mV5so= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47779+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200592904152.980780043403; Sun, 22 Sep 2019 18:03:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LkdZYY1788612xShRlUfGOzI; Sun, 22 Sep 2019 18:03:12 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:12 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114B1021580 for ; Mon, 23 Sep 2019 01:03:11 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay9b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:11 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id AA52B57 for ; Mon, 23 Sep 2019 01:03:10 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id BF1964C; Mon, 23 Sep 2019 01:03:09 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Date: Mon, 23 Sep 2019 08:31:54 +0800 Message-Id: <1569198715-31552-30-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: HZ4AwSFhZ9ryZb4ROhWbu3OEx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200592; bh=1gs3B8N1pZGxkRrI4y2tmVL55HCv7uMeTD2OHydAGPU=; h=Cc:Date:From:Reply-To:Subject:To; b=aGxmVTMyR2MjxY2u3cNzizD+tpJSfFVJidbOr/H+jn+OlP5MYzfpSuJh2gMRV5Bk7pR JpO1wgjBS0pUm7my9llcBLH2ID46jRo6046cUCOqFBVs+hsD9oIFEAqZGBNzmcEBrnp2H Q3sN/oak99ww0wkMCCpDcU1lom0gmY6VSgc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RiscVEdk2Readme.md Signed-off-by: Abner Chang --- RiscVEdk2Readme.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 RiscVEdk2Readme.md diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md new file mode 100644 index 0000000..ec691fe --- /dev/null +++ b/RiscVEdk2Readme.md @@ -0,0 +1,34 @@ +This branch is used to contribute RISC-V architecture to EDK2 + +The branch owner:
+Abner Chang < abner.chang@hpe.com >
+Gilbert Chen < gilbert.chen@hpe.com > + +## RISC-V EDK2 Port Introduction +RISC-V is an open ISA which was designed to support research and education= of computer architecture, but now it becomes +a standard open Instruction Set Architecture for industry implementations.= The RISC-V edk2 project is to create a new processor binding in UEFI spec = and have the RISC-V edk2 implementation. The goal is to have RISC-V edk2 po= rt as the firmware reference +for RISC-V platforms. + +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V Op= enSbi (https://github.com/riscv/opensbi) library integrated. RiscVPkg provi= des the generic and common modules of RISC-V prcessor. The first edk2 RISC-= V platform is SiFive U500 FPGA whcih is maintained in U500Pkg under Platfor= m/RiscV/SiFive in edk2-platform repository. + +## RISC-V EDK2 Package +``` +RiscVPkg - RISC-V processor package. This package provides RISC-V proc= essor related protocols/libraries accroding + to UEFI specification and edk2 implementations. +``` +## Toolchain of RISC-V EDK2 port +To build edk2 RISC-V platform requires GCC RISC-V toolchain, refer to http= s://github.com/riscv/riscv-gnu-toolchain for the details. The commit ID 648= 79b24 of riscv-gnu-toolchain repository is verified to build RISC-V edk2 pl= atform and boot to EFI SHELL successfully. You have to clone the toolchain = from above link and check out commit:64879b24 for building RISC-V edk2 port= . The commit later than 64879b24 causes system hangs at the PEI phase to DX= E phase transition. We are still figuring out the root cause. + +## EDK2 Build Target +"RISCV64" ARCH is the RISC-V architecture which currently supported and ve= rified. The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu= -toolchain @64879b24 as mentioned above, toolchain tag is "GCC5" which is d= eclared in tools_def.txt.
+Below is the edk2 build options for building RISC-V RV64 platform,
+``` +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5 +``` +For example,
+``` +build -a RISCV64 -p Platform/SiFive/U500/U500.dsc -t GCC5 +``` + +Make sure RISC-V toolchain is built succesfully and the toolchain binaries= are generated in somewhere you specified when building toolchain. 'GCC5_RI= SCV64_PREFIX' is the cross compilation prefix to toolchain binraries.
+For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknow= n-elf-' before you build RISC-V edk2 port. --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47779): https://edk2.groups.io/g/devel/message/47779 Mute This Topic: https://groups.io/mt/34258226/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 23:24:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47780+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47780+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1569200594; cv=none; d=zoho.com; s=zohoarc; b=O6t4eLMa9rqGuYeJakgI4Y2GJMhZ83uRhcHJ7tbTQ3QUzlXRYjVg2menr4Mxee1b9YE32KaS/TKDhnIcvXtI68ZjFZl4q2VyOD4rB4/mAZnSDJzJaBvf9Wd2c6doakEpw9iJXb8MmPzcr/oS8iS/ysD2by3hDBakMuSgf8piM34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569200594; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=r4CBrrRhRxHbNsoVMPqVF+j9KRe922H+tK2fNUqDO5o=; b=GU4El8k7Jz/lr5hVru3u5sPrGSXuXgtdmHcQRCOCAoHzopXatbMTlC050CTCH+Q4V1l1tDintmUQlaYJkYiHbun2Tfjk9Fw7jVS+JWydZ4qmsp+FhrdX4IVb3F/m4CsYGP4BfQqawrwQhfeYE5MofHDizk0isPi5DsHGBHH8VNg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47780+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569200594655745.559393087627; Sun, 22 Sep 2019 18:03:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8birYY1788612x9648jteAO7; Sun, 22 Sep 2019 18:03:14 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:13 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N112fN012872 for ; Mon, 23 Sep 2019 01:03:12 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v5adnjua7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:12 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 1685151 for ; Mon, 23 Sep 2019 01:03:12 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 1EC1F55; Mon, 23 Sep 2019 01:03:10 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Date: Mon, 23 Sep 2019 08:31:55 +0800 Message-Id: <1569198715-31552-31-git-send-email-abner.chang@hpe.com> In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: OAPV2Qt2YfbrAnzY4VsVUctux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569200594; bh=/wgNj0rEr26iqY/Gqvp1NLg2xsk/6294a63zcJ3sGb0=; h=Cc:Date:From:Reply-To:Subject:To; b=I2cQirsA2XDWoWGr8KsCG80p+Uzztqd+xDU7e12Iz9TfWYvzGvCF/J7sobcim6ZeAKl YdC09AyGHb3qKaj7JCy9HH1gUMiWB3bpqZp/3UhmKUtag4/hdGGgAvqVcCprLIf9vaXAj qEc6bZ9Q2Es3ZjJnxamcNkBm6/wLqdYU0Pw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add maintainer and reviewer of RiscVPkg. Signed-off-by: Abner Chang --- Maintainers.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 919bacc..11449a5 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -408,6 +408,11 @@ F: PcAtChipsetPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg M: Ray Ni =20 +RiscVPkg: RISCV64 architecture modules +F: RISCV64/ +M: Abner Chang +R: Gilbert Chen + SecurityPkg F: SecurityPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47780): https://edk2.groups.io/g/devel/message/47780 Mute This Topic: https://groups.io/mt/34258227/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-