From nobody Mon Feb 9 02:14:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46784+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46784+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595615; cv=none; d=zoho.com; s=zohoarc; b=YCiA3jmB759ytMdH5s+qHTN4bnEUKD71vO//PpuftECIAImkhc9Pe64uOcnGTjh/UyHLCM4H8Map7+Nj25JOwjmW3MTpqW5RJHJKw1w2tOrYyQtaNcbMcPCBCSU8gn0Se4TwwpqBc+/RTICNF46yeqN6UUpFqv4OvqcmOKnqHnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595615; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=JSluAs+Y0MtAnL97ELP4kef+/MhvQeeLHZh/lQ+joLo=; b=enDQMLq7EsPBl7FD8BMr2mOUORwC2/ByqO+KmGwDa5gtmzWAQMiHYkGoCMXIAWwS+64Iw6wIwV3pYNKvRp7yJ/5RWLr73CGMREDHnt91wf80eQSkFHQRyHFEZKc30S7L2oG+w49aCsJgxA/QBgsFAc+7UCYNsbK2qDkOE37VR3g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46784+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595615345377.8933692384545; Wed, 4 Sep 2019 04:13:35 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:34 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBi15003899 for ; Wed, 4 Sep 2019 11:13:33 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 2usvqnwy81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:33 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id BA48BAF for ; Wed, 4 Sep 2019 11:13:32 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D171639; Wed, 4 Sep 2019 11:13:31 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 07/22]: MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. Date: Wed, 4 Sep 2019 18:43:02 +0800 Message-Id: <1567593797-26216-8-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595615; bh=/m0b8wf2zRNmnPLjjQ3J1bT/KqbAiP8OsUwaV+RyRL4=; h=Cc:Date:From:Reply-To:Subject:To; b=Kjn7RJN4QxS9jjzu2nZbgLVySjcKByFR6BfS3mVH8kHJuskQJfqy375n7EdchHyD7k0 Y2zxGMh1pBsaGhhHqCxh6M/iUIliIDQvfgV90JwzktKGBGQnJfi7fkcWNYbUPjIBDsD2G jryS9uiEn4DmUkHvEYwgWAt37kOM5qckW3o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V MMIO library instance. RISC-V only supports memory map I/O. However= the first implementation of RISC-V EDK2 port uses PC/AT as the RISC-V platform spec. We have to keep= the I/O functions as the temporary solution. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +- MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 697 +++++++++++++++++= ++++ 2 files changed, 703 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 457cce9..fbb568e 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -2,13 +2,14 @@ # Instance of I/O Library using compiler intrinsics. # # I/O Library that uses compiler intrinsics to perform IN and OUT instruc= tions -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO = requests. +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated in= to MMIO requests. # MMIO requests are forwarded directly to memory. For EBC, I/O port requ= ests # ASSERT(). # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP.= All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -55,6 +56,9 @@ [Sources.AARCH64] IoLibArm.c =20 +[Sources.RISCV64] + IoLibRiscV.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Librar= y/BaseIoLibIntrinsic/IoLibRiscV.c new file mode 100644 index 0000000..6173d25 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c @@ -0,0 +1,697 @@ +/** @file + Common I/O Library routines for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseIoLibIntrinsicInternal.h" + +/** + Reads an 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +MmioRead8 ( + IN UINTN Address + ) +{ + return *(volatile UINT8*)Address; +} + +/** + Writes an 8-bit MMIO register. + + Writes the 8-bit MMIO register specified by Address with the value speci= fied + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +MmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + *(volatile UINT8 *)Address =3D Value; + return Value; +} + +/** + Reads a 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address. The 16-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +MmioRead16 ( + IN UINTN Address + ) +{ + return *(volatile UINT16 *)Address; +} + +/** + Writes a 16-bit MMIO register. + + Writes the 16-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +MmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + *(volatile UINT16 *)Address =3D Value; + return Value; +} + +/** + Reads a 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address. The 32-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +MmioRead32 ( + IN UINTN Address + ) +{ + return *(volatile UINT32 *)Address; +} + +/** + Writes a 32-bit MMIO register. + + Writes the 32-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The valu return *(volatile UINT8*)Address; + to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +MmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + *(volatile UINT32 *)Address =3D Value; + return Value; +} + +/** + Reads a 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address. The 64-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +MmioRead64 ( + IN UINTN Address + ) +{ + return *(volatile UINT64 *)Address; +} + +/** + Writes a 64-bit MMIO register. + + Writes the 64-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + *(volatile UINT64 *)Address =3D Value; + return Value; +} + +/** + Reads an 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port. The 8-bit read value is retu= rned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +IoRead8 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port use PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions for temporary solution. + // + return *(volatile UINT8*)Port; +} + +/** + Writes an 8-bit I/O port. + + Writes the 8-bit I/O port specified by Port with the value specified by = Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ + +UINT8 +EFIAPI +IoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT8 *)Port =3D Value; + return Value; +} + +/** + Reads a 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port. The 16-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +IoRead16 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT16*)Port; +} + +/** + Writes a 16-bit I/O port. + + Writes the 16-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +IoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT16*)Port =3D Value; + return Value; +} + +/** + Reads a 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port. The 32-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +IoRead32 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT32*)Port; +} + +/** + Writes a 32-bit I/O port. + + Writes the 32-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +IoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT32*)Port =3D Value; + return Value; +} + +/** + Reads a 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port. The 64-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +IoRead64 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT64*)Port; +} + +/** + Writes a 64-bit I/O port. + + Writes the 64-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written to the I/O port. + +**/ +UINT64 +EFIAPI +IoWrite64 ( + IN UINTN Port, + IN UINT64 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT64*)Port =3D Value; + return 0; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT8 *Buffer8; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer8 =3D (UINT8 *)Buffer; + while (Count-- > 0) { + *Buffer8++ =3D *(volatile UINT8 *)Port++; + } +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT8 *Buffer8; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer8 =3D (UINT8 *)Buffer; + while (Count-- > 0) { + *(volatile UINT8 *)Port++ =3D *Buffer8++; + } +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT16 *Buffer16; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer16 =3D (UINT16 *)Buffer; + while (Count-- > 0) { + *Buffer16++ =3D *(volatile UINT16 *)Port++; + } +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT16 *Buffer16; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer16 =3D (UINT16 *)Buffer; + while (Count-- > 0) { + *(volatile UINT16 *)Port++ =3D *Buffer16++; + } +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT32 *Buffer32; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer32 =3D (UINT32 *)Buffer; + while (Count-- > 0) { + *Buffer32++ =3D *(volatile UINT32 *)Port++; + } +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT32 *Buffer32; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer32 =3D (UINT32 *)Buffer; + while (Count-- > 0) { + *(volatile UINT32 *)Port++ =3D *Buffer32++; + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46784): https://edk2.groups.io/g/devel/message/46784 Mute This Topic: https://groups.io/mt/33137129/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-