From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46778+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46778+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595609; cv=none; d=zoho.com; s=zohoarc; b=hy5823BdnEg4jjtidXB35XtsvoCBF7bvD9tT7WN60miQroVIHBK2a+TCvZqlGD62nuTR3M5tW99B+AMJwwKB83I4W/2zaDC71y9ABmASChnPpq4JTKrzy/vp4Aj/Q5kSuW6zeQkv+41bYB/zaplzD7S9CBiZJB/xgUAXuzz0juI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595609; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=CEntNBlpp6Yzu0jXCpd5hMB7KW//PHhYTY4ZLV+I/nw=; b=ZnXvW7VRUIvyqGEYpdcrW10QTvjKAD9MEmfP63FF7keXEuRpiqNH8yHOkuv5CxmCjPD1rFL6Xi8KytfHOQndBcx7OxKpqZp1g1BRw8SeeUfMwi0xZWJi9vsCd/EPn6Z7ZPx7ovXq+ENYInSuTu+itz3ULmAxeZ+YYFf/B5wqB0o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46778+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595609305881.6374941777594; Wed, 4 Sep 2019 04:13:29 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:26 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBfGQ020079 for ; Wed, 4 Sep 2019 11:13:25 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7ud-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:25 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 6C8A877 for ; Wed, 4 Sep 2019 11:13:24 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 8343036; Wed, 4 Sep 2019 11:13:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 01/22]: RiscVPkg: RISC-V processor package. Date: Wed, 4 Sep 2019 18:42:56 +0800 Message-Id: <1567593797-26216-2-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595609; bh=sneZkv4jcgoDnJU4bhL6M5rdKcXec3j+HKTWmY41Uvc=; h=Cc:Date:From:Reply-To:Subject:To; b=q+2eMe+uSWC/lDb7HxQEfJOx3PBzra2oPcoVpAHogjBrPA/6pFI60qdKNPrjjMWv+qa Rv57yhCHHOOrfrpISkMt0XcYW71sP3VSwupoZGyRjFMvVKNjEvUIBBbMzT0rHrv/aR75j FQ2St0aS6RNFWjBD1bOfoq93P/nQec5E79U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add RiscVPkg package which provides RISC-V processor related drivers and = libraries. - Support RISC-V OpenSBI and RISC-V platforms Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/RiscVPkg.dec | 57 +++++++++++++++++++++++++++++++++++++++++= ++++ RiscVPkg/RiscVPkg.uni | Bin 0 -> 1718 bytes RiscVPkg/RiscVPkgExtra.uni | Bin 0 -> 1374 bytes 3 files changed, 57 insertions(+) create mode 100644 RiscVPkg/RiscVPkg.dec create mode 100644 RiscVPkg/RiscVPkg.uni create mode 100644 RiscVPkg/RiscVPkgExtra.uni diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec new file mode 100644 index 0000000..acf71fe --- /dev/null +++ b/RiscVPkg/RiscVPkg.dec @@ -0,0 +1,57 @@ +## @file RiscVPkg.dec +# This Package provides UEFI RISC-V modules and libraries. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D RiscVPkg + PACKAGE_UNI_FILE =3D RiscVPkg.uni + PACKAGE_GUID =3D 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + opensbi/include + opensbi/lib/utils/libfdt + +[LibraryClasses] + +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] + +[Guids] + gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} + gUefiRiscVMachineContextGuid =3D { 0xdad19cd5, 0x9d1f, 0x4f38, { 0xbc, 0= xba, 0x10, 0x81, 0xe4, 0xcd, 0xb7, 0x3f}} + +[PcdsFixedAtBuild] + # Processor Specific Data GUID HOB GUID + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0= x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2= , 0xFA, 0x93}|VOID*|0x00001000 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0= x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA= , 0x6F}|VOID*|0x00001001 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x= 36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C,= 0x25, 0xB9}|VOID*|0x00001002 + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0x= B4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF,= 0x71, 0x65}|VOID*|0x00001003 + + + # + # 1000000000 + # PcdRiscVMachineTimerTickInNanoSecond =3D -----------------------------= ---------- + # PcdRiscVMachineTimerFrequency= InHerz + # + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UIN= T64|0x00001010 + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000= |UINT64|0x00001011 + +[PcdsPatchableInModule] + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPkgExtra.uni diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni new file mode 100644 index 0000000000000000000000000000000000000000..550e30d5c9e5db4091e4ba5090e= 38413a5c69393 GIT binary patch literal 1718 zcmchXNpBND5QXcE#D8cx7eI*(95^6^h~r7H5@O2>fm1ZL6K8}SqqZ@a9}j%5dloy1 z1Sd3_UTb;vs;YngYFNV@|1&;k@9f$#o7t5;wnv=3Dmu4irQ+mRjEM|NFHZERl{r${+F zvjzJUoy>l6GU2RmEA#Acky)}&S?T-;*<0?e!dNeTRK6tf)iyzUYB$I_dxHI^%rEV^ zy|7od&-y(!z6YGEAXB08!Bdj^@mLd*Wx(2ET=3DUO@mpLn;Q4C$HGaqs@W0pqrF7zHb z>HDBNLGq0?Vdd=3Du_y=3DH?Hy8Xau;Ph+&c5Jag@kw$i(_!ik<{HL=3DgV=3DD29AV6yha9v z!m-QH5^f<9r-fZ)a?*2-dPBSz_cLqoT|#O&}9ktiP?uiKdtGHGN;Wnrz`1=3DUgM zHOX^}{n-vCM_$CinDKs;8NOsmz9Ucav1G4kN8l{{Rn_54tSX9Y?qi08`3JIhG41jb zx!fQ%%JmmH6GFDy;zE_SA``De&8r3@$CCGf@jB6a^4YkPgC!>;BAC!0yWZ zyIKvX-~?P<>ZoHUjEDAty*kaos^&rHyrvCVC4uRooiit#i<4-f%0ip|N|5LW%Ny*_G8Ab2IF<+uuTW!M&_@f=3D6c;Nc94;bI#jXm5omD-eV{1I+M=3DINMv>U3(oSW)4HsSNN$Y-1}dN58>mgFa;^`vJZ;oL%_Zu4^>4;liX)`OLI|G_^2v#JHJyCzG{?N{g(2L&GDO)SpAvBFbl+mf$wAckI>0sm)jwcT0p$^BQxYMns~1P^C=3DK&<C@6YNcfrUwIFSAxgbGY{Emp0&1+ z%B!p`WY2YJdo{LTpE(zm%;YOLkMTjOrW6 y+J&iO)3ijhIWXMtN?L@e8L(*oPG%luwI%n%TL35A}MR?_sM(CC|Utz|=3D+n literal 0 HcmV?d00001 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46778): https://edk2.groups.io/g/devel/message/46778 Mute This Topic: https://groups.io/mt/33137119/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46779+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46779+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595609; cv=none; d=zoho.com; s=zohoarc; b=fIbu12OYNEG9zxh/4aBqSxkfPnI+xBO/YkZ1t/0ZYq72IMCkRml8OBEasF6SqP75pNjc9lr6ExL7OKccXsyTynFdDLCUgxkolYj7usFNc2k5fROfjMnSpMHdXiaoEmfq19UL89+wU6TShRLPydV42GDYWv42vBDz6FbaSIAL6wc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595609; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=/idMkeVXKJH2vlkuQ5b28PN4n+gMQxcvLL2ovY3qV18=; b=Q55RK270aqKuoRWBea+kDCOb2vq4yLugrpzTegEvpB0Y/P9TfARQhVrXXsX2b6dg6EyoxMDSgUVGMS0tRLH+JNM6mxV/rdy073BEulsr171HMOfaBHOlGUIyzYGxMSRGwvQ97TcsqZJrjhB8L3BfiaFZwxir2BdgeYyDfm6P/Us= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46779+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595609207440.1188544096548; Wed, 4 Sep 2019 04:13:29 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:27 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBmj4010658 for ; Wed, 4 Sep 2019 11:13:26 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usgabm53m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:26 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 02E0AB0 for ; Wed, 4 Sep 2019 11:13:26 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D78FB36; Wed, 4 Sep 2019 11:13:24 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 02/22]: RiscVPkg/Include: Add header files of RISC-V CPU package Date: Wed, 4 Sep 2019 18:42:57 +0800 Message-Id: <1567593797-26216-3-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595608; bh=Bcy/+2YfLi3/dtMOeinwSKnkk8H3YHdtRs1oReiW/Rc=; h=Cc:Date:From:Reply-To:Subject:To; b=lU91CHNwQbObjBIy9AQJJfVTTfwAfepKH9K81I0ONJyN68fiVLswf6vDDRgPAbqRxOx 0orOhK+TJgXCa5uutCH2MvZ4z7QrMh64BO0lNrZjOieT5cs746IYWjLkARwiKgBu+XDAF jV+3rzkn7R/gfqLy4IPVBp+hES1eT30KbTw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V package library definitions. RiscV.h -Add RiscV.h which conform with RISC-V Privilege Spec v1.10. sbi.h sbi_bits.h sbi_types.h - Add definitions for RISC-V OpenSBI EDK2 port. RealTimeClockLib.h - Header file of platform level Real Time Clock library. SbiFirmwareContext.h - Header file of RISC-V OpenSBI Firmware Context of UEFI EDK2 implementatio= n. RiscVPlatformTempMemoryInitLib.h - Header file of temporary memory functions. RiscVPlatformDxeIplLib - Header file for supporting platform level DXE IPL on RISC-V platform. ProcessorSpecificDataHob.h - Header file of RISC-V processor specific information data hob. This infor= mation is built up by platform and consumed by RISC-V generic SMBIOS DXE dr= iver for building up SMBIOS records. SmbiosPrcessorSpecificData.h - Header file of RISC-V processor specific information for SMBIOS type 44 r= ecord. RiscVCpuLib.h - Add defitions of generic CSR functions Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/Include/Library/RealTimeClockLib.h | 136 +++++++++++++++++ RiscVPkg/Include/Library/RiscVCpuLib.h | 74 +++++++++ RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 47 ++++++ .../Library/RiscVPlatformTempMemoryInitLib.h | 23 +++ RiscVPkg/Include/ProcessorSpecificDataHob.h | 99 ++++++++++++ RiscVPkg/Include/RiscV.h | 168 +++++++++++++++++= ++++ RiscVPkg/Include/SmbiosProcessorSpecificData.h | 64 ++++++++ RiscVPkg/Include/sbi/SbiFirmwareContext.h | 44 ++++++ RiscVPkg/Include/sbi/sbi.h | 103 +++++++++++++ RiscVPkg/Include/sbi/sbi_bits.h | 23 +++ RiscVPkg/Include/sbi/sbi_types.h | 24 +++ 11 files changed, 805 insertions(+) create mode 100644 RiscVPkg/Include/Library/RealTimeClockLib.h create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib= .h create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h create mode 100644 RiscVPkg/Include/RiscV.h create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h create mode 100644 RiscVPkg/Include/sbi/sbi_types.h diff --git a/RiscVPkg/Include/Library/RealTimeClockLib.h b/RiscVPkg/Include= /Library/RealTimeClockLib.h new file mode 100644 index 0000000..2815b44 --- /dev/null +++ b/RiscVPkg/Include/Library/RealTimeClockLib.h @@ -0,0 +1,136 @@ +/** @file + Implement EFI RealTimeClock runtime services via RISC-V platform Lib. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __REAL_TIME_CLOCK_LIB__ +#define __REAL_TIME_CLOCK_LIB__ + + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ); + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ); + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ); + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ); + + + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +#endif + diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Libr= ary/RiscVCpuLib.h new file mode 100644 index 0000000..7a8e75a --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h @@ -0,0 +1,74 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __RISCV_CPU_LIB_H__ +#define __RISCV_CPU_LIB_H__ + +#include "RiscV.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext); + +UINT32 +RiscVGetScratch (VOID); + +UINT32 +RiscVGetTrapCause (VOID); + +UINT64 +RiscVReadMachineTimer (VOID); + +VOID +RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp(VOID); + +UINT64 +RiscVReadMachineIE(VOID); + +UINT64 +RiscVReadMachineIP(VOID); + +UINT64 +RiscVReadMachineStatus(VOID); + +VOID +RiscVWriteMachineStatus(UINT64); + +UINT64 +RiscVReadMachineTvec(VOID); + +UINT64 +RiscVReadMisa (VOID); + +UINT64 +RiscVReadMVendorId (VOID); + +UINT64 +RiscVReadMArchId (VOID); + +UINT64 +RiscVReadMImplId (VOID); + +#endif diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Incl= ude/Library/RiscVPlatformDxeIpl.h new file mode 100644 index 0000000..69ad310 --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h @@ -0,0 +1,47 @@ +/** @file + Header file of RISC-V platform DXE IPL + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights= reserved.
+=20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __RISC_V_PLATFORM_DXEIPL_H__ +#define __RISC_V_PLATFORM_DXEIPL_H__ + +typedef struct { + VOID *TopOfStack; + VOID *BaseOfStack; + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint; + EFI_PEI_HOB_POINTERS HobList; +} OPENSBI_SWITCH_MODE_CONTEXT; + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + =20 + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack=20 + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ); +#endif + diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/Ri= scVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h new file mode 100644 index 0000000..0ed3a6e --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h @@ -0,0 +1,23 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __RISCV_PLATFORM_TEMP_MEM_LIB_H__ +#define __RISCV_PLATFORM_TEMP_MEM_LIB_H__ + +#include "RiscV.h" + +VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemSize(VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemBase(VOID); +#endif diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include= /ProcessorSpecificDataHob.h new file mode 100644 index 0000000..4512277 --- /dev/null +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h @@ -0,0 +1,99 @@ +/** @file + Definition of Processor Specific Data HOB. + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials are licensed and made availa= ble under=20 + the terms and conditions of the BSD License that accompanies this distri= bution. =20 + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. = =20 + =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + +**/ +#ifndef __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__ +#define __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__ + +#include + +#define TO_BE_FILLED 0 +#define TO_BE_FILLED_BY_VENDOR 0 +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 +#define TO_BE_FILLED_BY_CODE 0 + +#pragma pack(1) + +/// +/// RISC-V processor specific data HOB +/// +typedef struct { + EFI_GUID ParentPrcessorGuid; + UINTN ParentProcessorUid; + EFI_GUID CoreGuid; + VOID *Context; // The additional information of this core whi= ch=20 + // built in PEI phase and carried to DXE phase. + // The content is pocessor or platform specifi= c. + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; +} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB; + +/// +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE4 SmbiosType4Processor; +} RISC_V_PROCESSOR_TYPE4_DATA_HOB; + +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF + +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03 + +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3 +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIG= URATION_SOCKET_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_= CONFIGURATION_SOCKET_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5 +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONF= IGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7 +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_= CONFIGURATION_ENABLE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACH= E_CONFIGURATION_ENABLE_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8 +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION) +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE7 SmbiosType7Cache; +} RISC_V_PROCESSOR_TYPE7_DATA_HOB; + +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache; +} RISC_V_PROCESSOR_SMBIOS_DATA_HOB; + +#pragma pack() + +#endif diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h new file mode 100644 index 0000000..f894429 --- /dev/null +++ b/RiscVPkg/Include/RiscV.h @@ -0,0 +1,168 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __RISCV_H__ +#define __RISCV_H__ + +#if defined(MDE_CPU_RISCV32) +#define RISC_V_XLEN_BITS 32 +#elif defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#elif defined (MDE_CPU_RISCV128) +#define RISC_V_XLEN_BITS 128 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x0000000= 1 << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +//#define RISCV_CSR_MACHINE_MTIME 0x701 +//#define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap ha= ndler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap= handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap= handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handl= er. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine = mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Incl= ude/SmbiosProcessorSpecificData.h new file mode 100644 index 0000000..8669b37 --- /dev/null +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h @@ -0,0 +1,64 @@ +/** @file + Industry Standard Definitions of RISC-V Processor Specific data defined = in + below link for complaiant with SMBIOS Table Specification v3.3.0.=20 + https://github.com/riscv/riscv-smbios=20 + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials are licensed and made availa= ble under=20 + the terms and conditions of the BSD License that accompanies this distri= bution. =20 + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. = =20 + =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + +**/ +#ifndef __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__ +#define __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__ + +#include + +#include + +#pragma pack(1) + +typedef enum{ + RegisterUnsupported =3D 0x00, + RegisterLen32 =3D 0x01, + RegisterLen64 =3D 0x02, + RegisterLen128 =3D 0x03 +} RISC_V_REGISTER_LENGTH; + +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100 + +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0) +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2) +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3) +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7) + +/// +/// RISC-V processor specific data for SMBIOS type 44 +/// +typedef struct { + UINT16 Revision; + UINT8 Length; + RISCV_UINT128 HartId; + UINT8 BootHartId; + RISCV_UINT128 MachineVendorId; + RISCV_UINT128 MachineArchId; + RISCV_UINT128 MachineImplId; + UINT32 InstSetSupported; + UINT8 PrivilegeModeSupported; + RISCV_UINT128 MModeExcepDelegation; + RISCV_UINT128 MModeInterruptDelegation; + UINT8 HartXlen; + UINT8 MachineModeXlen; + UINT8 Reserved; + UINT8 SupervisorModeXlen; + UINT8 UserModeXlen; +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA; + +#pragma pack() +#endif + diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/s= bi/SbiFirmwareContext.h new file mode 100644 index 0000000..eedaa44 --- /dev/null +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h @@ -0,0 +1,44 @@ +/** @file + RISC-V OpesbSBI Platform Firmware context definition + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __SBI_FIRMWARE_CONTEXT_H__ +#define __SBI_FIRMWARE_CONTEXT_H__ + +#include + +#define RISC_V_MAX_HART_SUPPORTED 16 + +// +// keep the structure member in 64-bit alignment. +// +#pragma pack(push) +#pragma pack(8) + +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension this core= supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture ID + RISCV_UINT128 MachineImplId; // Machine Implementation ID +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; + +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7) + +typedef struct { + VOID *PeiServiceTable; // PEI Service table + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +#pragma pack(pop) +#endif + diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index 0000000..537973b --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi.h @@ -0,0 +1,103 @@ +/** @file + SBI inline function calls. + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __SBI_H__ +#define __SBI_H__ + +#include +#include + +#define SBI_SET_TIMER 0=20 +#define SBI_CONSOLE_PUTCHAR 1=20 +#define SBI_CONSOLE_GETCHAR 2=20 +#define SBI_CLEAR_IPI 3=20 +#define SBI_SEND_IPI 4=20 +#define SBI_REMOTE_FENCE_I 5=20 +#define SBI_REMOTE_SFENCE_VMA 6=20 +#define SBI_REMOTE_SFENCE_VMA_ASID 7=20 +#define SBI_SHUTDOWN 8=20 + + +#define SBI_CALL(which, arg0, arg1, arg2) ({ \ + register uintptr_t a0 asm ("a0") =3D (uintptr_t)(arg0); \ + register uintptr_t a1 asm ("a1") =3D (uintptr_t)(arg1); \ + register uintptr_t a2 asm ("a2") =3D (uintptr_t)(arg2); \ + register uintptr_t a7 asm ("a7") =3D (uintptr_t)(which); \ + asm volatile ("ecall" \ + : "+r" (a0) \ + : "r" (a1), "r" (a2), "r" (a7) \ + : "memory"); \ + a0; \ +})=20 + +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)=20 +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)=20 +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)=20 +=20 +static inline void sbi_console_putchar(int ch)=20 +{=20 + SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);=20 +}=20 +=20 +static inline int sbi_console_getchar(void)=20 +{=20 + return SBI_CALL_0(SBI_CONSOLE_GETCHAR);=20 +}=20 +=20 +static inline void sbi_set_timer(uint64_t stime_value)=20 +{=20 +#if __riscv_xlen =3D=3D 32 + SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);=20 +#else=20 + SBI_CALL_1(SBI_SET_TIMER, stime_value);=20 +#endif=20 +}=20 +=20 +static inline void sbi_shutdown(void)=20 +{=20 + SBI_CALL_0(SBI_SHUTDOWN);=20 +}=20 +=20 +static inline void sbi_clear_ipi(void)=20 +{=20 + SBI_CALL_0(SBI_CLEAR_IPI);=20 +}=20 +=20 +static inline void sbi_send_ipi(const unsigned long *hart_mask)=20 +{=20 + SBI_CALL_1(SBI_SEND_IPI, hart_mask);=20 +}=20 +=20 +static inline void sbi_remote_fence_i(const unsigned long *hart_mask)=20 +{=20 + SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);=20 +}=20 +=20 +static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,=20 + unsigned long start,=20 + unsigned long size)=20 +{=20 + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);=20 +}=20 +=20 +static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_ma= sk,=20 + unsigned long start,=20 + unsigned long size,=20 + unsigned long asid)=20 +{=20 + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);=20 +}=20 + +#endif \ No newline at end of file diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bit= s.h new file mode 100644 index 0000000..4116ee6 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_bits.h @@ -0,0 +1,23 @@ +/** @file + RISC-V OpesbSBI header file reference. + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __EDK2_SBI_BITS_H__ +#define __EDK2_SBI_BITS_H__ + +#undef MAX +#undef MIN + +#include "../opensbi/include/sbi/sbi_bits.h" + +#endif \ No newline at end of file diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_ty= pes.h new file mode 100644 index 0000000..fe877f2 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_types.h @@ -0,0 +1,24 @@ +/** @file + RISC-V OpesbSBI header file reference. + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __EDK2_SBI_TYPES_H__ +#define __EDK2_SBI_TYPES_H__ + +#undef TRUE +#undef FALSE +#undef NULL + +#include "../opensbi/include/sbi/sbi_types.h" + +#endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46779): https://edk2.groups.io/g/devel/message/46779 Mute This Topic: https://groups.io/mt/33137120/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46780+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46780+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595609; cv=none; d=zoho.com; s=zohoarc; b=Tw4yU4UaRbkWS03q7JUmc461IOsBGzt3gACelb0EmbWid4XkcY2nYfNxhmpxQCp8xTHlNgzXXGJrXn+ZCIdGIcR/g/b+/D4Q+eLzK8QwWXygOU3eHiX+NHGW9pbeec9zEC8J5bka0E6oCamTv195/IGceE15zpweEQHUUTBYuK0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595609; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=p5/5qmlKoTNM42Fuc5ggB6ots4tZX9SiW3CKI7XTaac=; b=cMck3qBdgBM0ZELHop168Gr1fJG4m9nFtYBvWV/IgNwNX9qREcNhfJtTlF+JCxHpu5lIHSIxTIuktwDj7ZkE2/yTfZxKNQQjQvyZa532zlUuUeGWt8fOiruih/dvLB2JB5bcHV7zKEwJhrDDLZtkm4PqnsLH+fTm6th7t9kSTkk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46780+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156759560951833.55265650575234; Wed, 4 Sep 2019 04:13:29 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:28 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBnub024305 for ; Wed, 4 Sep 2019 11:13:28 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2ut55qu163-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:27 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 60DFCB1 for ; Wed, 4 Sep 2019 11:13:27 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 6CB7D39; Wed, 4 Sep 2019 11:13:26 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 03/22]: MdePkg: RISC-V sections in DEC file. Date: Wed, 4 Sep 2019 18:42:58 +0800 Message-Id: <1567593797-26216-4-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595609; bh=NUiS9m2QsYurHZGgXwRpOi+MDAjhP8Gy9dOwZ/tlIGw=; h=Cc:Date:From:Reply-To:Subject:To; b=M1WKKuB0txuYNeiTgUnplyW6VJmlTQoBaJbhCma4hpGV1aejntcC/vZkdepGO0dzdU3 khWwrfevHkaBtCr8l5wWX4hok6ZLakRPzhnG0DVNPV2xQzpnUO6+F8TPLee5Du7+AHvUx 0LBCLYXkKW8H2O2a+2HEAaVPLBij1NuWrKE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V sections in MdePkg.dec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/MdePkg.dec | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 3fd7d16..9673c3c 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -39,6 +39,15 @@ [Includes.AARCH64] Include/AArch64 =20 +[Includes.RISCV128] + Include/RiscV128 + +[Includes.RISCV64] + Include/RiscV64 + +[Includes.RISCV32] + Include/RiscV32 + [LibraryClasses] ## @libraryclass Provides most usb APIs to support the Hid requests de= fined in Usb Hid 1.1 spec # and the standard requests defined in Usb 1.1 spec. --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Date: Wed, 4 Sep 2019 18:42:59 +0800 Message-Id: <1567593797-26216-5-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595610; bh=cQmMHHmdxoqwwB6NEtqNT+OyTyo+K+9sCJu9KcLqq1I=; h=Cc:Date:From:Reply-To:Subject:To; b=rjMAWGqgbHQjgzqGkopbh9b4EnSxCnEI5DVtFhmHjwRAYifq5fFpFaowrkjtEIlRlBk uC6ffQSlEinWzpxwuGNELDSXC6uDgfd87cmzgLWX857LtPbjD1/9VfapPfiPl+0JK+Jf4 +obKWmbnyo8eO1doMwVP06/oAcekoDhCRNE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RISC-V processor related definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/Include/IndustryStandard/PeImage.h | 14 +- MdePkg/Include/Library/BaseLib.h | 67 ++++++ MdePkg/Include/Protocol/DebugSupport.h | 55 +++++ MdePkg/Include/Protocol/PxeBaseCode.h | 8 + MdePkg/Include/RiscV64/ProcessorBind.h | 336 ++++++++++++++++++++++++++= ++++ MdePkg/Include/Uefi/UefiBaseType.h | 25 +++ MdePkg/Include/Uefi/UefiSpec.h | 11 + 7 files changed, 513 insertions(+), 3 deletions(-) create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/Ind= ustryStandard/PeImage.h index 720bb08..47796b2 100644 --- a/MdePkg/Include/IndustryStandard/PeImage.h +++ b/MdePkg/Include/IndustryStandard/PeImage.h @@ -9,6 +9,8 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMAGE_FILE_MACHINE_X64 0x8664 #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 #define IMAGE_FILE_MACHINE_ARM64 0xAA64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 =20 // // EXE file formats @@ -478,9 +483,9 @@ typedef struct { /// #define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8 =20 -// -// Based relocation types. -// +/// +/// Based relocation types. +/// #define EFI_IMAGE_REL_BASED_ABSOLUTE 0 #define EFI_IMAGE_REL_BASED_HIGH 1 #define EFI_IMAGE_REL_BASED_LOW 2 @@ -488,7 +493,10 @@ typedef struct { #define EFI_IMAGE_REL_BASED_HIGHADJ 4 #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 #define EFI_IMAGE_REL_BASED_IA64_IMM64 9 #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9 #define EFI_IMAGE_REL_BASED_DIR64 10 diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 2a75bc0..5f0ee8d 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4,6 +4,8 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -124,6 +126,71 @@ typedef struct { =20 #endif // defined (MDE_CPU_AARCH64) =20 +#if defined (MDE_CPU_RISCV64) +/// +/// The RISC-V architecture context buffer used by SetJump() and LongJump(= ). +/// +typedef struct { + UINT64 RA; + UINT64 S0; + UINT64 S1; + UINT64 S2; + UINT64 S3; + UINT64 S4; + UINT64 S5; + UINT64 S6; + UINT64 S7; + UINT64 S8; + UINT64 S9; + UINT64 S10; + UINT64 S11; + UINT64 SP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +/** + RISC-V read CSR register. + +**/ +UINT32 +EFIAPI +RiscVReadCsr ( + UINT32 CsrIndex + ); + +/** + RISC-V write CSR register. + +**/ +VOID +EFIAPI +RiscVwriteCsr ( + UINT32 CsrIndex, + UINT32 Value + ); + +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvdInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvdDataCacheAsm ( + VOID + ); + +#endif // defined (MDE_CPU_RISCV64) =20 // // String Services diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index 800e771..1a29cc0 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -7,6 +7,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -603,6 +604,59 @@ typedef struct { UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; =20 +/// +/// RISC-V processor exception types. +/// +#define EXCEPT_RISCV_INST_MISALIGNED 0 +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 +#define EXCEPT_RISCV_ILLEGAL_INST 2 +#define EXCEPT_RISCV_BREAKPOINT 3 +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 + +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 +#define EXCEPT_RISCV_TIMER_INT 0x1 + +typedef struct { + UINT64 X0; + UINT64 X1; + UINT64 X2; + UINT64 X3; + UINT64 X4; + UINT64 X5; + UINT64 X6; + UINT64 X7; + UINT64 X8; + UINT64 X9; + UINT64 X10; + UINT64 X11; + UINT64 X12; + UINT64 X13; + UINT64 X14; + UINT64 X15; + UINT64 X16; + UINT64 X17; + UINT64 X18; + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 X29; + UINT64 X30; + UINT64 X31; +} EFI_SYSTEM_CONTEXT_RISCV64; =20 /// /// Universal EFI_SYSTEM_CONTEXT definition. @@ -614,6 +668,7 @@ typedef union { EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; } EFI_SYSTEM_CONTEXT; =20 // diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protoco= l/PxeBaseCode.h index b02d270..b7f9303 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -3,6 +3,8 @@ devices for network access and network booting. =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -153,6 +155,12 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A #elif defined (MDE_CPU_AARCH64) #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B +#elif defined (MDE_CPU_RISCV32) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0019 +#elif defined (MDE_CPU_RISCV64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B +#elif defined (MDE_CPU_RISCV128) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001D #endif =20 =20 diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV6= 4/ProcessorBind.h new file mode 100644 index 0000000..c1bf5cd --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,336 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choic= es +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +#if defined(__INTEL_COMPILER) +// +// Disable ICC's remark #869: "Parameter" was never referenced warning. +// This is legal ANSI C code so we disable the remark that is turned on wi= th -Wall +// +#pragma warning ( disable : 869 ) + +// +// Disable ICC's remark #1418: external function definition with no prior = declaration. +// This is legal ANSI C code so we disable the remark that is turned on wi= th /W4 +// +#pragma warning ( disable : 1418 ) + +// +// Disable ICC's remark #1419: external declaration in primary source file +// This is legal ANSI C code so we disable the remark that is turned on wi= th /W4 +// +#pragma warning ( disable : 1419 ) + +// +// Disable ICC's remark #593: "Variable" was set but never used. +// This is legal ANSI C code so we disable the remark that is turned on wi= th /W4 +// +#pragma warning ( disable : 593 ) + +#endif + + +#if defined(_MSC_EXTENSIONS) + +// +// Disable warning that make it impossible to compile at /W4 +// This only works for Microsoft* tools +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this war= ning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompil= ed header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For = precompiled header only. +// +#pragma warning ( disable : 4206 ) + +#if _MSC_VER =3D=3D 1800 + +// +// Disable these warnings for VS2013. +// + +// +// This warning is for potentially uninitialized local variable, and it ma= y cause false +// positive issues in VS2013 build +// +#pragma warning ( disable : 4701 ) + +// +// This warning is for potentially uninitialized local pointer variable, a= nd it may cause +// false positive issues in VS2013 build +// +#pragma warning ( disable : 4703 ) + +#endif + +#endif + + +#if defined(_MSC_EXTENSIONS) + // + // use Microsoft C complier dependent integer width types + // + + /// + /// 8-byte unsigned value + /// + typedef unsigned __int64 UINT64; + /// + /// 8-byte signed value + /// + typedef __int64 INT64; + /// + /// 4-byte unsigned value + /// + typedef unsigned __int32 UINT32; + /// + /// 4-byte signed value + /// + typedef __int32 INT32; + /// + /// 2-byte unsigned value + /// + typedef unsigned short UINT16; + /// + /// 2-byte Character. Unless otherwise specified all strings are stored= in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 s= tandards. + /// + typedef unsigned short CHAR16; + /// + /// 2-byte signed value + /// + typedef short INT16; + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRU= E. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character + /// + typedef char CHAR8; + /// + /// 1-byte signed value + /// + typedef signed char INT8; + + /// + /// Unsigned value of native width. (4 bytes on supported 32-bit proces= sor instructions, + /// 8 bytes on supported 64-bit processor instructions) + /// + typedef UINT64 UINTN; + /// + /// Signed value of native width. (4 bytes on supported 32-bit processo= r instructions, + /// 8 bytes on supported 64-bit processor instructions) + /// + typedef INT64 INTN; +#else + /// + /// 8-byte unsigned value + /// + typedef unsigned long long UINT64 __attribute__ ((aligned (8))); + /// + /// 8-byte signed value + /// + typedef long long INT64 __attribute__ ((aligned (8))); + /// + /// 4-byte unsigned value + /// + typedef unsigned int UINT32 __attribute__ ((aligned (4))); + /// + /// 4-byte signed value + /// + typedef int INT32 __attribute__ ((aligned (4))); + /// + /// 2-byte unsigned value + /// + typedef unsigned short UINT16 __attribute__ ((aligned (2))); + /// + /// 2-byte Character. Unless otherwise specified all strings are stored= in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 s= tandards. + /// + typedef unsigned short CHAR16 __attribute__ ((aligned (2))); + /// + /// 2-byte signed value + /// + typedef short INT16 __attribute__ ((aligned (2))); + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRU= E. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character + /// + typedef char CHAR8; + /// + /// 1-byte signed value + /// + typedef signed char INT8; + /// + /// Unsigned value of native width. (4 bytes on supported 32-bit proces= sor instructions, + /// 8 bytes on supported 64-bit processor instructions) + /// + typedef UINT64 UINTN __attribute__ ((aligned (8))); + /// + /// Signed value of native width. (4 bytes on supported 32-bit processo= r instructions, + /// 8 bytes on supported 64-bit processor instructions) + /// + typedef INT64 INTN __attribute__ ((aligned (8))); +#endif + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal x64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAP= I. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(_MSC_EXTENSIONS) + /// + /// Microsoft* compiler specific method for EFIAPI calling convention. + /// + #define EFIAPI __cdecl +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization le= vel + /// The GCC support assumes a GCC compiler that supports the EFI ABI. Th= e EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-= 64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used f= or + /// x64. Warning the assembly code in the MDE x64 does not follow the co= rrect + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EF= I ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a functi= on pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a funct= ion pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiB= aseType.h index a62f13d..89880be 100644 --- a/MdePkg/Include/Uefi/UefiBaseType.h +++ b/MdePkg/Include/Uefi/UefiBaseType.h @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -240,6 +241,12 @@ typedef union { /// #define EFI_IMAGE_MACHINE_AARCH64 0xAA64 =20 +/// +/// PE32+ Machine type for RISC-V 32/64/128 +/// +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 =20 #if defined (MDE_CPU_IA32) =20 @@ -268,6 +275,24 @@ typedef union { =20 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) =20 +#elif defined (MDE_CPU_RISCV128) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + (((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV128) || ((Machine) =3D=3D EFI_= IMAGE_MACHINE_EBC)) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#elif defined (MDE_CPU_RISCV64) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + (((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV64) || ((Machine) =3D=3D EFI_I= MAGE_MACHINE_EBC)) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#elif defined (MDE_CPU_RISCV32) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + (((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV32) || ((Machine) =3D=3D EFI_I= MAGE_MACHINE_EBC)) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + #elif defined (MDE_CPU_EBC) =20 /// diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 44a0a6a..b805175 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -6,6 +6,8 @@ by this include file. =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -2178,6 +2180,9 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV32 L"\\EFI\\BOOT\\BOOTRISCV32.E= FI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.E= FI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV128 L"\\EFI\\BOOT\\BOOTRISCV128= .EFI" =20 #if defined (MDE_CPU_IA32) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA= 32 @@ -2188,6 +2193,12 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM #elif defined (MDE_CPU_AARCH64) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AA= RCH64 +#elif defined (MDE_CPU_RISCV32) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RI= SCV32 +#elif defined (MDE_CPU_RISCV64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RI= SCV64 +#elif defined (MDE_CPU_RISCV128) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RI= SCV128 #else #error Unknown Processor Type #endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46781): https://edk2.groups.io/g/devel/message/46781 Mute This Topic: https://groups.io/mt/33137122/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46782+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46782+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595612; cv=none; d=zoho.com; s=zohoarc; b=ZRiY2bWf0z+OCyL5sS5+sg5Lp146QR7KYaygMMBlBs25iBpKMlMF/+iN5eryBdfsjdV3ahNlXpzXKldFbtvJuWAGKuRKrpEQPFTFPYtJdcX4vzFBOtRgylOuRhC8tQVQ1t17HCiHXEBQI70McLZeJzY/POlLErhbD0Cf5XW1zBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595612; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=7gd4AgoravQlRymWY2sUAi899kwXaJxFCusR+fpdzYE=; b=P6mDlZ7KJmEYxY/VPMa0xP/3bu4MDx26oWp4mbXaUBgqso2EKHAJqE4+VTdATnZ1ncNpVZPy1dDX5UQi9BHph9SMZQUFeOAb3zXJXFw8wEyOmHZCFnrTRQGmnyndZN/POIxarWIRg4DET5vGq2YV4WLlFuHlx8jrqgFhgVT0LHk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46782+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595612354591.2904636134854; Wed, 4 Sep 2019 04:13:32 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:31 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBs0k020698 for ; Wed, 4 Sep 2019 11:13:30 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7uy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:30 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 13B7290 for ; Wed, 4 Sep 2019 11:13:30 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 29EA639; Wed, 4 Sep 2019 11:13:28 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 05/22]: MdeModulePkg/CapsuleRuntimeDxe: Add RISC-V arch. Date: Wed, 4 Sep 2019 18:43:00 +0800 Message-Id: <1567593797-26216-6-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595612; bh=e7YeYSLCiSDzN1HTYCdutYllVSoft7TNGG/YaF/BIkY=; h=Cc:Date:From:Reply-To:Subject:To; b=HyQU5ppXoz3WnME7rI/lc7AmNyT+St1Z5K8oJcIaak1YgLEuAbStGtO1jmZQ7fHpmOe 1jFJ/94UeU5L2IDZuwphBT3zAm3SsD5lstphnMpln/Ihv/OZEAi3BDxTUbHAmTVt2yy5i ndS0BE1hSbnWLvyUBBLp6pOyLGz0cbGBKhE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISC-V in INF for building CapsuleRuntimeDxe RISC-V image. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++--= -- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf= b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf index 9da4507..84f3688 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -5,6 +5,7 @@ # the capsule runtime services are ready. # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -21,20 +22,20 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] CapsuleService.c CapsuleService.h =20 -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64] +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64] SaveLongModeContext.c =20 -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64] +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64] CapsuleCache.c =20 -[Sources.Ia32, Sources.X64, Sources.EBC] +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64] CapsuleReset.c =20 [Sources.ARM, Sources.AARCH64] --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46782): https://edk2.groups.io/g/devel/message/46782 Mute This Topic: https://groups.io/mt/33137123/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46783+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46783+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595614; cv=none; d=zoho.com; s=zohoarc; b=OfEKpV4hmtkdOw7GyzYGVn9WGCrqAxVWBA4Nzsd73lKRAZs4NIaLHxdiMkuOxI8EKYK2EBzBa+ML/tU5uo6t72PzPq8gqthC5TsC17dIGQWuyt1kpnuCKdbQee2GOZmXwcFWRTiXfVJUBVj6EY3T9ae+fEW8WEFrfdfc591vZBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595614; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=YoV7pNSMqn/x2qSPshutaKKkkZ8iy0njkHjVFs8c4aw=; b=avT2OPvkubztMxewBsJKJpTpAAZ7s88fV5VRv3Ri1slQhTNaUG7FYX3bSrT15wu0op7LEKN/b/yZ6PlM0MYAA3iGLTowzBVOYdq7nGu4Dn6Ys113PPiUu6XGo8SW8muosfbD6Ed710u/vAQAlL62SL3++aFz07stiMS4tt5eY/c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46783+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595614297858.449471569295; Wed, 4 Sep 2019 04:13:34 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:33 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBiBr003908 for ; Wed, 4 Sep 2019 11:13:32 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usvqnwy7u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:32 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 67295B2 for ; Wed, 4 Sep 2019 11:13:31 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 7E0E939; Wed, 4 Sep 2019 11:13:30 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 6/22]: MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Date: Wed, 4 Sep 2019 18:43:01 +0800 Message-Id: <1567593797-26216-7-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595614; bh=72FZFKpUitwliQDOfWynnZslPqo6C692l5VEazItsrA=; h=Cc:Date:From:Reply-To:Subject:To; b=rwMZZb3A/xJrg8N9n+jZTXX65SlcT0sG3C43ODB/9s5xGf3ERgFqhkxm8IISyBEvgFO GT9nm5CmcaCUjOIgRzfqRwOO0GyR//c1bScn4TQVdZa48LP5JiOSLdcQsjdCaRJivMvAO 4nXmiZNgRSazAWs0vmMjpHVAG/2GaKEi9Zk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../BaseCacheMaintenanceLib.inf | 4 + .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 242 +++++++++++++++++= ++++ 2 files changed, 246 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feec..d9bfa04 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ [Sources.AARCH64] ArmCache.c =20 +[Sources.RISCV64] + RiscVCache.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000..2d376a4 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,242 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include +#include +#include + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvdInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + //ASSERT(FALSE); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + //ASSERT(FALSE); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + //ASSERT(FALSE); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + //ASSERT(FALSE); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + //ASSERT(FALSE); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvdDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); + //ASSERT(FALSE); + return Address; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46783): https://edk2.groups.io/g/devel/message/46783 Mute This Topic: https://groups.io/mt/33137127/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46784+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46784+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595615; cv=none; d=zoho.com; s=zohoarc; b=YCiA3jmB759ytMdH5s+qHTN4bnEUKD71vO//PpuftECIAImkhc9Pe64uOcnGTjh/UyHLCM4H8Map7+Nj25JOwjmW3MTpqW5RJHJKw1w2tOrYyQtaNcbMcPCBCSU8gn0Se4TwwpqBc+/RTICNF46yeqN6UUpFqv4OvqcmOKnqHnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595615; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=JSluAs+Y0MtAnL97ELP4kef+/MhvQeeLHZh/lQ+joLo=; b=enDQMLq7EsPBl7FD8BMr2mOUORwC2/ByqO+KmGwDa5gtmzWAQMiHYkGoCMXIAWwS+64Iw6wIwV3pYNKvRp7yJ/5RWLr73CGMREDHnt91wf80eQSkFHQRyHFEZKc30S7L2oG+w49aCsJgxA/QBgsFAc+7UCYNsbK2qDkOE37VR3g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46784+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595615345377.8933692384545; Wed, 4 Sep 2019 04:13:35 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:34 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBi15003899 for ; Wed, 4 Sep 2019 11:13:33 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 2usvqnwy81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:33 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id BA48BAF for ; Wed, 4 Sep 2019 11:13:32 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D171639; Wed, 4 Sep 2019 11:13:31 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 07/22]: MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions. Date: Wed, 4 Sep 2019 18:43:02 +0800 Message-Id: <1567593797-26216-8-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595615; bh=/m0b8wf2zRNmnPLjjQ3J1bT/KqbAiP8OsUwaV+RyRL4=; h=Cc:Date:From:Reply-To:Subject:To; b=Kjn7RJN4QxS9jjzu2nZbgLVySjcKByFR6BfS3mVH8kHJuskQJfqy375n7EdchHyD7k0 Y2zxGMh1pBsaGhhHqCxh6M/iUIliIDQvfgV90JwzktKGBGQnJfi7fkcWNYbUPjIBDsD2G jryS9uiEn4DmUkHvEYwgWAt37kOM5qckW3o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V MMIO library instance. RISC-V only supports memory map I/O. However= the first implementation of RISC-V EDK2 port uses PC/AT as the RISC-V platform spec. We have to keep= the I/O functions as the temporary solution. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 8 +- MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c | 697 +++++++++++++++++= ++++ 2 files changed, 703 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 457cce9..fbb568e 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -2,13 +2,14 @@ # Instance of I/O Library using compiler intrinsics. # # I/O Library that uses compiler intrinsics to perform IN and OUT instruc= tions -# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO = requests. +# for IA-32, x64 and RISC-V. On IPF, I/O port requests are translated in= to MMIO requests. # MMIO requests are forwarded directly to memory. For EBC, I/O port requ= ests # ASSERT(). # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP.= All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -55,6 +56,9 @@ [Sources.AARCH64] IoLibArm.c =20 +[Sources.RISCV64] + IoLibRiscV.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c b/MdePkg/Librar= y/BaseIoLibIntrinsic/IoLibRiscV.c new file mode 100644 index 0000000..6173d25 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibRiscV.c @@ -0,0 +1,697 @@ +/** @file + Common I/O Library routines for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseIoLibIntrinsicInternal.h" + +/** + Reads an 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +MmioRead8 ( + IN UINTN Address + ) +{ + return *(volatile UINT8*)Address; +} + +/** + Writes an 8-bit MMIO register. + + Writes the 8-bit MMIO register specified by Address with the value speci= fied + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +MmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + *(volatile UINT8 *)Address =3D Value; + return Value; +} + +/** + Reads a 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address. The 16-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +MmioRead16 ( + IN UINTN Address + ) +{ + return *(volatile UINT16 *)Address; +} + +/** + Writes a 16-bit MMIO register. + + Writes the 16-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +MmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + *(volatile UINT16 *)Address =3D Value; + return Value; +} + +/** + Reads a 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address. The 32-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +MmioRead32 ( + IN UINTN Address + ) +{ + return *(volatile UINT32 *)Address; +} + +/** + Writes a 32-bit MMIO register. + + Writes the 32-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The valu return *(volatile UINT8*)Address; + to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +MmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + *(volatile UINT32 *)Address =3D Value; + return Value; +} + +/** + Reads a 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address. The 64-bit read val= ue is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +MmioRead64 ( + IN UINTN Address + ) +{ + return *(volatile UINT64 *)Address; +} + +/** + Writes a 64-bit MMIO register. + + Writes the 64-bit MMIO register specified by Address with the value spec= ified + by Value and returns Value. This function must guarantee that all MMIO r= ead + and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + *(volatile UINT64 *)Address =3D Value; + return Value; +} + +/** + Reads an 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port. The 8-bit read value is retu= rned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +IoRead8 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port use PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions for temporary solution. + // + return *(volatile UINT8*)Port; +} + +/** + Writes an 8-bit I/O port. + + Writes the 8-bit I/O port specified by Port with the value specified by = Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ + +UINT8 +EFIAPI +IoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT8 *)Port =3D Value; + return Value; +} + +/** + Reads a 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port. The 16-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +IoRead16 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT16*)Port; +} + +/** + Writes a 16-bit I/O port. + + Writes the 16-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +IoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT16*)Port =3D Value; + return Value; +} + +/** + Reads a 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port. The 32-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +IoRead32 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT32*)Port; +} + +/** + Writes a 32-bit I/O port. + + Writes the 32-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +IoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT32*)Port =3D Value; + return Value; +} + +/** + Reads a 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port. The 64-bit read value is re= turned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +IoRead64 ( + IN UINTN Port + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + return *(volatile UINT64*)Port; +} + +/** + Writes a 64-bit I/O port. + + Writes the 64-bit I/O port specified by Port with the value specified by= Value + and returns Value. This function must guarantee that all I/O read and wr= ite + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written to the I/O port. + +**/ +UINT64 +EFIAPI +IoWrite64 ( + IN UINTN Port, + IN UINT64 Value + ) +{ + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + *(volatile UINT64*)Port =3D Value; + return 0; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT8 *Buffer8; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer8 =3D (UINT8 *)Buffer; + while (Count-- > 0) { + *Buffer8++ =3D *(volatile UINT8 *)Port++; + } +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT8 *Buffer8; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer8 =3D (UINT8 *)Buffer; + while (Count-- > 0) { + *(volatile UINT8 *)Port++ =3D *Buffer8++; + } +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT16 *Buffer16; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer16 =3D (UINT16 *)Buffer; + while (Count-- > 0) { + *Buffer16++ =3D *(volatile UINT16 *)Port++; + } +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT16 *Buffer16; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer16 =3D (UINT16 *)Buffer; + while (Count-- > 0) { + *(volatile UINT16 *)Port++ =3D *Buffer16++; + } +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT32 *Buffer32; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer32 =3D (UINT32 *)Buffer; + while (Count-- > 0) { + *Buffer32++ =3D *(volatile UINT32 *)Port++; + } +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT32 *Buffer32; + + // + // RISC-V only supports memory map I/O. However the + // first implementation of RISC-V EDK2 port uses PC/AT + // as the RISC-V platform spec. We have to keep I/O + // functions as the temporary solution. + // + Buffer32 =3D (UINT32 *)Buffer; + while (Count-- > 0) { + *(volatile UINT32 *)Port++ =3D *Buffer32++; + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46784): https://edk2.groups.io/g/devel/message/46784 Mute This Topic: https://groups.io/mt/33137129/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46785+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46785+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595616; cv=none; d=zoho.com; s=zohoarc; b=GV82uDIvLWe3Ka0X2HiB4lFvX7cEqTYo+XIaVpXELrYaickHDlUy4fImUXoM3+n2fxWvNbvUwl7QhzuKTUY8OGnzp7TC1r/Z8KqSIcTvVVOGerhmBbmYf7Qe4x/dFd3I2CHwPSoKTEWq+htmUfrjIl3As+43O8SCtbEgSCuu2DE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595616; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=vMqHfUr/Sl0Hd4QkM/YL1UaY9LUJa8qXy0AdEj8pC7g=; b=ZRqjxe9GMrkSZ4qrVsltX7PIP3lO2CgCvuO5iRQsAqPvhu4eqokK8gjicYjuAatWydoY2IqGxtIpRcLEXW6vWSkTfV0VTkRlHw0LyN1Zyc5zDiSGaqaersVRerhGSJzaAr6Xh5tMn2ZTMSNywVo3LldXrVlHzDbviZKp5Tfwh8E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46785+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595616285967.183784811684; Wed, 4 Sep 2019 04:13:36 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:35 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBgHQ017958 for ; Wed, 4 Sep 2019 11:13:34 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usyw7vrf7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:34 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 19FEBB1 for ; Wed, 4 Sep 2019 11:13:34 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 313BA39; Wed, 4 Sep 2019 11:13:32 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 08/22]: MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Date: Wed, 4 Sep 2019 18:43:03 +0800 Message-Id: <1567593797-26216-9-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595616; bh=9gAnUUTZ/800BL36GO/tHujKNZCwpxz68Q65x7U+itA=; h=Cc:Date:From:Reply-To:Subject:To; b=h/OrqNUZRRrFCxzsRLReAqyMEGxh1JYOrmXwFIJNEkqVeRi7uGgyIZR7ckUzK95Zfxt +bTj9uUNdKnQ16xTb0qksEfYu/Gg5hdlU0cAkASezUgjEqChAvZn3FWa2DLVQqQ6PHJts lg7cbDoQdlfuuyJ4PDPMbZe1eEcWIDV89I4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support RISC-V image relocation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 4 +- .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 + .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 149 +++++++++++++++++= ++++ 5 files changed, 160 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/Bas= ePeCoffLib/BasePeCoff.c index 07bb62f..97e0ff4 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c @@ -1,6 +1,6 @@ /** @file Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but - only supports relocating IA32, x64, IPF, and EBC images. + only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images. =20 Caution: This file requires additional review when modified. This library will have external input - PE/COFF image. @@ -17,6 +17,7 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. = All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.inf index 395c140..e5c8e66 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -3,6 +3,7 @@ # The IPF version library supports loading IPF and EBC PE/COFF image. # The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. # The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. +# The RISC-V version library support loading RISC-V images. # # Caution: This module requires additional review when modified. # This library will have external input - PE/COFF image. @@ -11,6 +12,7 @@ # # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@ [Sources.ARM] Arm/PeCoffLoaderEx.c =20 +[Sources.RISCV64] + RiscV/PeCoffLoaderEx.c + =20 [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.uni index b0ea702..edc48cd 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -4,7 +4,8 @@ // The IPF version library supports loading IPF and EBC PE/COFF image. // The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. // The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. -// +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COF= F images. +//=20 // Caution: This module requires additional review when modified. // This library will have external input - PE/COFF image. // This external input must be validated carefully to avoid security issue= like @@ -12,6 +13,7 @@ // // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg= /Library/BasePeCoffLib/BasePeCoffLibInternals.h index b74277f..9c33703 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h @@ -2,6 +2,7 @@ Declaration of internal functions in PE/COFF Lib. =20 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/L= ibrary/BasePeCoffLib/RiscV/PeCoffLoaderEx.c new file mode 100644 index 0000000..a99550f --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c @@ -0,0 +1,149 @@ +/** @file + PE/Coff loader for RISC-V PE image + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ +#include "BasePeCoffLibInternals.h" +#include + +// +// RISC-V definition. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + *(UINT64 *)(*FixupData) =3D (UINT64)(UINTN)Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) |\ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) |\ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25))); + } + break; + + default: + return RETURN_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} + +/** + Returns TRUE if the machine type of PE/COFF image is supported. Supported + does not mean the image can be executed it means the PE/COFF loader supp= orts + loading and relocating of the image type. It's up to the caller to suppo= rt + the entry point. + + @param Machine Machine type from the PE Header. + + @return TRUE if this PE/COFF loader can load the image + +**/ +BOOLEAN +PeCoffLoaderImageFormatSupported ( + IN UINT16 Machine + ) +{ + if ((Machine =3D=3D IMAGE_FILE_MACHINE_RISCV32) || (Machine =3D=3D IMAG= E_FILE_MACHINE_RISCV64)) { + return TRUE; + } + + return FALSE; +} + +/** + Performs an Itanium-based specific re-relocation fixup and is a no-op on= other + instruction sets. This is used to re-relocated the image into the EFI vi= rtual + space for runtime calls. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeHotRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + return RETURN_UNSUPPORTED; +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46785): https://edk2.groups.io/g/devel/message/46785 Mute This Topic: https://groups.io/mt/33137131/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46786+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46786+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595617; cv=none; d=zoho.com; s=zohoarc; b=RLS3etSBleGWAQlLRZtGHwUWH/wcf2eHaHWjLn0DtFIluWvmY5ERtNRqej7+z3PX5cAJCKTIkRtTr9O2P26tT6rKGPkreIkzuXaHFN917gspMS3gQzo4Ek3y4vuflaVRG1WEBN2yocolX/zLdP4GIjdUoL1e5etOMMGuxkVvq3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595617; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SLzvi6nF3ntUvc3W8kdjAmt+WF6r9VCQY2bdrrijHmk=; b=iEazgRzDFOAVMIRV0tDPR2JczbTvU8JCmxgNIOOdgW54mi8Sg7EJssggUD6bKQ32pJft1CP4a2iNAWiN2krtUu+c/GSlysWtpwxBPZlhQ7pxIKZJj+Q/f01L0CqQvOmpcp64T5d+yqUjHKZZbaQkIAQrKFfMiyMk2FrYHjun5OQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46786+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595617625824.6791193373966; Wed, 4 Sep 2019 04:13:37 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:36 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBfvk016728 for ; Wed, 4 Sep 2019 11:13:36 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usra9rck8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:36 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 6DE57B1 for ; Wed, 4 Sep 2019 11:13:35 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 848B539; Wed, 4 Sep 2019 11:13:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 09/22]: MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Date: Wed, 4 Sep 2019 18:43:04 +0800 Message-Id: <1567593797-26216-10-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595617; bh=gfFYvHa+KR8HW3jxEoGwx/K+C3uQGcnEAFnZgBLsgLU=; h=Cc:Date:From:Reply-To:Subject:To; b=axlAmU3P+TBdgcOXEeKw0wY1Qixjxsr8/NeStwgwuQYHsQJpQ4t80YYMHKfhv9eTZxD nRMLY0EE8FJzNq/Ywg3wmqyyPT1WZdJHHYYdYwEjeuUR1HoUGypYFDWlq/W1Sryu4yd0S inJKq9tEq4LWP2N634X43qCPLED10vvT2nA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement RISC-V CPU related functions in BaseCpuLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 4 ++++ MdePkg/Library/BaseCpuLib/RiscV/Cpu.s | 25 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.s diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index a7cb381..20ee774 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT AArch64/CpuSleep.asm | MSFT =20 +[Sources.RISCV64] + RiscV/Cpu.s + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.s b/MdePkg/Library/BaseCpu= Lib/RiscV/Cpu.s new file mode 100644 index 0000000..9a1bf0f --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.s @@ -0,0 +1,25 @@ +//------------------------------------------------------------------------= ------ +// +// CpuSleep for RISC-V +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +.data +.align 3 +.section .text + +.global ASM_PFX(_CpuSleep) + +ASM_PFX(_CpuSleep): + wfi + ret + + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46786): https://edk2.groups.io/g/devel/message/46786 Mute This Topic: https://groups.io/mt/33137132/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46787+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46787+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595618; cv=none; d=zoho.com; s=zohoarc; b=O5LgV3TV7QvmJffgf/5EOHc+e1Ds3ACh0tEP6IPZFFn6agjx3ynEiZtM5DhZEXhLhhpWHcur8JUsj7DWSx8unKlr7YqJ5DM1G65LOWPXuTD2JtdVHnJgJjlYWZTFMDVUDmDbcShfSwKu1vfhYLHQrX4bKUFvVThlX074fLCE8xk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595618; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=n4JSaRWmlVIn/5Z6xipOAQ3vuN8uyPMv844dkfcB27k=; b=Uf9gK/aBH6UyPJhWdoM5+jcCdX4Vi4OhN1VmT73ql3BHC8oXZ99j6i+u5esm1r4x7eQ5F9mdmuY8bV7V26NLZtcsDbjgV9VdyIKodTRCKshKcrMuo1b9ppCAUCMdOHQg5OCr5YU+lvRabtJQyXUm3EqQJX7IXJ57lzFU3RMLUhc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46787+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595618843645.142275295419; Wed, 4 Sep 2019 04:13:38 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:38 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBjJX016912 for ; Wed, 4 Sep 2019 11:13:37 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usra9rckg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:37 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id C39C1B0 for ; Wed, 4 Sep 2019 11:13:36 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D8ABB39; Wed, 4 Sep 2019 11:13:35 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 10/22]: MdePkg/BaseSynchronizationLib: RISC-V cache related code. Date: Wed, 4 Sep 2019 18:43:05 +0800 Message-Id: <1567593797-26216-11-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595618; bh=Wk3OrKpbDG6quhxJA6u13WzvsaZdpGyEKKIMWsHv2JA=; h=Cc:Date:From:Reply-To:Subject:To; b=P+isi6nJaYH0cOJngY4ZvXHeZrxG4y7E5i15QR6RNrkMTrm+082BT2EDTYoaJBSzkV3 b4a9lUJ29eRUkQp55D+xMM5S9tqu7LVkQ2YIul5y3LZ9H/6tWue82gWXMWJN0qT33gSGv OEsZfuGq8ZK4ZRB59H0vRLN4JF5U471GY6g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support RISC-V cache related functions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../BaseSynchronizationLib.inf | 6 + .../RiscV64/Synchronization.c | 189 +++++++++++++++++= ++++ .../RiscV64/SynchronizationAsm.s | 84 +++++++++ 3 files changed, 279 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zation.c create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.s diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19..d49001b 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,11 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT =20 +[Sources.RISCV64] + Synchronization.c + RiscV64/Synchronization.c | GCC + RiscV64/SynchronizationAsm.s + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.= c b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c new file mode 100644 index 0000000..e85e2f5 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c @@ -0,0 +1,189 @@ +/** @file + Implementation of synchronization functions on RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include + +UINT32 +SyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue +); + +UINT64 +SyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue +); + +UINT32 +SyncSyncIncrement32 ( + IN volatile UINT32 *Value + ); + +UINT32 +SyncSyncDecrement32 ( + IN volatile UINT32 *Value + ); + +/** + Performs an atomic compare exchange operation on a 16-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 16-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 16-bit value for the + compare exchange operation. + @param CompareValue 16-bit value used in compare operation. + @param ExchangeValue 16-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT16 +EFIAPI +InternalSyncCompareExchange16 ( + IN volatile UINT16 *Value, + IN UINT16 CompareValue, + IN UINT16 ExchangeValue + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO operation\n",= __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Performs an atomic compare exchange operation on a 32-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 32-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 32-bit value for the + compare exchange operation. + @param CompareValue 32-bit value used in compare operation. + @param ExchangeValue 32-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT32 +EFIAPI +InternalSyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue + ) +{ + + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange32(Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic compare exchange operation on a 64-bit unsigned integ= er. + + Performs an atomic compare exchange operation on the 64-bit unsigned int= eger specified + by Value. If Value is equal to CompareValue, then Value is set to Excha= ngeValue and + CompareValue is returned. If Value is not equal to CompareValue, then V= alue is returned. + The compare exchange operation must be performed using MP safe mechanism= s. + + @param Value A pointer to the 64-bit value for the compare exch= ange + operation. + @param CompareValue 64-bit value used in compare operation. + @param ExchangeValue 64-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT64 +EFIAPI +InternalSyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ) +{ + if (((UINTN)Value % sizeof (UINT64)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange64 (Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic increment of an 32-bit unsigned integer. + + Performs an atomic increment of the 32-bit unsigned integer specified by + Value and returns the incremented value. The increment operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to increment. + + @return The incremented value. + +**/ +UINT32 +EFIAPI +InternalSyncIncrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncIncrement32 (Value); +} + +/** + Performs an atomic decrement of an 32-bit unsigned integer. + + Performs an atomic decrement of the 32-bit unsigned integer specified by + Value and returns the decrement value. The decrement operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to decrement. + + @return The decrement value. + +**/ +UINT32 +EFIAPI +InternalSyncDecrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) !=3D 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural addres= s.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncDecrement32 (Value); +} diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationA= sm.s b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.s new file mode 100644 index 0000000..3e838b0 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.s @@ -0,0 +1,84 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V synchronization functions. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(SyncCompareExchange32) +.global ASM_PFX(SyncCompareExchange64) +.global ASM_PFX(SyncSyncIncrement32) +.global ASM_PFX(SyncSyncDecrement32) + +// +// ompare and xchange a 32-bit value. +// +// @param a0 : Pointer to 32-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange32): + lr.w a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.w a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit: + mv a0, a3 + ret + +.global ASM_PFX(SyncCompareExchange64) + +// +// Compare and xchange a 64-bit value. +// +// @param a0 : Pointer to 64-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange64): + lr.d a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.d a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit2: + mv a0, a3 + ret + +// +// Performs an atomic increment of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncIncrement32): + li a1, 1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret + +// +// Performs an atomic decrement of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncDecrement32): + li a1, -1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46787): https://edk2.groups.io/g/devel/message/46787 Mute This Topic: https://groups.io/mt/33137133/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46788+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46788+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595622; cv=none; d=zoho.com; s=zohoarc; b=g+Ph30gbGjbOMXV6qb/kiwkQntGsjerxnXi+7q7GkBey+mD5QsXhgl6i9Is0OSbvno10Ye6sLgZWK6Z9AX4WJ5+9rTJinNxamcvZkoHqqOyDIGh8f3zhrarRcX2YIlVD+/STuF4/MeHtjMGkqdbGUH8l87o6o4JhXVO9EBFtVCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595622; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=4hAhhPPyY1GTz31xcNKvmx37aVJFaZrBb689RvLtmrM=; b=Xoe04NvOeVKRdCz5AhTrK7gh0zOdrCGDj171+HcSdhNT6jbdAgsUvs0GTrv3Gs1OelclN9bZjiUJGlY6QnXRH5qjfuSlG2NFqxxwSh1+aKszREd87TtaTyyyfvBLCb7YB/m0JANpXmv9CiD5wqWHiBGv/N2rdGpcAhiQe8knoKI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46788+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595622148201.99628068096536; Wed, 4 Sep 2019 04:13:42 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:41 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBg9v017961 for ; Wed, 4 Sep 2019 11:13:40 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 2usyw7vrg5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:39 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 59244BA for ; Wed, 4 Sep 2019 11:13:38 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 3A97539; Wed, 4 Sep 2019 11:13:37 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 11/22]: BaseTools: BaseTools changes for RISC-V platform. Date: Wed, 4 Sep 2019 18:43:06 +0800 Message-Id: <1567593797-26216-12-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595621; bh=e4iGly+K+vVt5zVLR6WvK1SjY9R0/jFjiYaOHilfJLQ=; h=Cc:Date:From:Reply-To:Subject:To; b=dJpoOD0yLY7XefFVPwTkiM32UNxUWI2TcO2N/wLAcfMPYeWgmExY2mmoDhIYGbwgZA1 WwS8bj4ZA6e3e+QdRv5KY+HtpP/f3J2kkLyasWiSIlg/vpOA1RXutJ2/5cccoNlqTD9mt Tq6shOzu7+TONIPiq4AL6NYe6gAMTIvkG4E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BaseTools changes for building EDK2 RISC-V platform. The changes made to build_rule.template is to avoid build errors cause by G= CC711RISCV tool chain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- BaseTools/Conf/build_rule.template | 23 +- BaseTools/Conf/tools_def.template | 108 +- BaseTools/Source/C/Common/BasePeCoff.c | 19 +- BaseTools/Source/C/Common/PeCoffLoaderEx.c | 96 ++ BaseTools/Source/C/GenFv/GenFvInternalLib.c | 281 ++++- BaseTools/Source/C/GenFw/Elf32Convert.c | 6 +- BaseTools/Source/C/GenFw/Elf64Convert.c | 273 ++++- BaseTools/Source/C/GenFw/elf_common.h | 63 ++ .../Source/C/Include/IndustryStandard/PeImage.h | 10 + BaseTools/Source/Python/Common/DataType.py | 1075 ++++++++++------= ---- 10 files changed, 1393 insertions(+), 561 deletions(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index db06d3a..8e7f6e0 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -145,14 +145,6 @@ "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src} =20 -[C-Header-File] - - *.h, *.H - - - - - [Assembly-Code-File.COMMON.COMMON] ?.asm, ?.Asm, ?.ASM @@ -321,6 +313,21 @@ "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst} =20 =20 +[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32] + + *.lib + + + $(MAKE_FILE) + + + $(DEBUG_DIR)(+)$(MODULE_NAME).dll + + + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @= $(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS) + "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst} + + [Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION] *.lib diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 8f0e6cb..36a301a 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -3,7 +3,7 @@ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -114,6 +114,12 @@ DEFINE GCC49_X64_PREFIX =3D ENV(GCC49_BIN) DEFINE GCC5_IA32_PREFIX =3D ENV(GCC5_BIN) DEFINE GCC5_X64_PREFIX =3D ENV(GCC5_BIN) DEFINE GCC_HOST_PREFIX =3D ENV(GCC_HOST_BIN) +# +# RISC-V GCC toolchain +# This is the default directory used when install official riscv-tools. +# +DEFINE GCCRISCV_RISCV32_PREFIX =3D ENV(GCC_RISCV32_BIN) +DEFINE GCCRISCV_RISCV64_PREFIX =3D ENV(GCC_RISCV64_BIN) =20 DEFINE UNIX_IASL_BIN =3D ENV(IASL_PREFIX)iasl DEFINE WIN_IASL_BIN =3D ENV(IASL_PREFIX)iasl.exe @@ -236,6 +242,15 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Required to build platforms or ACPI tables: # Intel(r) ACPI Compiler from # https://acpica.org/downloads +# GCCRISCV - Linux - Requires: +# RISC-V official release of RISC-V GNU toolch= ain, +# https://github.com/riscv/riscv-gnu-toolcha= in @64879b24 +# The commit ID 64879b24 is the one can buil= d RISC-V platform and boo to EFI shell. +# Follow the instructions mentioned in READM= E.md to build RISC-V tool change. +# Set below environment variables to the RISC-= V tool chain binaries before building RISC-V EDK2 port. +# - GCC_RISCV32_BIN +# - GCC_RISCV64_BIN +# # CLANG35 -Linux,Windows- Requires: # Clang v3.5 or later, and GNU binutils target= ing aarch64-linux-gnu or arm-linux-gnueabi # Optional: @@ -1806,6 +1821,26 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D DEF(GCC49_A= RM_ASLDLINK_FLAGS) DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D DEF(GCC49_AARCH64_ASLDLINK_FLAGS) DEFINE GCC5_ASLCC_FLAGS =3D DEF(GCC49_ASLCC_FLAGS) -fno-lto =20 +DEFINE GCC_RISCV_ALL_CC_FLAGS =3D -g -fshort-wchar -fno= -strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata= -sections -c -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=3D$(BASE_NA= ME)Strings +DEFINE GCC_RISCV_ALL_DLINK_COMMON =3D -nostdlib -n -q --gc-= sections -z common-page-size=3D0x40 +DEFINE GCC_RISCV_ALL_DLINK_FLAGS =3D DEF(GCC_RISCV_ALL_DLI= NK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST= _DIR_DEBUG)/$(BASE_NAME).map +DEFINE GCC_RISCV_ALL_DLINK2_FLAGS =3D --defsym=3DPECOFF_HEA= DER_SIZE=3D0x220 --script=3D$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds +DEFINE GCC_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -imac= ros $(DEST_DIR_DEBUG)/AutoGen.h +DEFINE GCC_RISCV_RISCV32_DLINK2_FLAGS =3D --defsym=3DPECOFF_HEA= DER_SIZE=3D0x220 DEF(GCC_DLINK2_FLAGS_COMMON) + +DEFINE GCCRISCV_RISCV32_ARCH =3D rv32imafdc +DEFINE GCCRISCV_RISCV64_ARCH =3D rv64imafdc +DEFINE GCCRISCV_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-compa= re -Wno-pointer-compare +DEFINE GCCRISCV_RISCV32_CC_FLAGS =3D DEF(GCC_RISCV_ALL_CC_FL= AGS) DEF(GCCRISCV_CC_FLAGS_WARNING_DISABLE) -march=3DDEF(GCCRISCV_RISCV32_A= RCH) -malign-double -fno-stack-protector -D EFI32 -fno-asynchronous-unwind-= tables -Wno-address -Wno-unused-but-set-variable -fpack-struct=3D8 +DEFINE GCCRISCV_RISCV64_CC_FLAGS =3D DEF(GCC_RISCV_ALL_CC_FL= AGS) DEF(GCCRISCV_CC_FLAGS_WARNING_DISABLE) -march=3DDEF(GCCRISCV_RISCV64_A= RCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fn= o-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=3D8= -mcmodel=3Dmedany -mabi=3Dlp64 +DEFINE GCCRISCV_RISCV32_RISCV64_DLINK_COMMON =3D -nostdlib -n -q --gc-se= ctions -z common-page-size=3D0x40 +DEFINE GCCRISCV_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC_RISCV_ALL_DLINK= _COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable +DEFINE GCCRISCV_RISCV32_RISCV64_DLINK_FLAGS =3D DEF(GCC_RISCV_ALL_DLINK= _COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_D= IR_DEBUG)/$(BASE_NAME).map +DEFINE GCCRISCV_RISCV32_DLINK2_FLAGS =3D DEF(GCC_RISCV_RISCV32_D= LINK2_FLAGS) +DEFINE GCCRISCV_RISCV64_DLINK_FLAGS =3D DEF(GCC_RISCV_ALL_DLINK= _FLAGS) -melf64lriscv --oformat=3Delf64-littleriscv --no-relax +DEFINE GCCRISCV_RISCV64_DLINK2_FLAGS =3D DEF(GCC_RISCV_ALL_DLINK= 2_FLAGS) +DEFINE GCCRISCV_ASM_FLAGS =3D DEF(GCC_RISCV_ALL_ASM_F= LAGS) -march=3DDEF(GCCRISCV_RISCV64_ARCH) -mcmodel=3Dmedany -mabi=3Dlp64 + ##########################################################################= ########## # # GCC 4.8 - This configuration is used to compile under Linux to produce @@ -2247,6 +2282,77 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-pa= ge-size=3D0x20 NOOPT_GCC5_AARCH64_DLINK_FLAGS =3D DEF(GCC5_AARCH64_DLINK_FLAGS) -O0 NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-page-size=3D0x20 -O0 =20 +##########################################################################= ######### +##########################################################################= ########## +# +# GCC RISC-V This configuration is used to compile under Linux to produce +# PE/COFF binaries using GCC RISC-V tool chain +# https://github.com/riscv/riscv-gnu-toolchain @64879b24 +# The commit ID 64879b24 is the one can build RISC-V platform and boo to E= FI shell. +# +##########################################################################= ########## + +*_GCCRISCV_*_*_FAMILY =3D GCC + +*_GCCRISCV_*_MAKE_PATH =3D DEF(GCC49_IA32_PREFIX)make +*_GCCRISCV_*_PP_FLAGS =3D DEF(GCC_PP_FLAGS) +*_GCCRISCV_*_ASLPP_FLAGS =3D DEF(GCC_ASLPP_FLAGS) +*_GCCRISCV_*_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS) +*_GCCRISCV_*_VFRPP_FLAGS =3D DEF(GCC_VFRPP_FLAGS) +*_GCCRISCV_*_APP_FLAGS =3D +*_GCCRISCV_*_ASL_FLAGS =3D DEF(IASL_FLAGS) +*_GCCRISCV_*_ASL_OUTFLAGS =3D DEF(IASL_OUTFLAGS) + +################## +# GCCRISCV RISCV32 definitions +################## + +*_GCCRISCV_RISCV32_OBJCOPY_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-objcopy +*_GCCRISCV_RISCV32_SLINK_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc-ar +*_GCCRISCV_RISCV32_DLINK_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-ld +*_GCCRISCV_RISCV32_ASLDLINK_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-ld +*_GCCRISCV_RISCV32_ASM_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV32_PP_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV32_VFRPP_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV32_ASLCC_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV32_ASLPP_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV32_RC_PATH =3D DEF(GCCRISCV_RISCV32_PREFIX)ri= scv64-unknown-elf-objcopy + +*_GCCRISCV_RISCV32_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS) -m32 +*_GCCRISCV_RISCV32_ASLDLINK_FLAGS =3D DEF(GCCRISCV_RISCV32_RISCV64_A= SLDLINK_FLAGS) -m elf_i386 +*_GCCRISCV_RISCV32_ASM_FLAGS =3D DEF(GCCRISCV_ASM_FLAGS) -m32 -= march=3Di386 +*_GCCRISCV_RISCV32_CC_FLAGS =3D DEF(GCCRISCV_RISCV32_CC_FLAGS)= -Os +*_GCCRISCV_RISCV32_DLINK_FLAGS =3D DEF(GCCRISCV_RISCV32_RISCV64_D= LINK_FLAGS) -m elf_i386 --oformat=3Delf32-i386 +*_GCCRISCV_RISCV32_DLINK2_FLAGS =3D DEF(GCCRISCV_RISCV32_DLINK2_FL= AGS) +*_GCCRISCV_RISCV32_RC_FLAGS =3D DEF(GCC_IA32_RC_FLAGS) +*_GCCRISCV_RISCV32_OBJCOPY_FLAGS =3D +*_GCCRISCV_RISCV32_NASM_FLAGS =3D -f elf32 + +################## +# GCCRISCV RISCV64 definitions +################## +*_GCCRISCV_RISCV64_OBJCOPY_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-objcopy +*_GCCRISCV_RISCV64_CC_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_SLINK_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc-ar +*_GCCRISCV_RISCV64_DLINK_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-ld +*_GCCRISCV_RISCV64_ASLDLINK_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-ld +*_GCCRISCV_RISCV64_ASM_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_PP_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_VFRPP_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_ASLCC_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_ASLPP_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-gcc +*_GCCRISCV_RISCV64_RC_PATH =3D DEF(GCCRISCV_RISCV64_PREFIX)ri= scv64-unknown-elf-objcopy + +*_GCCRISCV_RISCV64_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS) -m64 +*_GCCRISCV_RISCV64_ASLDLINK_FLAGS =3D DEF(GCCRISCV_RISCV32_RISCV64_A= SLDLINK_FLAGS) -m elf_x86_64 +*_GCCRISCV_RISCV64_ASM_FLAGS =3D DEF(GCCRISCV_ASM_FLAGS)=20 +*_GCCRISCV_RISCV64_CC_FLAGS =3D DEF(GCCRISCV_RISCV64_CC_FLAGS)= -save-temps +*_GCCRISCV_RISCV64_DLINK_FLAGS =3D DEF(GCCRISCV_RISCV64_DLINK_FLA= GS) +*_GCCRISCV_RISCV64_DLINK2_FLAGS =3D DEF(GCCRISCV_RISCV64_DLINK2_FL= AGS) +*_GCCRISCV_RISCV64_RC_FLAGS =3D DEF(GCC_IA32_RC_FLAGS) +*_GCCRISCV_RISCV64_OBJCOPY_FLAGS =3D +*_GCCRISCV_RISCV64_NASM_FLAGS =3D -f elf64 + ##########################################################################= ########## # # CLANG35 - This configuration is used to compile under Linux to produce diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Co= mmon/BasePeCoff.c index e7566b3..e346e02 100644 --- a/BaseTools/Source/C/Common/BasePeCoff.c +++ b/BaseTools/Source/C/Common/BasePeCoff.c @@ -4,6 +4,7 @@ =20 Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage ( IN UINT64 Adjust ); =20 +RETURN_STATUS +PeCoffLoaderRelocateRiscVImage ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ); + STATIC RETURN_STATUS PeCoffLoaderGetPeHeader ( @@ -174,7 +183,10 @@ Returns: ImageContext->Machine !=3D EFI_IMAGE_MACHINE_X64 && \ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \ - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64) { + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \ + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV32 && \ + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \ + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV128) { if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) { // // There are two types of ARM images. Pure ARM and ARM/Thumb. @@ -802,6 +814,11 @@ Returns: case EFI_IMAGE_MACHINE_ARMT: Status =3D PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupDa= ta, Adjust); break; + case EFI_IMAGE_MACHINE_RISCV32: + case EFI_IMAGE_MACHINE_RISCV64: + case EFI_IMAGE_MACHINE_RISCV128: + Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupD= ata, Adjust); + break; default: Status =3D RETURN_UNSUPPORTED; break; diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/= C/Common/PeCoffLoaderEx.c index e367836..867c47b 100644 --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c @@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups =20 Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 --*/ @@ -61,6 +62,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMM64_SIGN_INST_WORD_POS_X 27 #define IMM64_SIGN_VAL_POS_X 63 =20 +// +// RISC-V definition. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + RiscVHi20Fixup =3D (UINT32 *) Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) | \ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + RiscVHi20Fixup =3D NULL; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25))); + } + RiscVHi20Fixup =3D NULL; + break; + + default: + return EFI_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} + /** Pass in a pointer to an ARM MOVT or MOVW immediate instruction and return the immediate data encoded in the instruction diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source= /C/GenFv/GenFvInternalLib.c index 908740d..b1dc7ec 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -4,6 +4,7 @@ This file contains the internal functions required to gener= ate a Firmware Volume Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
Portions Copyright (c) 2016 HP Development Company, L.P.
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development= LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 =20 BOOLEAN mArm =3D FALSE; +BOOLEAN mRiscV =3D FALSE; STATIC UINT32 MaxFfsAlignment =3D 0; BOOLEAN VtfFileFlag =3D FALSE; =20 @@ -1802,6 +1804,154 @@ if (MachineType =3D=3D EFI_IMAGE_MACHINE_IA32 || Ma= chineType =3D=3D EFI_IMAGE_MACHINE_X6 } =20 EFI_STATUS +RiscvPatchVtfTrapHandler (EFI_FFS_FILE_HEADER *VtfFileImage, UINTN UserTra= pAddressInFile) +/*++ + +Routine Description: + This patches RISC-V trap handler in VTF. + 0xF...FE00 Trap from user-mode + 0xF...FE40 Trap from supervisor-mode + 0xF...FE80 Trap from hypervisor-mode + 0xF...FEC0 Trap from machine-mode + 0xF...FEFC Non-maskable interrupt(s) +=20 +Arguments: + VtfFileImage VTF file. + UserTrapAddressInFile User Trap address in file image. + +Returns: + + EFI_SUCCESS Function Completed successfully. + EFI_ABORTED Error encountered. + EFI_INVALID_PARAMETER A required parameter was NULL. + EFI_NOT_FOUND PEI Core file not found. + +--*/ +{ + EFI_STATUS Status; + EFI_FILE_SECTION_POINTER Pe32Section; + UINT32 EntryPoint; + UINT32 BaseOfCode; + UINT16 MachineType; + UINT8 *HighTrapVectorAddress; + UINTN TrapPrivilegeNum; + + if (UserTrapAddressInFile =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + Status =3D GetSectionByType (VtfFileImage, EFI_SECTION_PE32, 1, &Pe32Sec= tion); // Get PE32 section. + if (!EFI_ERROR (Status)) { + Status =3D GetPe32Info ( // Get entry point. + (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength= (Pe32Section.CommonHeader)), + &EntryPoint, + &BaseOfCode, + &MachineType + ); + if (!EFI_ERROR (Status)) { + // + // Pacth trap handler. + // + HighTrapVectorAddress =3D (UINT8 *)((UINTN)EntryPoint + ((UINTN) Pe3= 2Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader))); + HighTrapVectorAddress -=3D (0x10 + 0x100); + + // + // Patch all privilege trap bases. + // + for (TrapPrivilegeNum =3D 0; TrapPrivilegeNum < 4; TrapPrivilegeNum = ++) { + *((UINT32 *)HighTrapVectorAddress) =3D (*((UINT32 *)HighTrapVector= Address) & 0xfff) | (*((UINT32 *)(UINTN)UserTrapAddressInFile) & 0xfffff000= );=20 + *((UINT32 *)(HighTrapVectorAddress + 4)) =3D (*((UINT32 *)(HighTra= pVectorAddress + 4)) & 0x000fffff) | ((*((UINT32 *)(UINTN)UserTrapAddressIn= File) & 0xfff) << 20); + HighTrapVectorAddress +=3D 0x40; + UserTrapAddressInFile +=3D 8; + } + + return EFI_SUCCESS; + } else { + Error (NULL, 0, 3000, "Invalid", "Patch RISC-V trap: Incorrect PE32 = format of RISC-V VTF"); + } + } else { + Error (NULL, 0, 3000, "Invalid", "atch RISC-V trap: Can't find PE32 se= ction of RISC-V VTF."); + } + return EFI_UNSUPPORTED; +} + +EFI_STATUS +RiscvPatchVtf (EFI_FFS_FILE_HEADER *VtfFileImage, UINT32 ResetVector) +/*++ + +Routine Description: + This patches the entry point of either SecCore or=20 + + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h + +Arguments: + VtfFileImage VTF file. + ResetVector Entry point for reset vector. + +Returns: + + EFI_SUCCESS Function Completed successfully. + EFI_ABORTED Error encountered. + EFI_INVALID_PARAMETER A required parameter was NULL. + EFI_NOT_FOUND PEI Core file not found. + +--*/ +{ + EFI_STATUS Status; + EFI_FILE_SECTION_POINTER Pe32Section; + UINT32 EntryPoint; + UINT8 *EntryPointAddress; + UINT32 *LoadHigh20BitInstrcutionAddr; + UINT32 *JmpLow12BitInstrcutionAddr; + UINT32 LoadHigh20BitAddressOffset; + UINT32 JmpLow12BitAddressOffset; + UINT32 BaseOfCode; + UINT16 MachineType; + UINT32 LoadHigh20BitOpc; + UINT32 JmpLow12BitOpc; + + if (ResetVector =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + Status =3D GetSectionByType (VtfFileImage, EFI_SECTION_PE32, 1, &Pe32Sec= tion); // Get PE32 section. + if (!EFI_ERROR (Status)) { + Status =3D GetPe32Info ( // Get entry point. + (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength= (Pe32Section.CommonHeader)), + &EntryPoint, + &BaseOfCode, + &MachineType + ); + if (!EFI_ERROR (Status)) { + EntryPointAddress =3D (UINT8 *)((UINTN)EntryPoint + ((UINTN) Pe32Sec= tion.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader))); + LoadHigh20BitAddressOffset =3D *((UINT32 *)(EntryPointAddress - 16))= ; // (Entrypoint - 16) map to the second qword from Entrypoint + JmpLow12BitAddressOffset =3D *((UINT32 *)(EntryPointAddress - 8)); /= / (Entrypoint - 8) map to the second qword from Entrypoint + LoadHigh20BitInstrcutionAddr =3D (UINT32 *)(EntryPointAddress + Load= High20BitAddressOffset); + JmpLow12BitInstrcutionAddr =3D (UINT32 *)(EntryPointAddress + JmpLow= 12BitAddressOffset); + // + // Patch RISC-V instruction : li a0, 0x12345000 + // + LoadHigh20BitOpc =3D *LoadHigh20BitInstrcutionAddr; + LoadHigh20BitOpc =3D (LoadHigh20BitOpc & 0xfff) | (ResetVector & 0xf= ffff000); + *((UINT32 *)(EntryPointAddress - 16)) =3D LoadHigh20BitOpc; + // + // Patch RISC-V instruction : jalr x0, a0, 0x678 + // + JmpLow12BitOpc =3D *JmpLow12BitInstrcutionAddr; + JmpLow12BitOpc =3D (JmpLow12BitOpc & 0x000fffff) | ((ResetVector & 0= xfff) << 20); + *((UINT32 *)(EntryPointAddress - 12)) =3D JmpLow12BitOpc; + return EFI_SUCCESS; + } else { + Error (NULL, 0, 3000, "Invalid", "Incorrect PE32 format of RISC-V VT= F"); + } + } else { + Error (NULL, 0, 3000, "Invalid", "Can't find PE32 section of RISC-V VT= F."); + } + return EFI_UNSUPPORTED; +} + + +EFI_STATUS FindCorePeSection( IN VOID *FvImageBuffer, IN UINT64 FvSize, @@ -2274,6 +2424,106 @@ Returns: } =20 EFI_STATUS +UpdateRiscvResetVectorIfNeeded ( + MEMORY_FILE *FvImage, + FV_INFO *FvInfo + ) +/*++ + +Routine Description: + This parses the FV looking for SEC and patches that address into the=20 + beginning of the FV header. + + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h + +Arguments: + FvImage Memory file for the FV memory image/ + FvInfo Information read from INF file. + +Returns: + + EFI_SUCCESS Function Completed successfully. + EFI_ABORTED Error encountered. + EFI_INVALID_PARAMETER A required parameter was NULL. + EFI_NOT_FOUND PEI Core file not found. + +--*/ +{ + EFI_STATUS Status; + UINT16 MachineType; + EFI_FILE_SECTION_POINTER SecPe32; + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress; + + UINT32 bSecCore; + UINT32 tmp; + + + // + // Verify input parameters + // + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Initialize FV library + // + InitializeFvLib (FvImage->FileImage, FvInfo->Size); + + // + // Find the Sec Core + // + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FI= LETYPE_SECURITY_CORE, &SecPe32);=20 + if(EFI_ERROR(Status)) { + printf("skip because Secutiry Core not found\n"); + return EFI_SUCCESS; + } + + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL); + + Status =3D GetCoreMachineType(SecPe32, &MachineType); + if(EFI_ERROR(Status)) { + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type f= or SEC core."); + return EFI_ABORTED; + } + + if ((MachineType !=3D EFI_IMAGE_MACHINE_RISCV32) && (MachineType !=3D EF= I_IMAGE_MACHINE_RISCV64)) { + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Mac= hine type is not RiscV."); + return EFI_ABORTED; + } + + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32,= &SecCoreEntryAddress); + if(EFI_ERROR(Status)) { + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point ad= dress for SEC Core."); + return EFI_ABORTED; + } + + VerboseMsg("SecCore entry point Address =3D 0x%llX", (unsigned long long= ) SecCoreEntryAddress); + VerboseMsg("BaseAddress =3D 0x%llX", (unsigned long long) FvInfo->BaseAd= dress); + bSecCore =3D (SecCoreEntryAddress - FvInfo->BaseAddress); + VerboseMsg("offset =3D 0x%llX", bSecCore); + + if(bSecCore > 0x0fffff) { + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of= start of the FV"); + return EFI_ABORTED; + } + + tmp =3D bSecCore; + bSecCore =3D 0; + //J-type + bSecCore =3D (tmp&0x100000)<<11; //imm[20] at bit[31] + bSecCore |=3D (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21] + bSecCore |=3D (tmp&0x000800)<<9; //imm[11] at bit[20] + bSecCore |=3D (tmp&0x0FF000); //imm[19:12] at bit[19:12] + bSecCore |=3D 0x6F; //JAL opcode + + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore)); + + return EFI_SUCCESS; +} + + + +EFI_STATUS GetPe32Info ( IN UINT8 *Pe32, OUT UINT32 *EntryPoint, @@ -2365,7 +2615,8 @@ Returns: // Verify machine type is supported // if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D EF= I_IMAGE_MACHINE_X64) && (*MachineType !=3D EFI_IMAGE_MACHINE_EBC) && - (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64)) { + (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64) && + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV32) && (*MachineType !=3D = EFI_IMAGE_MACHINE_RISCV64) && (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV128= )) { Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE3= 2 file."); return EFI_UNSUPPORTED; } @@ -2777,7 +3028,6 @@ Returns: FvHeader->Checksum =3D 0; FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, = FvHeader->HeaderLength / sizeof (UINT16)); } - // // Add files to FV // @@ -2808,7 +3058,8 @@ Returns: Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad = file between the last file and the VTF file."); goto Finish; } - if (!mArm) { + + if (!mArm && !mRiscV) { // // Update reset vector (SALE_ENTRY for IPF) // Now for IA32 and IA64 platform, the fv which has bsf file must ha= ve the @@ -2843,6 +3094,22 @@ Returns: FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16)); } =20 + if (mRiscV) { + // + // Update RISCV reset vector. + // + Status =3D UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDa= taInfo); + if (EFI_ERROR (Status)) { + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector= for RISC-V."); + goto Finish; + } + // + // Update Checksum for FvHeader + // + FvHeader->Checksum =3D 0; + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16)); + } + // // Update FV Alignment attribute to the largest alignment of all the FFS= files in the FV // @@ -3430,6 +3697,12 @@ Returns: mArm =3D TRUE; } =20 + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_RISCV32) || + (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_RISCV64) || + (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_RISCV128)) { + mRiscV =3D TRUE; + } + // // Keep Image Context for PE image in FV // @@ -3583,7 +3856,7 @@ Returns: ImageContext.DestinationAddress =3D NewPe32BaseAddress; Status =3D PeCoffLoaderRelocateImage (&ImageC= ontext); if (EFI_ERROR (Status)) { - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s", FileName); + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s Status=3D%d", FileName, Status); free ((VOID *) MemoryImagePointer); return Status; } diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/G= enFw/Elf32Convert.c index 46089ff..3e47475 100644 --- a/BaseTools/Source/C/GenFw/Elf32Convert.c +++ b/BaseTools/Source/C/GenFw/Elf32Convert.c @@ -3,6 +3,7 @@ Elf32 Convert solution =20 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -141,8 +142,9 @@ InitializeElf32 ( Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN= "); return FALSE; } - if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M))) { - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_A= RM"); + + if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M) || (mEhdr->e_machine =3D=3D EM_RISCV))) { + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386, EM_ARM= or EM_RISCV"); return FALSE; } if (mEhdr->e_version !=3D EV_CURRENT) { diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index 3d6319c..e65f640 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -3,6 +3,7 @@ Elf64 convert solution =20 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+Portions Copyright (c) 2016 - 2017 Hewlett Packard Enterprise Development = LP. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -31,6 +32,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "ElfConvert.h" #include "Elf64Convert.h" =20 +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL<e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) { + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64, EM_= AARCH64 or EM_RISCV64"); return FALSE; } if (mEhdr->e_version !=3D EV_CURRENT) { @@ -481,6 +489,7 @@ ScanSections64 ( switch (mEhdr->e_machine) { case EM_X86_64: case EM_AARCH64: + case EM_RISCV64: mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64); break; default: @@ -690,6 +699,12 @@ ScanSections64 ( NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_AARCH64; NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC; break; + + case EM_RISCV64: + NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64; + NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC; + break; + default: VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_m= achine); NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_X64; @@ -769,6 +784,11 @@ WriteSections64 ( Elf_Shdr *SecShdr; UINT32 SecOffset; BOOLEAN (*Filter)(Elf_Shdr *); + UINT32 Value; + UINT32 Value2; + UINT8 *RiscvHi20Targ =3D NULL; + Elf_Shdr *RiscvHi20Sym =3D NULL; + Elf64_Half RiscvSymSecIndex =3D 0; Elf64_Addr GOTEntryRva; =20 // @@ -893,13 +913,14 @@ WriteSections64 ( if (SymName =3D=3D NULL) { SymName =3D (const UINT8 *)""; } - - Error (NULL, 0, 3000, "Invalid", - "%s: Bad definition for symbol '%s'@%#llx or unsupported = symbol type. " - "For example, absolute and undefined symbols are not supp= orted.", - mInImageName, SymName, Sym->st_value); - - exit(EXIT_FAILURE); + if (mEhdr->e_machine !=3D EM_RISCV64) { + Error (NULL, 0, 3000, "Invalid", + "%s: Bad definition for symbol '%s'@%#llx or unsupporte= d symbol type. " + "For example, absolute and undefined symbols are not su= pported.", + mInImageName, SymName, Sym->st_value); + + exit(EXIT_FAILURE); + } } SymShdr =3D GetShdrByIndex(Sym->st_shndx); =20 @@ -1114,6 +1135,135 @@ WriteSections64 ( default: Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE= (Rel->r_info)); } + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) { + switch (ELF_R_TYPE(Rel->r_info)) { + case R_RISCV_NONE: + break; + case R_RISCV_32: + *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymSh= dr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); + break; + case R_RISCV_64: + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoff= SectionsOffset[Sym->st_shndx]; + break; + case R_RISCV_HI20: + RiscvHi20Targ =3D Targ; + RiscvHi20Sym =3D SymShdr; + RiscvSymSecIndex =3D Sym->st_shndx; + break; + case R_RISCV_LO12_I: + if (RiscvHi20Sym =3D=3D SymShdr && RiscvHi20Targ !=3D NULL && = RiscvSymSecIndex =3D=3D Sym->st_shndx && RiscvSymSecIndex !=3D 0) { + Value =3D (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20) <<= 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value =3D Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx]; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscvHi20Targ =3D (RV_X (Value2, 12, 20) << 12) |= \ + (RV_X (*(UINT32 *)RiscvHi20Targ, = 0, 12)); + *(UINT32 *)Targ =3D (RV_X (Value, 0, 12) << 20) | \ + (RV_X (*(UINT32 *)Targ, 0, 20)); + } + RiscvHi20Sym =3D NULL; + RiscvHi20Targ =3D NULL; + RiscvSymSecIndex =3D 0; + break; + + case R_RISCV_LO12_S: + if (RiscvHi20Sym =3D=3D SymShdr && RiscvHi20Targ !=3D NULL && = RiscvSymSecIndex =3D=3D Sym->st_shndx && RiscvSymSecIndex !=3D 0) { + Value =3D (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20) <<= 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UI= NT32 *)Targ, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value =3D Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx]; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscvHi20Targ =3D (RV_X (Value2, 12, 20) << 12) |= \ + (RV_X (*(UINT32 *)RiscvHi20Targ, = 0, 12)); + + Value2 =3D *(UINT32 *)Targ & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Targ =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) <<= 7) | (RV_X(Value, 5, 7) << 25))); + } + RiscvHi20Sym =3D NULL; + RiscvHi20Targ =3D NULL; + RiscvSymSecIndex =3D 0; + break; + + case R_RISCV_PCREL_HI20: + RiscvHi20Targ =3D Targ; + RiscvHi20Sym =3D SymShdr; + RiscvSymSecIndex =3D Sym->st_shndx; + + Value =3D (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20)); + //printf("PCREL_HI20 Sym:[%s] value:0x%x SymShdr->sh_addr:0x%l= x mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, mCof= fSectionsOffset[Sym->st_shndx]); + break; + case R_RISCV_PCREL_LO12_I: + if (RiscvHi20Targ !=3D NULL && RiscvHi20Sym !=3D NULL && Riscv= SymSecIndex !=3D 0) { + int i; + Value2 =3D (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20)); + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); + if(Value & (RISCV_IMM_REACH/2)) { + Value |=3D ~(RISCV_IMM_REACH-1); + } + //printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr->sh_addr:= 0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, = mCoffSectionsOffset[Sym->st_shndx]); + Value =3D Value - RiscvHi20Sym->sh_addr + mCoffSectionsOffse= t[RiscvSymSecIndex]; + if(-2048 > (INT32)Value) { =20 + i =3D (-Value / 4096); =20 + //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCR= EL_LO12_I relocation out of range. %d i=3D%d", Value, i); + printf("WriteSections64(): PCREL_LO12_I relocation out of = range. Value:%d Value2:%d i=3D%d\n", Value, Value2, i); + Value2 -=3D i; + Value +=3D 4096 * i; + if(-2048 > (INT32)Value) { + Value2 -=3D 1; + Value +=3D 4096; + } + } + else if( 2047 < (INT32)Value) { + i =3D (Value / 4096); + //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCR= EL_LO12_I relocation out of range. %d i=3D%d", Value, i); + printf("WriteSections64(): PCREL_LO12_I relocation out of = range. Value:%d Value2:%d i=3D%d\n", Value, Value2, i); + Value2 +=3D i; + Value -=3D 4096 * i; + if(2047 < (INT32)Value) { + Value2 +=3D 1; + Value -=3D 4096; + } + } + + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UIN= T32*)Targ, 0, 20)); + *(UINT32 *)RiscvHi20Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV= _X(*(UINT32 *)RiscvHi20Targ, 0, 12)); + //printf("PCREL_LO12_I Sym:[%s] relocated value:0x%x(%d) val= ue2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(S= ym), Value, Value, Value2, Value2, SymShdr->sh_addr, mCoffSectionsOffset[S= ym->st_shndx]); + } + RiscvHi20Sym =3D NULL; + RiscvHi20Targ =3D NULL; + RiscvSymSecIndex =3D 0; + break; + + case R_RISCV_ADD64: + case R_RISCV_SUB64: + case R_RISCV_ADD32: + case R_RISCV_SUB32: + case R_RISCV_BRANCH: + case R_RISCV_JAL: + case R_RISCV_GPREL_I: + case R_RISCV_GPREL_S: + case R_RISCV_CALL: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + case R_RISCV_RELAX: + case R_RISCV_SUB6: + case R_RISCV_SET6: + case R_RISCV_SET8: + case R_RISCV_SET16: + case R_RISCV_SET32: + break; + + default: + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE= (Rel->r_info)); + } } else { Error (NULL, 0, 3000, "Invalid", "Not a supported machine type"); } @@ -1133,6 +1283,7 @@ WriteRelocations64 ( UINT32 Index; EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr; EFI_IMAGE_DATA_DIRECTORY *Dir; + UINT32 RiscVRelType; =20 for (Index =3D 0; Index < mEhdr->e_shnum; Index++) { Elf_Shdr *RelShdr =3D GetShdrByIndex(Index); @@ -1237,8 +1388,110 @@ WriteRelocations64 ( default: Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s= unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF= _R_TYPE(Rel->r_info)); } + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) { + RiscVRelType =3D ELF_R_TYPE(Rel->r_info); + switch (RiscVRelType) { + case R_RISCV_NONE: + break; + + case R_RISCV_32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_HIGHLOW); + break; + + case R_RISCV_64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_DIR64); + break; + + case R_RISCV_HI20: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_HI20); + break; + + case R_RISCV_LO12_I: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_LOW12I); + break; + + case R_RISCV_LO12_S: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_RISCV_LOW12S); + break; + + case R_RISCV_ADD64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_SUB64: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_ADD32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_SUB32: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_BRANCH: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_JAL: + CoffAddFixup( + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info] + + (Rel->r_offset - SecShdr->sh_addr)), + EFI_IMAGE_REL_BASED_ABSOLUTE); + break; + + case R_RISCV_GPREL_I: + case R_RISCV_GPREL_S: + case R_RISCV_CALL: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + case R_RISCV_RELAX: + case R_RISCV_SUB6: + case R_RISCV_SET6: + case R_RISCV_SET8: + case R_RISCV_SET16: + case R_RISCV_SET32: + case R_RISCV_PCREL_HI20: + case R_RISCV_PCREL_LO12_I: + break; + + default: + printf ("Unsupported RISCV64 ELF relocation type 0x%x, offse= t: %lx\n", RiscVRelType, Rel->r_offset); + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s u= nsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R= _TYPE(Rel->r_info)); + } } else { - Error (NULL, 0, 3000, "Not Supported", "This tool does not sup= port relocations for ELF with e_machine %u (processor type).", (unsigned) m= Ehdr->e_machine); + Error (NULL, 0, 3000, "Not Supported", "This tool does not s= upport relocations for ELF with e_machine %u (processor type).", (unsigned)= mEhdr->e_machine); } } if (mEhdr->e_machine =3D=3D EM_X86_64 && RelShdr->sh_info =3D=3D m= GOTShindex) { diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/Gen= Fw/elf_common.h index 15c9e33..5f286cc 100644 --- a/BaseTools/Source/C/GenFw/elf_common.h +++ b/BaseTools/Source/C/GenFw/elf_common.h @@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD =20 Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Portion Copyright (c) 2016 - 2017, Hewlett Packard Enterprise Development = LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 =20 @@ -178,6 +179,9 @@ typedef struct { #define EM_X86_64 62 /* Advanced Micro Devices x86-64 */ #define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */ #define EM_AARCH64 183 /* ARM 64bit Architecture */ +#define EM_RISCV64 243 /* 64bit RISC-V Architecture */ +#define EM_RISCV 244 /* 32bit RISC-V Architecture */ +#define EM_RISCV128 245 /* 128bit RISC-V Architecture */ =20 /* Non-standard or deprecated. */ #define EM_486 6 /* Intel i486. */ @@ -979,5 +983,64 @@ typedef struct { #define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative of= fset to GOT entry without REX prefix, relaxable. */ #define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relativ= e offset to GOT entry with REX prefix, relaxable. */ =20 +/*=20 + * RISC-V relocation types=20 + */=20 +=20 +/* Relocation types used by the dynamic linker */ +#define R_RISCV_NONE 0 +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JUMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_TPREL64 11 =20 +/* Relocation types not used by the dynamic linker */ +#define R_RISCV_BRANCH 16 +#define R_RISCV_JAL 17 +#define R_RISCV_CALL 18 +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 +#define R_RISCV_LO12_I 27 +#define R_RISCV_LO12_S 28 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GNU_VTINHERIT 41 +#define R_RISCV_GNU_VTENTRY 42 +#define R_RISCV_ALIGN 43 +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 +#define R_RISCV_RVC_LUI 46 +#define R_RISCV_GPREL_I 47 +#define R_RISCV_GPREL_S 48 +#define R_RISCV_TPREL_I 49 +#define R_RISCV_TPREL_S 50 +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 #endif /* !_SYS_ELF_COMMON_H_ */ diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTo= ols/Source/C/Include/IndustryStandard/PeImage.h index 44037d1..4edf2d4 100644 --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h @@ -6,6 +6,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -41,6 +42,9 @@ #define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only #define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/T= humb 2 Little Endian #define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Lit= tle Endian +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 // 32bit RISC-V ISA +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 // 128bit RISC-V ISA =20 // // Support old names for backward compatible @@ -50,6 +54,9 @@ #define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 #define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT #define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64 +#define EFI_IMAGE_MACHINE_RISCV32 IMAGE_FILE_MACHINE_RISCV32 +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64 +#define EFI_IMAGE_MACHINE_RISCV128 IMAGE_FILE_MACHINE_RISCV128 =20 #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE @@ -504,7 +511,10 @@ typedef struct { #define EFI_IMAGE_REL_BASED_HIGHADJ 4 #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 #define EFI_IMAGE_REL_BASED_IA64_IMM64 9 #define EFI_IMAGE_REL_BASED_DIR64 10 =20 diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/= Python/Common/DataType.py index 8ae1bd2..2ee6b37 100644 --- a/BaseTools/Source/Python/Common/DataType.py +++ b/BaseTools/Source/Python/Common/DataType.py @@ -1,535 +1,540 @@ -## @file -# This file is used to define common static strings used by INF/DEC/DSC fi= les -# -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
-# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent - -## -# Common Definitions -# -TAB_SPLIT =3D '.' -TAB_COMMENT_EDK_START =3D '/*' -TAB_COMMENT_EDK_END =3D '*/' -TAB_COMMENT_EDK_SPLIT =3D '//' -TAB_COMMENT_SPLIT =3D '#' -TAB_SPECIAL_COMMENT =3D '##' -TAB_EQUAL_SPLIT =3D '=3D' -TAB_VALUE_SPLIT =3D '|' -TAB_COMMA_SPLIT =3D ',' -TAB_SPACE_SPLIT =3D ' ' -TAB_SEMI_COLON_SPLIT =3D ';' -TAB_SECTION_START =3D '[' -TAB_SECTION_END =3D ']' -TAB_OPTION_START =3D '<' -TAB_OPTION_END =3D '>' -TAB_SLASH =3D '\\' -TAB_BACK_SLASH =3D '/' -TAB_STAR =3D '*' -TAB_LINE_BREAK =3D '\n' -TAB_PRINTCHAR_VT =3D '\x0b' -TAB_PRINTCHAR_BS =3D '\b' -TAB_PRINTCHAR_NUL =3D '\0' -TAB_UINT8 =3D 'UINT8' -TAB_UINT16 =3D 'UINT16' -TAB_UINT32 =3D 'UINT32' -TAB_UINT64 =3D 'UINT64' -TAB_VOID =3D 'VOID*' -TAB_GUID =3D 'GUID' - -TAB_PCD_CLEAN_NUMERIC_TYPES =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UI= NT64} -TAB_PCD_NUMERIC_TYPES =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UINT64, = 'BOOLEAN'} -TAB_PCD_NUMERIC_TYPES_VOID =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UIN= T64, 'BOOLEAN', TAB_VOID} - -TAB_WORKSPACE =3D '$(WORKSPACE)' -TAB_FV_DIRECTORY =3D 'FV' - -TAB_ARCH_NULL =3D '' -TAB_ARCH_COMMON =3D 'COMMON' -TAB_ARCH_IA32 =3D 'IA32' -TAB_ARCH_X64 =3D 'X64' -TAB_ARCH_ARM =3D 'ARM' -TAB_ARCH_EBC =3D 'EBC' -TAB_ARCH_AARCH64 =3D 'AARCH64' - -ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_COMMON} - -SUP_MODULE_BASE =3D 'BASE' -SUP_MODULE_SEC =3D 'SEC' -SUP_MODULE_PEI_CORE =3D 'PEI_CORE' -SUP_MODULE_PEIM =3D 'PEIM' -SUP_MODULE_DXE_CORE =3D 'DXE_CORE' -SUP_MODULE_DXE_DRIVER =3D 'DXE_DRIVER' -SUP_MODULE_DXE_RUNTIME_DRIVER =3D 'DXE_RUNTIME_DRIVER' -SUP_MODULE_DXE_SAL_DRIVER =3D 'DXE_SAL_DRIVER' -SUP_MODULE_DXE_SMM_DRIVER =3D 'DXE_SMM_DRIVER' -SUP_MODULE_UEFI_DRIVER =3D 'UEFI_DRIVER' -SUP_MODULE_UEFI_APPLICATION =3D 'UEFI_APPLICATION' -SUP_MODULE_USER_DEFINED =3D 'USER_DEFINED' -SUP_MODULE_HOST_APPLICATION =3D 'HOST_APPLICATION' -SUP_MODULE_SMM_CORE =3D 'SMM_CORE' -SUP_MODULE_MM_STANDALONE =3D 'MM_STANDALONE' -SUP_MODULE_MM_CORE_STANDALONE =3D 'MM_CORE_STANDALONE' - -SUP_MODULE_LIST =3D [SUP_MODULE_BASE, SUP_MODULE_SEC, SUP_MODULE_PEI_CORE,= SUP_MODULE_PEIM, SUP_MODULE_DXE_CORE, SUP_MODULE_DXE_DRIVER, \ - SUP_MODULE_DXE_RUNTIME_DRIVER, SUP_MODULE_DXE_SAL_DRIVE= R, SUP_MODULE_DXE_SMM_DRIVER, SUP_MODULE_UEFI_DRIVER, \ - SUP_MODULE_UEFI_APPLICATION, SUP_MODULE_USER_DEFINED, S= UP_MODULE_HOST_APPLICATION, SUP_MODULE_SMM_CORE, SUP_MODULE_MM_STANDALONE, = SUP_MODULE_MM_CORE_STANDALONE] -SUP_MODULE_LIST_STRING =3D TAB_VALUE_SPLIT.join(SUP_MODULE_LIST) -SUP_MODULE_SET_PEI =3D {SUP_MODULE_PEIM, SUP_MODULE_PEI_CORE} - -EDK_COMPONENT_TYPE_LIBRARY =3D 'LIBRARY' -EDK_COMPONENT_TYPE_SECURITY_CORE =3D 'SECURITY_CORE' -EDK_COMPONENT_TYPE_PEI_CORE =3D SUP_MODULE_PEI_CORE -EDK_COMPONENT_TYPE_COMBINED_PEIM_DRIVER =3D 'COMBINED_PEIM_DRIVER' -EDK_COMPONENT_TYPE_PIC_PEIM =3D 'PIC_PEIM' -EDK_COMPONENT_TYPE_RELOCATABLE_PEIM =3D 'RELOCATABLE_PEIM' -EDK_COMPONENT_TYPE_BS_DRIVER =3D 'BS_DRIVER' -EDK_COMPONENT_TYPE_RT_DRIVER =3D 'RT_DRIVER' -EDK_COMPONENT_TYPE_SAL_RT_DRIVER =3D 'SAL_RT_DRIVER' -EDK_COMPONENT_TYPE_APPLICATION =3D 'APPLICATION' -EDK_NAME =3D 'EDK' -EDKII_NAME =3D 'EDKII' -MSG_EDKII_MAIL_ADDR =3D 'devel@edk2.groups.io' - -COMPONENT_TO_MODULE_MAP_DICT =3D { - EDK_COMPONENT_TYPE_LIBRARY : SUP_MODULE_BASE, - EDK_COMPONENT_TYPE_SECURITY_CORE : SUP_MODULE_SEC, - EDK_COMPONENT_TYPE_PEI_CORE : SUP_MODULE_PEI_CORE, - EDK_COMPONENT_TYPE_COMBINED_PEIM_DRIVER : SUP_MODULE_PEIM, - EDK_COMPONENT_TYPE_PIC_PEIM : SUP_MODULE_PEIM, - EDK_COMPONENT_TYPE_RELOCATABLE_PEIM : SUP_MODULE_PEIM, - "PE32_PEIM" : SUP_MODULE_PEIM, - EDK_COMPONENT_TYPE_BS_DRIVER : SUP_MODULE_DXE_DRIVER, - EDK_COMPONENT_TYPE_RT_DRIVER : SUP_MODULE_DXE_RUNTIME_DR= IVER, - EDK_COMPONENT_TYPE_SAL_RT_DRIVER : SUP_MODULE_DXE_SAL_DRIVER, - EDK_COMPONENT_TYPE_APPLICATION : SUP_MODULE_UEFI_APPLICATI= ON, - "LOGO" : SUP_MODULE_BASE, -} - -BINARY_FILE_TYPE_FW =3D 'FW' -BINARY_FILE_TYPE_GUID =3D 'GUID' -BINARY_FILE_TYPE_PREEFORM =3D 'PREEFORM' -BINARY_FILE_TYPE_UEFI_APP =3D 'UEFI_APP' -BINARY_FILE_TYPE_UNI_UI =3D 'UNI_UI' -BINARY_FILE_TYPE_UNI_VER =3D 'UNI_VER' -BINARY_FILE_TYPE_LIB =3D 'LIB' -BINARY_FILE_TYPE_PE32 =3D 'PE32' -BINARY_FILE_TYPE_PIC =3D 'PIC' -BINARY_FILE_TYPE_PEI_DEPEX =3D 'PEI_DEPEX' -BINARY_FILE_TYPE_DXE_DEPEX =3D 'DXE_DEPEX' -BINARY_FILE_TYPE_SMM_DEPEX =3D 'SMM_DEPEX' -BINARY_FILE_TYPE_TE =3D 'TE' -BINARY_FILE_TYPE_VER =3D 'VER' -BINARY_FILE_TYPE_UI =3D 'UI' -BINARY_FILE_TYPE_BIN =3D 'BIN' -BINARY_FILE_TYPE_FV =3D 'FV' -BINARY_FILE_TYPE_RAW =3D 'RAW_BINARY' - -PLATFORM_COMPONENT_TYPE_LIBRARY_CLASS =3D 'LIBRARY_CLASS' -PLATFORM_COMPONENT_TYPE_MODULE =3D 'MODULE' - -TAB_SOURCES =3D 'Sources' -TAB_SOURCES_COMMON =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_COMMON -TAB_SOURCES_IA32 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IA32 -TAB_SOURCES_X64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64 -TAB_SOURCES_ARM =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM -TAB_SOURCES_EBC =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC -TAB_SOURCES_AARCH64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_BINARIES =3D 'Binaries' -TAB_BINARIES_COMMON =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON -TAB_BINARIES_IA32 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IA32 -TAB_BINARIES_X64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64 -TAB_BINARIES_ARM =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM -TAB_BINARIES_EBC =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC -TAB_BINARIES_AARCH64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_INCLUDES =3D 'Includes' -TAB_INCLUDES_COMMON =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON -TAB_INCLUDES_IA32 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IA32 -TAB_INCLUDES_X64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64 -TAB_INCLUDES_ARM =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM -TAB_INCLUDES_EBC =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC -TAB_INCLUDES_AARCH64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_GUIDS =3D 'Guids' -TAB_GUIDS_COMMON =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON -TAB_GUIDS_IA32 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IA32 -TAB_GUIDS_X64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64 -TAB_GUIDS_ARM =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM -TAB_GUIDS_EBC =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC -TAB_GUIDS_AARCH64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_PROTOCOLS =3D 'Protocols' -TAB_PROTOCOLS_COMMON =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON -TAB_PROTOCOLS_IA32 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IA32 -TAB_PROTOCOLS_X64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64 -TAB_PROTOCOLS_ARM =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM -TAB_PROTOCOLS_EBC =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC -TAB_PROTOCOLS_AARCH64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_PPIS =3D 'Ppis' -TAB_PPIS_COMMON =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON -TAB_PPIS_IA32 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_IA32 -TAB_PPIS_X64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64 -TAB_PPIS_ARM =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM -TAB_PPIS_EBC =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC -TAB_PPIS_AARCH64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_LIBRARY_CLASSES =3D 'LibraryClasses' -TAB_LIBRARY_CLASSES_COMMON =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_= COMMON -TAB_LIBRARY_CLASSES_IA32 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IA= 32 -TAB_LIBRARY_CLASSES_X64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64 -TAB_LIBRARY_CLASSES_ARM =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM -TAB_LIBRARY_CLASSES_EBC =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC -TAB_LIBRARY_CLASSES_AARCH64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH= _AARCH64 - -TAB_PACKAGES =3D 'Packages' -TAB_PACKAGES_COMMON =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON -TAB_PACKAGES_IA32 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IA32 -TAB_PACKAGES_X64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64 -TAB_PACKAGES_ARM =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM -TAB_PACKAGES_EBC =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC -TAB_PACKAGES_AARCH64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_PCDS =3D 'Pcds' -TAB_PCDS_FIXED_AT_BUILD =3D 'FixedAtBuild' -TAB_PCDS_PATCHABLE_IN_MODULE =3D 'PatchableInModule' -TAB_PCDS_FEATURE_FLAG =3D 'FeatureFlag' -TAB_PCDS_DYNAMIC_EX =3D 'DynamicEx' -TAB_PCDS_DYNAMIC_EX_DEFAULT =3D 'DynamicExDefault' -TAB_PCDS_DYNAMIC_EX_VPD =3D 'DynamicExVpd' -TAB_PCDS_DYNAMIC_EX_HII =3D 'DynamicExHii' -TAB_PCDS_DYNAMIC =3D 'Dynamic' -TAB_PCDS_DYNAMIC_DEFAULT =3D 'DynamicDefault' -TAB_PCDS_DYNAMIC_VPD =3D 'DynamicVpd' -TAB_PCDS_DYNAMIC_HII =3D 'DynamicHii' - -PCD_DYNAMIC_TYPE_SET =3D {TAB_PCDS_DYNAMIC, TAB_PCDS_DYNAMIC_DEFAULT, TAB_= PCDS_DYNAMIC_VPD, TAB_PCDS_DYNAMIC_HII} -PCD_DYNAMIC_EX_TYPE_SET =3D {TAB_PCDS_DYNAMIC_EX, TAB_PCDS_DYNAMIC_EX_DEFA= ULT, TAB_PCDS_DYNAMIC_EX_VPD, TAB_PCDS_DYNAMIC_EX_HII} - -# leave as a list for order -PCD_TYPE_LIST =3D [TAB_PCDS_FIXED_AT_BUILD, TAB_PCDS_PATCHABLE_IN_MODULE, = TAB_PCDS_FEATURE_FLAG, TAB_PCDS_DYNAMIC, TAB_PCDS_DYNAMIC_EX] - -TAB_PCDS_FIXED_AT_BUILD_NULL =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD -TAB_PCDS_FIXED_AT_BUILD_COMMON =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TA= B_SPLIT + TAB_ARCH_COMMON -TAB_PCDS_FIXED_AT_BUILD_IA32 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_= SPLIT + TAB_ARCH_IA32 -TAB_PCDS_FIXED_AT_BUILD_X64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_X64 -TAB_PCDS_FIXED_AT_BUILD_ARM =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_ARM -TAB_PCDS_FIXED_AT_BUILD_EBC =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_EBC -TAB_PCDS_FIXED_AT_BUILD_AARCH64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + T= AB_SPLIT + TAB_ARCH_AARCH64 - -TAB_PCDS_PATCHABLE_IN_MODULE_NULL =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MOD= ULE -TAB_PCDS_PATCHABLE_IN_MODULE_COMMON =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_M= ODULE + TAB_SPLIT + TAB_ARCH_COMMON -TAB_PCDS_PATCHABLE_IN_MODULE_IA32 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MOD= ULE + TAB_SPLIT + TAB_ARCH_IA32 -TAB_PCDS_PATCHABLE_IN_MODULE_X64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_X64 -TAB_PCDS_PATCHABLE_IN_MODULE_ARM =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_ARM -TAB_PCDS_PATCHABLE_IN_MODULE_EBC =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_EBC -TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_= MODULE + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_PCDS_FEATURE_FLAG_NULL =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG -TAB_PCDS_FEATURE_FLAG_COMMON =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SP= LIT + TAB_ARCH_COMMON -TAB_PCDS_FEATURE_FLAG_IA32 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLI= T + TAB_ARCH_IA32 -TAB_PCDS_FEATURE_FLAG_X64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_X64 -TAB_PCDS_FEATURE_FLAG_ARM =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_ARM -TAB_PCDS_FEATURE_FLAG_EBC =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_EBC -TAB_PCDS_FEATURE_FLAG_AARCH64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_S= PLIT + TAB_ARCH_AARCH64 - -TAB_PCDS_DYNAMIC_EX_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX -TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAULT -TAB_PCDS_DYNAMIC_EX_HII_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_HII -TAB_PCDS_DYNAMIC_EX_VPD_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_VPD -TAB_PCDS_DYNAMIC_EX_COMMON =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT = + TAB_ARCH_COMMON -TAB_PCDS_DYNAMIC_EX_IA32 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + = TAB_ARCH_IA32 -TAB_PCDS_DYNAMIC_EX_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_X64 -TAB_PCDS_DYNAMIC_EX_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_ARM -TAB_PCDS_DYNAMIC_EX_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_EBC -TAB_PCDS_DYNAMIC_EX_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT= + TAB_ARCH_AARCH64 - -TAB_PCDS_DYNAMIC_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC -TAB_PCDS_DYNAMIC_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT -TAB_PCDS_DYNAMIC_HII_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_HII -TAB_PCDS_DYNAMIC_VPD_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_VPD -TAB_PCDS_DYNAMIC_COMMON =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_= ARCH_COMMON -TAB_PCDS_DYNAMIC_IA32 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_AR= CH_IA32 -TAB_PCDS_DYNAMIC_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_X64 -TAB_PCDS_DYNAMIC_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_ARM -TAB_PCDS_DYNAMIC_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_EBC -TAB_PCDS_DYNAMIC_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB= _ARCH_AARCH64 - -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE =3D 'PcdLoadFixAddressPe= iCodePageNumber' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE_DATA_TYPE =3D 'UINT32' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_DXE_PAGE_SIZE =3D 'PcdLoadFixAddressBo= otTimeCodePageNumber' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_DXE_PAGE_SIZE_DATA_TYPE =3D 'UINT32' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_RUNTIME_PAGE_SIZE =3D 'PcdLoadFixAddre= ssRuntimeCodePageNumber' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_RUNTIME_PAGE_SIZE_DATA_TYPE =3D 'UINT3= 2' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SMM_PAGE_SIZE =3D 'PcdLoadFixAddressSm= mCodePageNumber' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SMM_PAGE_SIZE_DATA_TYPE =3D 'UINT32' -TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SET =3D {TAB_PCDS_PATCHABLE_LOAD_FIX_= ADDRESS_PEI_PAGE_SIZE, \ - TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_DXE_PAGE_SIZE, \ - TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_RUNTIME_PAGE_SIZE, \ - TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_SMM_PAGE_SIZE} - -## The mapping dictionary from datum type to its maximum number. -MAX_VAL_TYPE =3D {"BOOLEAN":0x01, TAB_UINT8:0xFF, TAB_UINT16:0xFFFF, TAB_U= INT32:0xFFFFFFFF, TAB_UINT64:0xFFFFFFFFFFFFFFFF} -## The mapping dictionary from datum type to size string. -MAX_SIZE_TYPE =3D {"BOOLEAN":1, TAB_UINT8:1, TAB_UINT16:2, TAB_UINT32:4, T= AB_UINT64:8} - -TAB_DEPEX =3D 'Depex' -TAB_DEPEX_COMMON =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_COMMON -TAB_DEPEX_IA32 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IA32 -TAB_DEPEX_X64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64 -TAB_DEPEX_ARM =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM -TAB_DEPEX_EBC =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC -TAB_DEPEX_AARCH64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_SKUIDS =3D 'SkuIds' -TAB_DEFAULT_STORES =3D 'DefaultStores' -TAB_DEFAULT_STORES_DEFAULT =3D 'STANDARD' - -TAB_LIBRARIES =3D 'Libraries' -TAB_LIBRARIES_COMMON =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_COMMON -TAB_LIBRARIES_IA32 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IA32 -TAB_LIBRARIES_X64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64 -TAB_LIBRARIES_ARM =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM -TAB_LIBRARIES_EBC =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC -TAB_LIBRARIES_AARCH64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_COMPONENTS =3D 'Components' -TAB_COMPONENTS_COMMON =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON -TAB_COMPONENTS_IA32 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IA32 -TAB_COMPONENTS_X64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64 -TAB_COMPONENTS_ARM =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM -TAB_COMPONENTS_EBC =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC -TAB_COMPONENTS_AARCH64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64 - -TAB_BUILD_OPTIONS =3D 'BuildOptions' - -TAB_DEFINE =3D 'DEFINE' -TAB_NMAKE =3D 'Nmake' -TAB_USER_EXTENSIONS =3D 'UserExtensions' -TAB_INCLUDE =3D '!include' -TAB_DEFAULT =3D 'DEFAULT' -TAB_COMMON =3D 'COMMON' - -# -# Common Define -# -TAB_COMMON_DEFINES =3D 'Defines' - -# -# Inf Definitions -# -TAB_INF_DEFINES =3D TAB_COMMON_DEFINES -TAB_INF_DEFINES_INF_VERSION =3D 'INF_VERSION' -TAB_INF_DEFINES_BASE_NAME =3D 'BASE_NAME' -TAB_INF_DEFINES_FILE_GUID =3D 'FILE_GUID' -TAB_INF_DEFINES_MODULE_TYPE =3D 'MODULE_TYPE' -TAB_INF_DEFINES_EFI_SPECIFICATION_VERSION =3D 'EFI_SPECIFICATION_VERSION' -TAB_INF_DEFINES_UEFI_SPECIFICATION_VERSION =3D 'UEFI_SPECIFICATION_VERSION' -TAB_INF_DEFINES_PI_SPECIFICATION_VERSION =3D 'PI_SPECIFICATION_VERSION' -TAB_INF_DEFINES_EDK_RELEASE_VERSION =3D 'EDK_RELEASE_VERSION' -TAB_INF_DEFINES_BINARY_MODULE =3D 'BINARY_MODULE' -TAB_INF_DEFINES_LIBRARY_CLASS =3D 'LIBRARY_CLASS' -TAB_INF_DEFINES_COMPONENT_TYPE =3D 'COMPONENT_TYPE' -TAB_INF_DEFINES_MAKEFILE_NAME =3D 'MAKEFILE_NAME' -TAB_INF_DEFINES_DPX_SOURCE =3D 'DPX_SOURCE' -TAB_INF_DEFINES_BUILD_NUMBER =3D 'BUILD_NUMBER' -TAB_INF_DEFINES_BUILD_TYPE =3D 'BUILD_TYPE' -TAB_INF_DEFINES_FFS_EXT =3D 'FFS_EXT' -TAB_INF_DEFINES_FV_EXT =3D 'FV_EXT' -TAB_INF_DEFINES_SOURCE_FV =3D 'SOURCE_FV' -TAB_INF_DEFINES_VERSION_NUMBER =3D 'VERSION_NUMBER' -TAB_INF_DEFINES_VERSION =3D 'VERSION' # for Edk inf, the same as = VERSION_NUMBER -TAB_INF_DEFINES_VERSION_STRING =3D 'VERSION_STRING' -TAB_INF_DEFINES_PCD_IS_DRIVER =3D 'PCD_IS_DRIVER' -TAB_INF_DEFINES_TIANO_EDK_FLASHMAP_H =3D 'TIANO_EDK_FLASHMAP_H' -TAB_INF_DEFINES_ENTRY_POINT =3D 'ENTRY_POINT' -TAB_INF_DEFINES_UNLOAD_IMAGE =3D 'UNLOAD_IMAGE' -TAB_INF_DEFINES_CONSTRUCTOR =3D 'CONSTRUCTOR' -TAB_INF_DEFINES_DESTRUCTOR =3D 'DESTRUCTOR' -TAB_INF_DEFINES_DEFINE =3D 'DEFINE' -TAB_INF_DEFINES_SPEC =3D 'SPEC' -TAB_INF_DEFINES_CUSTOM_MAKEFILE =3D 'CUSTOM_MAKEFILE' -TAB_INF_DEFINES_MACRO =3D '__MACROS__' -TAB_INF_DEFINES_SHADOW =3D 'SHADOW' -TAB_INF_FIXED_PCD =3D 'FixedPcd' -TAB_INF_FEATURE_PCD =3D 'FeaturePcd' -TAB_INF_PATCH_PCD =3D 'PatchPcd' -TAB_INF_PCD =3D 'Pcd' -TAB_INF_PCD_EX =3D 'PcdEx' -TAB_INF_USAGE_PRO =3D 'PRODUCES' -TAB_INF_USAGE_SOME_PRO =3D 'SOMETIMES_PRODUCES' -TAB_INF_USAGE_CON =3D 'CONSUMES' -TAB_INF_USAGE_SOME_CON =3D 'SOMETIMES_CONSUMES' -TAB_INF_USAGE_NOTIFY =3D 'NOTIFY' -TAB_INF_USAGE_TO_START =3D 'TO_START' -TAB_INF_USAGE_BY_START =3D 'BY_START' -TAB_INF_GUIDTYPE_EVENT =3D 'Event' -TAB_INF_GUIDTYPE_FILE =3D 'File' -TAB_INF_GUIDTYPE_FV =3D 'FV' -TAB_INF_GUIDTYPE_GUID =3D 'GUID' -TAB_INF_GUIDTYPE_HII =3D 'HII' -TAB_INF_GUIDTYPE_HOB =3D 'HOB' -TAB_INF_GUIDTYPE_ST =3D 'SystemTable' -TAB_INF_GUIDTYPE_TSG =3D 'TokenSpaceGuid' -TAB_INF_GUIDTYPE_VAR =3D 'Variable' -TAB_INF_GUIDTYPE_PROTOCOL =3D 'PROTOCOL' -TAB_INF_GUIDTYPE_PPI =3D 'PPI' -TAB_INF_USAGE_UNDEFINED =3D 'UNDEFINED' - -# -# Dec Definitions -# -TAB_DEC_DEFINES =3D TAB_COMMON_DEFINES -TAB_DEC_DEFINES_DEC_SPECIFICATION =3D 'DEC_SPECIFICATION' -TAB_DEC_DEFINES_PACKAGE_NAME =3D 'PACKAGE_NAME' -TAB_DEC_DEFINES_PACKAGE_GUID =3D 'PACKAGE_GUID' -TAB_DEC_DEFINES_PACKAGE_VERSION =3D 'PACKAGE_VERSION' -TAB_DEC_DEFINES_PKG_UNI_FILE =3D 'PKG_UNI_FILE' - -# -# Dsc Definitions -# -TAB_DSC_DEFINES =3D TAB_COMMON_DEFINES -TAB_DSC_DEFINES_PLATFORM_NAME =3D 'PLATFORM_NAME' -TAB_DSC_DEFINES_PLATFORM_GUID =3D 'PLATFORM_GUID' -TAB_DSC_DEFINES_PLATFORM_VERSION =3D 'PLATFORM_VERSION' -TAB_DSC_DEFINES_DSC_SPECIFICATION =3D 'DSC_SPECIFICATION' -TAB_DSC_DEFINES_OUTPUT_DIRECTORY =3D 'OUTPUT_DIRECTORY' -TAB_DSC_DEFINES_SUPPORTED_ARCHITECTURES =3D 'SUPPORTED_ARCHITECTURES' -TAB_DSC_DEFINES_BUILD_TARGETS =3D 'BUILD_TARGETS' -TAB_DSC_DEFINES_SKUID_IDENTIFIER =3D 'SKUID_IDENTIFIER' -TAB_DSC_DEFINES_PCD_INFO_GENERATION =3D 'PCD_INFO_GENERATION' -TAB_DSC_DEFINES_PCD_VAR_CHECK_GENERATION =3D 'PCD_VAR_CHECK_GENERATION' -TAB_DSC_DEFINES_FLASH_DEFINITION =3D 'FLASH_DEFINITION' -TAB_DSC_DEFINES_BUILD_NUMBER =3D 'BUILD_NUMBER' -TAB_DSC_DEFINES_MAKEFILE_NAME =3D 'MAKEFILE_NAME' -TAB_DSC_DEFINES_BS_BASE_ADDRESS =3D 'BsBaseAddress' -TAB_DSC_DEFINES_RT_BASE_ADDRESS =3D 'RtBaseAddress' -TAB_DSC_DEFINES_RFC_LANGUAGES =3D 'RFC_LANGUAGES' -TAB_DSC_DEFINES_ISO_LANGUAGES =3D 'ISO_LANGUAGES' -TAB_DSC_DEFINES_DEFINE =3D 'DEFINE' -TAB_DSC_DEFINES_VPD_TOOL_GUID =3D 'VPD_TOOL_GUID' -TAB_FIX_LOAD_TOP_MEMORY_ADDRESS =3D 'FIX_LOAD_TOP_MEMORY_ADDRESS' -TAB_DSC_DEFINES_EDKGLOBAL =3D 'EDK_GLOBAL' -TAB_DSC_PREBUILD =3D 'PREBUILD' -TAB_DSC_POSTBUILD =3D 'POSTBUILD' -# -# TargetTxt Definitions -# -TAB_TAT_DEFINES_ACTIVE_PLATFORM =3D 'ACTIVE_PLATFORM' -TAB_TAT_DEFINES_ACTIVE_MODULE =3D 'ACTIVE_MODULE' -TAB_TAT_DEFINES_TOOL_CHAIN_CONF =3D 'TOOL_CHAIN_CONF' -TAB_TAT_DEFINES_MAX_CONCURRENT_THREAD_NUMBER =3D 'MAX_CONCURRENT_THREAD_NU= MBER' -TAB_TAT_DEFINES_TARGET =3D 'TARGET' -TAB_TAT_DEFINES_TOOL_CHAIN_TAG =3D 'TOOL_CHAIN_TAG' -TAB_TAT_DEFINES_TARGET_ARCH =3D 'TARGET_ARCH' -TAB_TAT_DEFINES_BUILD_RULE_CONF =3D "BUILD_RULE_CONF" - -# -# ToolDef Definitions -# -TAB_TOD_DEFINES_TARGET =3D 'TARGET' -TAB_TOD_DEFINES_TOOL_CHAIN_TAG =3D 'TOOL_CHAIN_TAG' -TAB_TOD_DEFINES_TARGET_ARCH =3D 'TARGET_ARCH' -TAB_TOD_DEFINES_COMMAND_TYPE =3D 'COMMAND_TYPE' -TAB_TOD_DEFINES_FAMILY =3D 'FAMILY' -TAB_TOD_DEFINES_BUILDRULEFAMILY =3D 'BUILDRULEFAMILY' -TAB_TOD_DEFINES_BUILDRULEORDER =3D 'BUILDRULEORDER' - -# -# Conditional Statements -# -TAB_IF =3D '!if' -TAB_END_IF =3D '!endif' -TAB_ELSE_IF =3D '!elseif' -TAB_ELSE =3D '!else' -TAB_IF_DEF =3D '!ifdef' -TAB_IF_N_DEF =3D '!ifndef' -TAB_IF_EXIST =3D '!if exist' -TAB_ERROR =3D '!error' - -# -# Unknown section -# -TAB_UNKNOWN =3D 'UNKNOWN' - -# -# Build database path -# -DATABASE_PATH =3D ":memory:" #"BuildDatabase.db" - -# used by ECC -MODIFIER_SET =3D {'IN', 'OUT', 'OPTIONAL', 'UNALIGNED', 'EFI_RUNTIMESERVIC= E', 'EFI_BOOTSERVICE', 'EFIAPI'} - -# Dependency Opcodes -DEPEX_OPCODE_BEFORE =3D "BEFORE" -DEPEX_OPCODE_AFTER =3D "AFTER" -DEPEX_OPCODE_PUSH =3D "PUSH" -DEPEX_OPCODE_AND =3D "AND" -DEPEX_OPCODE_OR =3D "OR" -DEPEX_OPCODE_NOT =3D "NOT" -DEPEX_OPCODE_END =3D "END" -DEPEX_OPCODE_SOR =3D "SOR" -DEPEX_OPCODE_TRUE =3D "TRUE" -DEPEX_OPCODE_FALSE =3D "FALSE" - -# Dependency Expression -DEPEX_SUPPORTED_OPCODE_SET =3D {"BEFORE", "AFTER", "PUSH", "AND", "OR", "N= OT", "END", "SOR", "TRUE", "FALSE", '(', ')'} - -TAB_STATIC_LIBRARY =3D "STATIC-LIBRARY-FILE" -TAB_DYNAMIC_LIBRARY =3D "DYNAMIC-LIBRARY-FILE" -TAB_FRAMEWORK_IMAGE =3D "EFI-IMAGE-FILE" -TAB_C_CODE_FILE =3D "C-CODE-FILE" -TAB_C_HEADER_FILE =3D "C-HEADER-FILE" -TAB_UNICODE_FILE =3D "UNICODE-TEXT-FILE" -TAB_IMAGE_FILE =3D "IMAGE-DEFINITION-FILE" -TAB_DEPENDENCY_EXPRESSION_FILE =3D "DEPENDENCY-EXPRESSION-FILE" -TAB_UNKNOWN_FILE =3D "UNKNOWN-TYPE-FILE" -TAB_DEFAULT_BINARY_FILE =3D "_BINARY_FILE_" -TAB_OBJECT_FILE =3D "OBJECT-FILE" -TAB_VFR_FILE =3D 'VISUAL-FORM-REPRESENTATION-FILE' - -# used by BRG -TAB_BRG_PCD =3D 'PCD' -TAB_BRG_LIBRARY =3D 'Library' - -# -# Build Rule File Version Definition -# -TAB_BUILD_RULE_VERSION =3D "build_rule_version" - -# section name for PCDs -PCDS_DYNAMIC_DEFAULT =3D "PcdsDynamicDefault" -PCDS_DYNAMIC_VPD =3D "PcdsDynamicVpd" -PCDS_DYNAMIC_HII =3D "PcdsDynamicHii" -PCDS_DYNAMICEX_DEFAULT =3D "PcdsDynamicExDefault" -PCDS_DYNAMICEX_VPD =3D "PcdsDynamicExVpd" -PCDS_DYNAMICEX_HII =3D "PcdsDynamicExHii" - -SECTIONS_HAVE_ITEM_PCD_SET =3D {PCDS_DYNAMIC_DEFAULT.upper(), PCDS_DYNAMIC= _VPD.upper(), PCDS_DYNAMIC_HII.upper(), \ - PCDS_DYNAMICEX_DEFAULT.upper(), PCDS_DYNAMIC= EX_VPD.upper(), PCDS_DYNAMICEX_HII.upper()} -# Section allowed to have items after arch -SECTIONS_HAVE_ITEM_AFTER_ARCH_SET =3D {TAB_LIBRARY_CLASSES.upper(), TAB_DE= PEX.upper(), TAB_USER_EXTENSIONS.upper(), - PCDS_DYNAMIC_DEFAULT.upper(), - PCDS_DYNAMIC_VPD.upper(), - PCDS_DYNAMIC_HII.upper(), - PCDS_DYNAMICEX_DEFAULT.upper(), - PCDS_DYNAMICEX_VPD.upper(), - PCDS_DYNAMICEX_HII.upper(), - TAB_BUILD_OPTIONS.upper(), - TAB_INCLUDES.upper()} - -# -# pack codes as used in PcdDb and elsewhere -# -PACK_PATTERN_GUID =3D '=3DLHHBBBBBBBB' -PACK_CODE_BY_SIZE =3D {8:'=3DQ', - 4:'=3DL', - 2:'=3DH', - 1:'=3DB', - 0:'=3DB', - 16:""} - -TAB_COMPILER_MSFT =3D 'MSFT' \ No newline at end of file +## @file +# This file is used to define common static strings used by INF/DEC/DSC fi= les +# +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. = All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent + +## +# Common Definitions +# +TAB_SPLIT =3D '.' +TAB_COMMENT_EDK_START =3D '/*' +TAB_COMMENT_EDK_END =3D '*/' +TAB_COMMENT_EDK_SPLIT =3D '//' +TAB_COMMENT_SPLIT =3D '#' +TAB_SPECIAL_COMMENT =3D '##' +TAB_EQUAL_SPLIT =3D '=3D' +TAB_VALUE_SPLIT =3D '|' +TAB_COMMA_SPLIT =3D ',' +TAB_SPACE_SPLIT =3D ' ' +TAB_SEMI_COLON_SPLIT =3D ';' +TAB_SECTION_START =3D '[' +TAB_SECTION_END =3D ']' +TAB_OPTION_START =3D '<' +TAB_OPTION_END =3D '>' +TAB_SLASH =3D '\\' +TAB_BACK_SLASH =3D '/' +TAB_STAR =3D '*' +TAB_LINE_BREAK =3D '\n' +TAB_PRINTCHAR_VT =3D '\x0b' +TAB_PRINTCHAR_BS =3D '\b' +TAB_PRINTCHAR_NUL =3D '\0' +TAB_UINT8 =3D 'UINT8' +TAB_UINT16 =3D 'UINT16' +TAB_UINT32 =3D 'UINT32' +TAB_UINT64 =3D 'UINT64' +TAB_VOID =3D 'VOID*' +TAB_GUID =3D 'GUID' + +TAB_PCD_CLEAN_NUMERIC_TYPES =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UI= NT64} +TAB_PCD_NUMERIC_TYPES =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UINT64, = 'BOOLEAN'} +TAB_PCD_NUMERIC_TYPES_VOID =3D {TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UIN= T64, 'BOOLEAN', TAB_VOID} + +TAB_WORKSPACE =3D '$(WORKSPACE)' +TAB_FV_DIRECTORY =3D 'FV' + +TAB_ARCH_NULL =3D '' +TAB_ARCH_COMMON =3D 'COMMON' +TAB_ARCH_IA32 =3D 'IA32' +TAB_ARCH_X64 =3D 'X64' +TAB_ARCH_ARM =3D 'ARM' +TAB_ARCH_EBC =3D 'EBC' +TAB_ARCH_AARCH64 =3D 'AARCH64' + +TAB_ARCH_RISCV32 =3D 'RISCV32' +TAB_ARCH_RISCV64 =3D 'RISCV64' +TAB_ARCH_RISCV128 =3D 'RISCV128' + +ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_RISCV32, TAB_ARCH_RISCV64, TAB_ARCH_RISCV128, = TAB_ARCH_COMMON} + +SUP_MODULE_BASE =3D 'BASE' +SUP_MODULE_SEC =3D 'SEC' +SUP_MODULE_PEI_CORE =3D 'PEI_CORE' +SUP_MODULE_PEIM =3D 'PEIM' +SUP_MODULE_DXE_CORE =3D 'DXE_CORE' +SUP_MODULE_DXE_DRIVER =3D 'DXE_DRIVER' +SUP_MODULE_DXE_RUNTIME_DRIVER =3D 'DXE_RUNTIME_DRIVER' +SUP_MODULE_DXE_SAL_DRIVER =3D 'DXE_SAL_DRIVER' +SUP_MODULE_DXE_SMM_DRIVER =3D 'DXE_SMM_DRIVER' +SUP_MODULE_UEFI_DRIVER =3D 'UEFI_DRIVER' +SUP_MODULE_UEFI_APPLICATION =3D 'UEFI_APPLICATION' +SUP_MODULE_USER_DEFINED =3D 'USER_DEFINED' +SUP_MODULE_HOST_APPLICATION =3D 'HOST_APPLICATION' +SUP_MODULE_SMM_CORE =3D 'SMM_CORE' +SUP_MODULE_MM_STANDALONE =3D 'MM_STANDALONE' +SUP_MODULE_MM_CORE_STANDALONE =3D 'MM_CORE_STANDALONE' + +SUP_MODULE_LIST =3D [SUP_MODULE_BASE, SUP_MODULE_SEC, SUP_MODULE_PEI_CORE,= SUP_MODULE_PEIM, SUP_MODULE_DXE_CORE, SUP_MODULE_DXE_DRIVER, \ + SUP_MODULE_DXE_RUNTIME_DRIVER, SUP_MODULE_DXE_SAL_DRIVE= R, SUP_MODULE_DXE_SMM_DRIVER, SUP_MODULE_UEFI_DRIVER, \ + SUP_MODULE_UEFI_APPLICATION, SUP_MODULE_USER_DEFINED, S= UP_MODULE_HOST_APPLICATION, SUP_MODULE_SMM_CORE, SUP_MODULE_MM_STANDALONE, = SUP_MODULE_MM_CORE_STANDALONE] +SUP_MODULE_LIST_STRING =3D TAB_VALUE_SPLIT.join(SUP_MODULE_LIST) +SUP_MODULE_SET_PEI =3D {SUP_MODULE_PEIM, SUP_MODULE_PEI_CORE} + +EDK_COMPONENT_TYPE_LIBRARY =3D 'LIBRARY' +EDK_COMPONENT_TYPE_SECURITY_CORE =3D 'SECURITY_CORE' +EDK_COMPONENT_TYPE_PEI_CORE =3D SUP_MODULE_PEI_CORE +EDK_COMPONENT_TYPE_COMBINED_PEIM_DRIVER =3D 'COMBINED_PEIM_DRIVER' +EDK_COMPONENT_TYPE_PIC_PEIM =3D 'PIC_PEIM' +EDK_COMPONENT_TYPE_RELOCATABLE_PEIM =3D 'RELOCATABLE_PEIM' +EDK_COMPONENT_TYPE_BS_DRIVER =3D 'BS_DRIVER' +EDK_COMPONENT_TYPE_RT_DRIVER =3D 'RT_DRIVER' +EDK_COMPONENT_TYPE_SAL_RT_DRIVER =3D 'SAL_RT_DRIVER' +EDK_COMPONENT_TYPE_APPLICATION =3D 'APPLICATION' +EDK_NAME =3D 'EDK' +EDKII_NAME =3D 'EDKII' +MSG_EDKII_MAIL_ADDR =3D 'devel@edk2.groups.io' + +COMPONENT_TO_MODULE_MAP_DICT =3D { + EDK_COMPONENT_TYPE_LIBRARY : SUP_MODULE_BASE, + EDK_COMPONENT_TYPE_SECURITY_CORE : SUP_MODULE_SEC, + EDK_COMPONENT_TYPE_PEI_CORE : SUP_MODULE_PEI_CORE, + EDK_COMPONENT_TYPE_COMBINED_PEIM_DRIVER : SUP_MODULE_PEIM, + EDK_COMPONENT_TYPE_PIC_PEIM : SUP_MODULE_PEIM, + EDK_COMPONENT_TYPE_RELOCATABLE_PEIM : SUP_MODULE_PEIM, + "PE32_PEIM" : SUP_MODULE_PEIM, + EDK_COMPONENT_TYPE_BS_DRIVER : SUP_MODULE_DXE_DRIVER, + EDK_COMPONENT_TYPE_RT_DRIVER : SUP_MODULE_DXE_RUNTIME_DR= IVER, + EDK_COMPONENT_TYPE_SAL_RT_DRIVER : SUP_MODULE_DXE_SAL_DRIVER, + EDK_COMPONENT_TYPE_APPLICATION : SUP_MODULE_UEFI_APPLICATI= ON, + "LOGO" : SUP_MODULE_BASE, +} + +BINARY_FILE_TYPE_FW =3D 'FW' +BINARY_FILE_TYPE_GUID =3D 'GUID' +BINARY_FILE_TYPE_PREEFORM =3D 'PREEFORM' +BINARY_FILE_TYPE_UEFI_APP =3D 'UEFI_APP' +BINARY_FILE_TYPE_UNI_UI =3D 'UNI_UI' +BINARY_FILE_TYPE_UNI_VER =3D 'UNI_VER' +BINARY_FILE_TYPE_LIB =3D 'LIB' +BINARY_FILE_TYPE_PE32 =3D 'PE32' +BINARY_FILE_TYPE_PIC =3D 'PIC' +BINARY_FILE_TYPE_PEI_DEPEX =3D 'PEI_DEPEX' +BINARY_FILE_TYPE_DXE_DEPEX =3D 'DXE_DEPEX' +BINARY_FILE_TYPE_SMM_DEPEX =3D 'SMM_DEPEX' +BINARY_FILE_TYPE_TE =3D 'TE' +BINARY_FILE_TYPE_VER =3D 'VER' +BINARY_FILE_TYPE_UI =3D 'UI' +BINARY_FILE_TYPE_BIN =3D 'BIN' +BINARY_FILE_TYPE_FV =3D 'FV' +BINARY_FILE_TYPE_RAW =3D 'RAW_BINARY' + +PLATFORM_COMPONENT_TYPE_LIBRARY_CLASS =3D 'LIBRARY_CLASS' +PLATFORM_COMPONENT_TYPE_MODULE =3D 'MODULE' + +TAB_SOURCES =3D 'Sources' +TAB_SOURCES_COMMON =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_COMMON +TAB_SOURCES_IA32 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IA32 +TAB_SOURCES_X64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64 +TAB_SOURCES_ARM =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM +TAB_SOURCES_EBC =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC +TAB_SOURCES_AARCH64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_BINARIES =3D 'Binaries' +TAB_BINARIES_COMMON =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON +TAB_BINARIES_IA32 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IA32 +TAB_BINARIES_X64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64 +TAB_BINARIES_ARM =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM +TAB_BINARIES_EBC =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC +TAB_BINARIES_AARCH64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_INCLUDES =3D 'Includes' +TAB_INCLUDES_COMMON =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON +TAB_INCLUDES_IA32 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IA32 +TAB_INCLUDES_X64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64 +TAB_INCLUDES_ARM =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM +TAB_INCLUDES_EBC =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC +TAB_INCLUDES_AARCH64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_GUIDS =3D 'Guids' +TAB_GUIDS_COMMON =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON +TAB_GUIDS_IA32 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IA32 +TAB_GUIDS_X64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64 +TAB_GUIDS_ARM =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM +TAB_GUIDS_EBC =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC +TAB_GUIDS_AARCH64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_PROTOCOLS =3D 'Protocols' +TAB_PROTOCOLS_COMMON =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON +TAB_PROTOCOLS_IA32 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IA32 +TAB_PROTOCOLS_X64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64 +TAB_PROTOCOLS_ARM =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM +TAB_PROTOCOLS_EBC =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC +TAB_PROTOCOLS_AARCH64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_PPIS =3D 'Ppis' +TAB_PPIS_COMMON =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON +TAB_PPIS_IA32 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_IA32 +TAB_PPIS_X64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64 +TAB_PPIS_ARM =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM +TAB_PPIS_EBC =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC +TAB_PPIS_AARCH64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_LIBRARY_CLASSES =3D 'LibraryClasses' +TAB_LIBRARY_CLASSES_COMMON =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_= COMMON +TAB_LIBRARY_CLASSES_IA32 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IA= 32 +TAB_LIBRARY_CLASSES_X64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64 +TAB_LIBRARY_CLASSES_ARM =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM +TAB_LIBRARY_CLASSES_EBC =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC +TAB_LIBRARY_CLASSES_AARCH64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH= _AARCH64 + +TAB_PACKAGES =3D 'Packages' +TAB_PACKAGES_COMMON =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON +TAB_PACKAGES_IA32 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IA32 +TAB_PACKAGES_X64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64 +TAB_PACKAGES_ARM =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM +TAB_PACKAGES_EBC =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC +TAB_PACKAGES_AARCH64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_PCDS =3D 'Pcds' +TAB_PCDS_FIXED_AT_BUILD =3D 'FixedAtBuild' +TAB_PCDS_PATCHABLE_IN_MODULE =3D 'PatchableInModule' +TAB_PCDS_FEATURE_FLAG =3D 'FeatureFlag' +TAB_PCDS_DYNAMIC_EX =3D 'DynamicEx' +TAB_PCDS_DYNAMIC_EX_DEFAULT =3D 'DynamicExDefault' +TAB_PCDS_DYNAMIC_EX_VPD =3D 'DynamicExVpd' +TAB_PCDS_DYNAMIC_EX_HII =3D 'DynamicExHii' +TAB_PCDS_DYNAMIC =3D 'Dynamic' +TAB_PCDS_DYNAMIC_DEFAULT =3D 'DynamicDefault' +TAB_PCDS_DYNAMIC_VPD =3D 'DynamicVpd' +TAB_PCDS_DYNAMIC_HII =3D 'DynamicHii' + +PCD_DYNAMIC_TYPE_SET =3D {TAB_PCDS_DYNAMIC, TAB_PCDS_DYNAMIC_DEFAULT, TAB_= PCDS_DYNAMIC_VPD, TAB_PCDS_DYNAMIC_HII} +PCD_DYNAMIC_EX_TYPE_SET =3D {TAB_PCDS_DYNAMIC_EX, TAB_PCDS_DYNAMIC_EX_DEFA= ULT, TAB_PCDS_DYNAMIC_EX_VPD, TAB_PCDS_DYNAMIC_EX_HII} + +# leave as a list for order +PCD_TYPE_LIST =3D [TAB_PCDS_FIXED_AT_BUILD, TAB_PCDS_PATCHABLE_IN_MODULE, = TAB_PCDS_FEATURE_FLAG, TAB_PCDS_DYNAMIC, TAB_PCDS_DYNAMIC_EX] + +TAB_PCDS_FIXED_AT_BUILD_NULL =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD +TAB_PCDS_FIXED_AT_BUILD_COMMON =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TA= B_SPLIT + TAB_ARCH_COMMON +TAB_PCDS_FIXED_AT_BUILD_IA32 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_= SPLIT + TAB_ARCH_IA32 +TAB_PCDS_FIXED_AT_BUILD_X64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_X64 +TAB_PCDS_FIXED_AT_BUILD_ARM =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_ARM +TAB_PCDS_FIXED_AT_BUILD_EBC =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S= PLIT + TAB_ARCH_EBC +TAB_PCDS_FIXED_AT_BUILD_AARCH64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + T= AB_SPLIT + TAB_ARCH_AARCH64 + +TAB_PCDS_PATCHABLE_IN_MODULE_NULL =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MOD= ULE +TAB_PCDS_PATCHABLE_IN_MODULE_COMMON =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_M= ODULE + TAB_SPLIT + TAB_ARCH_COMMON +TAB_PCDS_PATCHABLE_IN_MODULE_IA32 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MOD= ULE + TAB_SPLIT + TAB_ARCH_IA32 +TAB_PCDS_PATCHABLE_IN_MODULE_X64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_X64 +TAB_PCDS_PATCHABLE_IN_MODULE_ARM =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_ARM +TAB_PCDS_PATCHABLE_IN_MODULE_EBC =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU= LE + TAB_SPLIT + TAB_ARCH_EBC +TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_= MODULE + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_PCDS_FEATURE_FLAG_NULL =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG +TAB_PCDS_FEATURE_FLAG_COMMON =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SP= LIT + TAB_ARCH_COMMON +TAB_PCDS_FEATURE_FLAG_IA32 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLI= T + TAB_ARCH_IA32 +TAB_PCDS_FEATURE_FLAG_X64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_X64 +TAB_PCDS_FEATURE_FLAG_ARM =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_ARM +TAB_PCDS_FEATURE_FLAG_EBC =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT= + TAB_ARCH_EBC +TAB_PCDS_FEATURE_FLAG_AARCH64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_S= PLIT + TAB_ARCH_AARCH64 + +TAB_PCDS_DYNAMIC_EX_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX +TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAULT +TAB_PCDS_DYNAMIC_EX_HII_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_HII +TAB_PCDS_DYNAMIC_EX_VPD_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_VPD +TAB_PCDS_DYNAMIC_EX_COMMON =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT = + TAB_ARCH_COMMON +TAB_PCDS_DYNAMIC_EX_IA32 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + = TAB_ARCH_IA32 +TAB_PCDS_DYNAMIC_EX_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_X64 +TAB_PCDS_DYNAMIC_EX_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_ARM +TAB_PCDS_DYNAMIC_EX_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T= AB_ARCH_EBC +TAB_PCDS_DYNAMIC_EX_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT= + TAB_ARCH_AARCH64 + +TAB_PCDS_DYNAMIC_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC +TAB_PCDS_DYNAMIC_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT +TAB_PCDS_DYNAMIC_HII_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_HII +TAB_PCDS_DYNAMIC_VPD_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_VPD +TAB_PCDS_DYNAMIC_COMMON =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_= ARCH_COMMON +TAB_PCDS_DYNAMIC_IA32 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_AR= CH_IA32 +TAB_PCDS_DYNAMIC_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_X64 +TAB_PCDS_DYNAMIC_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_ARM +TAB_PCDS_DYNAMIC_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC= H_EBC +TAB_PCDS_DYNAMIC_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB= _ARCH_AARCH64 + +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE =3D 'PcdLoadFixAddressPe= iCodePageNumber' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE_DATA_TYPE =3D 'UINT32' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_DXE_PAGE_SIZE =3D 'PcdLoadFixAddressBo= otTimeCodePageNumber' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_DXE_PAGE_SIZE_DATA_TYPE =3D 'UINT32' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_RUNTIME_PAGE_SIZE =3D 'PcdLoadFixAddre= ssRuntimeCodePageNumber' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_RUNTIME_PAGE_SIZE_DATA_TYPE =3D 'UINT3= 2' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SMM_PAGE_SIZE =3D 'PcdLoadFixAddressSm= mCodePageNumber' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SMM_PAGE_SIZE_DATA_TYPE =3D 'UINT32' +TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_SET =3D {TAB_PCDS_PATCHABLE_LOAD_FIX_= ADDRESS_PEI_PAGE_SIZE, \ + TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_DXE_PAGE_SIZE, \ + TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_RUNTIME_PAGE_SIZE, \ + TAB_PCDS_PATCHABLE_LOAD_FIX_AD= DRESS_SMM_PAGE_SIZE} + +## The mapping dictionary from datum type to its maximum number. +MAX_VAL_TYPE =3D {"BOOLEAN":0x01, TAB_UINT8:0xFF, TAB_UINT16:0xFFFF, TAB_U= INT32:0xFFFFFFFF, TAB_UINT64:0xFFFFFFFFFFFFFFFF} +## The mapping dictionary from datum type to size string. +MAX_SIZE_TYPE =3D {"BOOLEAN":1, TAB_UINT8:1, TAB_UINT16:2, TAB_UINT32:4, T= AB_UINT64:8} + +TAB_DEPEX =3D 'Depex' +TAB_DEPEX_COMMON =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_COMMON +TAB_DEPEX_IA32 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IA32 +TAB_DEPEX_X64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64 +TAB_DEPEX_ARM =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM +TAB_DEPEX_EBC =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC +TAB_DEPEX_AARCH64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_SKUIDS =3D 'SkuIds' +TAB_DEFAULT_STORES =3D 'DefaultStores' +TAB_DEFAULT_STORES_DEFAULT =3D 'STANDARD' + +TAB_LIBRARIES =3D 'Libraries' +TAB_LIBRARIES_COMMON =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_COMMON +TAB_LIBRARIES_IA32 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IA32 +TAB_LIBRARIES_X64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64 +TAB_LIBRARIES_ARM =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM +TAB_LIBRARIES_EBC =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC +TAB_LIBRARIES_AARCH64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_COMPONENTS =3D 'Components' +TAB_COMPONENTS_COMMON =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON +TAB_COMPONENTS_IA32 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IA32 +TAB_COMPONENTS_X64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64 +TAB_COMPONENTS_ARM =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM +TAB_COMPONENTS_EBC =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC +TAB_COMPONENTS_AARCH64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64 + +TAB_BUILD_OPTIONS =3D 'BuildOptions' + +TAB_DEFINE =3D 'DEFINE' +TAB_NMAKE =3D 'Nmake' +TAB_USER_EXTENSIONS =3D 'UserExtensions' +TAB_INCLUDE =3D '!include' +TAB_DEFAULT =3D 'DEFAULT' +TAB_COMMON =3D 'COMMON' + +# +# Common Define +# +TAB_COMMON_DEFINES =3D 'Defines' + +# +# Inf Definitions +# +TAB_INF_DEFINES =3D TAB_COMMON_DEFINES +TAB_INF_DEFINES_INF_VERSION =3D 'INF_VERSION' +TAB_INF_DEFINES_BASE_NAME =3D 'BASE_NAME' +TAB_INF_DEFINES_FILE_GUID =3D 'FILE_GUID' +TAB_INF_DEFINES_MODULE_TYPE =3D 'MODULE_TYPE' +TAB_INF_DEFINES_EFI_SPECIFICATION_VERSION =3D 'EFI_SPECIFICATION_VERSION' +TAB_INF_DEFINES_UEFI_SPECIFICATION_VERSION =3D 'UEFI_SPECIFICATION_VERSION' +TAB_INF_DEFINES_PI_SPECIFICATION_VERSION =3D 'PI_SPECIFICATION_VERSION' +TAB_INF_DEFINES_EDK_RELEASE_VERSION =3D 'EDK_RELEASE_VERSION' +TAB_INF_DEFINES_BINARY_MODULE =3D 'BINARY_MODULE' +TAB_INF_DEFINES_LIBRARY_CLASS =3D 'LIBRARY_CLASS' +TAB_INF_DEFINES_COMPONENT_TYPE =3D 'COMPONENT_TYPE' +TAB_INF_DEFINES_MAKEFILE_NAME =3D 'MAKEFILE_NAME' +TAB_INF_DEFINES_DPX_SOURCE =3D 'DPX_SOURCE' +TAB_INF_DEFINES_BUILD_NUMBER =3D 'BUILD_NUMBER' +TAB_INF_DEFINES_BUILD_TYPE =3D 'BUILD_TYPE' +TAB_INF_DEFINES_FFS_EXT =3D 'FFS_EXT' +TAB_INF_DEFINES_FV_EXT =3D 'FV_EXT' +TAB_INF_DEFINES_SOURCE_FV =3D 'SOURCE_FV' +TAB_INF_DEFINES_VERSION_NUMBER =3D 'VERSION_NUMBER' +TAB_INF_DEFINES_VERSION =3D 'VERSION' # for Edk inf, the same as = VERSION_NUMBER +TAB_INF_DEFINES_VERSION_STRING =3D 'VERSION_STRING' +TAB_INF_DEFINES_PCD_IS_DRIVER =3D 'PCD_IS_DRIVER' +TAB_INF_DEFINES_TIANO_EDK_FLASHMAP_H =3D 'TIANO_EDK_FLASHMAP_H' +TAB_INF_DEFINES_ENTRY_POINT =3D 'ENTRY_POINT' +TAB_INF_DEFINES_UNLOAD_IMAGE =3D 'UNLOAD_IMAGE' +TAB_INF_DEFINES_CONSTRUCTOR =3D 'CONSTRUCTOR' +TAB_INF_DEFINES_DESTRUCTOR =3D 'DESTRUCTOR' +TAB_INF_DEFINES_DEFINE =3D 'DEFINE' +TAB_INF_DEFINES_SPEC =3D 'SPEC' +TAB_INF_DEFINES_CUSTOM_MAKEFILE =3D 'CUSTOM_MAKEFILE' +TAB_INF_DEFINES_MACRO =3D '__MACROS__' +TAB_INF_DEFINES_SHADOW =3D 'SHADOW' +TAB_INF_FIXED_PCD =3D 'FixedPcd' +TAB_INF_FEATURE_PCD =3D 'FeaturePcd' +TAB_INF_PATCH_PCD =3D 'PatchPcd' +TAB_INF_PCD =3D 'Pcd' +TAB_INF_PCD_EX =3D 'PcdEx' +TAB_INF_USAGE_PRO =3D 'PRODUCES' +TAB_INF_USAGE_SOME_PRO =3D 'SOMETIMES_PRODUCES' +TAB_INF_USAGE_CON =3D 'CONSUMES' +TAB_INF_USAGE_SOME_CON =3D 'SOMETIMES_CONSUMES' +TAB_INF_USAGE_NOTIFY =3D 'NOTIFY' +TAB_INF_USAGE_TO_START =3D 'TO_START' +TAB_INF_USAGE_BY_START =3D 'BY_START' +TAB_INF_GUIDTYPE_EVENT =3D 'Event' +TAB_INF_GUIDTYPE_FILE =3D 'File' +TAB_INF_GUIDTYPE_FV =3D 'FV' +TAB_INF_GUIDTYPE_GUID =3D 'GUID' +TAB_INF_GUIDTYPE_HII =3D 'HII' +TAB_INF_GUIDTYPE_HOB =3D 'HOB' +TAB_INF_GUIDTYPE_ST =3D 'SystemTable' +TAB_INF_GUIDTYPE_TSG =3D 'TokenSpaceGuid' +TAB_INF_GUIDTYPE_VAR =3D 'Variable' +TAB_INF_GUIDTYPE_PROTOCOL =3D 'PROTOCOL' +TAB_INF_GUIDTYPE_PPI =3D 'PPI' +TAB_INF_USAGE_UNDEFINED =3D 'UNDEFINED' + +# +# Dec Definitions +# +TAB_DEC_DEFINES =3D TAB_COMMON_DEFINES +TAB_DEC_DEFINES_DEC_SPECIFICATION =3D 'DEC_SPECIFICATION' +TAB_DEC_DEFINES_PACKAGE_NAME =3D 'PACKAGE_NAME' +TAB_DEC_DEFINES_PACKAGE_GUID =3D 'PACKAGE_GUID' +TAB_DEC_DEFINES_PACKAGE_VERSION =3D 'PACKAGE_VERSION' +TAB_DEC_DEFINES_PKG_UNI_FILE =3D 'PKG_UNI_FILE' + +# +# Dsc Definitions +# +TAB_DSC_DEFINES =3D TAB_COMMON_DEFINES +TAB_DSC_DEFINES_PLATFORM_NAME =3D 'PLATFORM_NAME' +TAB_DSC_DEFINES_PLATFORM_GUID =3D 'PLATFORM_GUID' +TAB_DSC_DEFINES_PLATFORM_VERSION =3D 'PLATFORM_VERSION' +TAB_DSC_DEFINES_DSC_SPECIFICATION =3D 'DSC_SPECIFICATION' +TAB_DSC_DEFINES_OUTPUT_DIRECTORY =3D 'OUTPUT_DIRECTORY' +TAB_DSC_DEFINES_SUPPORTED_ARCHITECTURES =3D 'SUPPORTED_ARCHITECTURES' +TAB_DSC_DEFINES_BUILD_TARGETS =3D 'BUILD_TARGETS' +TAB_DSC_DEFINES_SKUID_IDENTIFIER =3D 'SKUID_IDENTIFIER' +TAB_DSC_DEFINES_PCD_INFO_GENERATION =3D 'PCD_INFO_GENERATION' +TAB_DSC_DEFINES_PCD_VAR_CHECK_GENERATION =3D 'PCD_VAR_CHECK_GENERATION' +TAB_DSC_DEFINES_FLASH_DEFINITION =3D 'FLASH_DEFINITION' +TAB_DSC_DEFINES_BUILD_NUMBER =3D 'BUILD_NUMBER' +TAB_DSC_DEFINES_MAKEFILE_NAME =3D 'MAKEFILE_NAME' +TAB_DSC_DEFINES_BS_BASE_ADDRESS =3D 'BsBaseAddress' +TAB_DSC_DEFINES_RT_BASE_ADDRESS =3D 'RtBaseAddress' +TAB_DSC_DEFINES_RFC_LANGUAGES =3D 'RFC_LANGUAGES' +TAB_DSC_DEFINES_ISO_LANGUAGES =3D 'ISO_LANGUAGES' +TAB_DSC_DEFINES_DEFINE =3D 'DEFINE' +TAB_DSC_DEFINES_VPD_TOOL_GUID =3D 'VPD_TOOL_GUID' +TAB_FIX_LOAD_TOP_MEMORY_ADDRESS =3D 'FIX_LOAD_TOP_MEMORY_ADDRESS' +TAB_DSC_DEFINES_EDKGLOBAL =3D 'EDK_GLOBAL' +TAB_DSC_PREBUILD =3D 'PREBUILD' +TAB_DSC_POSTBUILD =3D 'POSTBUILD' +# +# TargetTxt Definitions +# +TAB_TAT_DEFINES_ACTIVE_PLATFORM =3D 'ACTIVE_PLATFORM' +TAB_TAT_DEFINES_ACTIVE_MODULE =3D 'ACTIVE_MODULE' +TAB_TAT_DEFINES_TOOL_CHAIN_CONF =3D 'TOOL_CHAIN_CONF' +TAB_TAT_DEFINES_MAX_CONCURRENT_THREAD_NUMBER =3D 'MAX_CONCURRENT_THREAD_NU= MBER' +TAB_TAT_DEFINES_TARGET =3D 'TARGET' +TAB_TAT_DEFINES_TOOL_CHAIN_TAG =3D 'TOOL_CHAIN_TAG' +TAB_TAT_DEFINES_TARGET_ARCH =3D 'TARGET_ARCH' +TAB_TAT_DEFINES_BUILD_RULE_CONF =3D "BUILD_RULE_CONF" + +# +# ToolDef Definitions +# +TAB_TOD_DEFINES_TARGET =3D 'TARGET' +TAB_TOD_DEFINES_TOOL_CHAIN_TAG =3D 'TOOL_CHAIN_TAG' +TAB_TOD_DEFINES_TARGET_ARCH =3D 'TARGET_ARCH' +TAB_TOD_DEFINES_COMMAND_TYPE =3D 'COMMAND_TYPE' +TAB_TOD_DEFINES_FAMILY =3D 'FAMILY' +TAB_TOD_DEFINES_BUILDRULEFAMILY =3D 'BUILDRULEFAMILY' +TAB_TOD_DEFINES_BUILDRULEORDER =3D 'BUILDRULEORDER' + +# +# Conditional Statements +# +TAB_IF =3D '!if' +TAB_END_IF =3D '!endif' +TAB_ELSE_IF =3D '!elseif' +TAB_ELSE =3D '!else' +TAB_IF_DEF =3D '!ifdef' +TAB_IF_N_DEF =3D '!ifndef' +TAB_IF_EXIST =3D '!if exist' +TAB_ERROR =3D '!error' + +# +# Unknown section +# +TAB_UNKNOWN =3D 'UNKNOWN' + +# +# Build database path +# +DATABASE_PATH =3D ":memory:" #"BuildDatabase.db" + +# used by ECC +MODIFIER_SET =3D {'IN', 'OUT', 'OPTIONAL', 'UNALIGNED', 'EFI_RUNTIMESERVIC= E', 'EFI_BOOTSERVICE', 'EFIAPI'} + +# Dependency Opcodes +DEPEX_OPCODE_BEFORE =3D "BEFORE" +DEPEX_OPCODE_AFTER =3D "AFTER" +DEPEX_OPCODE_PUSH =3D "PUSH" +DEPEX_OPCODE_AND =3D "AND" +DEPEX_OPCODE_OR =3D "OR" +DEPEX_OPCODE_NOT =3D "NOT" +DEPEX_OPCODE_END =3D "END" +DEPEX_OPCODE_SOR =3D "SOR" +DEPEX_OPCODE_TRUE =3D "TRUE" +DEPEX_OPCODE_FALSE =3D "FALSE" + +# Dependency Expression +DEPEX_SUPPORTED_OPCODE_SET =3D {"BEFORE", "AFTER", "PUSH", "AND", "OR", "N= OT", "END", "SOR", "TRUE", "FALSE", '(', ')'} + +TAB_STATIC_LIBRARY =3D "STATIC-LIBRARY-FILE" +TAB_DYNAMIC_LIBRARY =3D "DYNAMIC-LIBRARY-FILE" +TAB_FRAMEWORK_IMAGE =3D "EFI-IMAGE-FILE" +TAB_C_CODE_FILE =3D "C-CODE-FILE" +TAB_C_HEADER_FILE =3D "C-HEADER-FILE" +TAB_UNICODE_FILE =3D "UNICODE-TEXT-FILE" +TAB_IMAGE_FILE =3D "IMAGE-DEFINITION-FILE" +TAB_DEPENDENCY_EXPRESSION_FILE =3D "DEPENDENCY-EXPRESSION-FILE" +TAB_UNKNOWN_FILE =3D "UNKNOWN-TYPE-FILE" +TAB_DEFAULT_BINARY_FILE =3D "_BINARY_FILE_" +TAB_OBJECT_FILE =3D "OBJECT-FILE" +TAB_VFR_FILE =3D 'VISUAL-FORM-REPRESENTATION-FILE' + +# used by BRG +TAB_BRG_PCD =3D 'PCD' +TAB_BRG_LIBRARY =3D 'Library' + +# +# Build Rule File Version Definition +# +TAB_BUILD_RULE_VERSION =3D "build_rule_version" + +# section name for PCDs +PCDS_DYNAMIC_DEFAULT =3D "PcdsDynamicDefault" +PCDS_DYNAMIC_VPD =3D "PcdsDynamicVpd" +PCDS_DYNAMIC_HII =3D "PcdsDynamicHii" +PCDS_DYNAMICEX_DEFAULT =3D "PcdsDynamicExDefault" +PCDS_DYNAMICEX_VPD =3D "PcdsDynamicExVpd" +PCDS_DYNAMICEX_HII =3D "PcdsDynamicExHii" + +SECTIONS_HAVE_ITEM_PCD_SET =3D {PCDS_DYNAMIC_DEFAULT.upper(), PCDS_DYNAMIC= _VPD.upper(), PCDS_DYNAMIC_HII.upper(), \ + PCDS_DYNAMICEX_DEFAULT.upper(), PCDS_DYNAMIC= EX_VPD.upper(), PCDS_DYNAMICEX_HII.upper()} +# Section allowed to have items after arch +SECTIONS_HAVE_ITEM_AFTER_ARCH_SET =3D {TAB_LIBRARY_CLASSES.upper(), TAB_DE= PEX.upper(), TAB_USER_EXTENSIONS.upper(), + PCDS_DYNAMIC_DEFAULT.upper(), + PCDS_DYNAMIC_VPD.upper(), + PCDS_DYNAMIC_HII.upper(), + PCDS_DYNAMICEX_DEFAULT.upper(), + PCDS_DYNAMICEX_VPD.upper(), + PCDS_DYNAMICEX_HII.upper(), + TAB_BUILD_OPTIONS.upper(), + TAB_INCLUDES.upper()} + +# +# pack codes as used in PcdDb and elsewhere +# +PACK_PATTERN_GUID =3D '=3DLHHBBBBBBBB' +PACK_CODE_BY_SIZE =3D {8:'=3DQ', + 4:'=3DL', + 2:'=3DH', + 1:'=3DB', + 0:'=3DB', + 16:""} + +TAB_COMPILER_MSFT =3D 'MSFT' --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46788): https://edk2.groups.io/g/devel/message/46788 Mute This Topic: https://groups.io/mt/33137137/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46789+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46789+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595622; cv=none; d=zoho.com; s=zohoarc; b=TLjPon/vnS9AN1gr3355IcJkLseFSUWKZFe24/QQA4SWN+/nH7M2bGnQ7o8ZR/hyXF2UNe0nh5O9s6/nzEzKqXJ1B/I+htjGfY0D6OFBforbYsVNYQRAEjFjX31WqYCue6YAPKIAqiq7aspHBJVFIwVjU5j8kA5n7P3L+8WNu7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595622; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=nlsBOSz3HpXvOVmjXagVMb0+oLufnRPF+RUqtRcmq1U=; b=Xo5jxz3C2YUAuZu4xC5vbzzSjhAlx7GqaqqIRcn+NeFQRL6cnc/oEqGDAGoCF/EjCbuG0r7AFn4PBesM2/o3/P2tJGbDlFft0ks6k+Uzf0YbkwOINj40R3yGOdWXTVoTeh/8bEU4t5FeknIEEJWpPUEOwaBm1LyiQRsuUMKmbLU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46789+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156759562246540.939645886329345; Wed, 4 Sep 2019 04:13:42 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:41 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBhuN022238 for ; Wed, 4 Sep 2019 11:13:40 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2uswj5wr98-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:40 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id AC4BEB3 for ; Wed, 4 Sep 2019 11:13:39 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id C3F8939; Wed, 4 Sep 2019 11:13:38 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 12/22]: MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. Date: Wed, 4 Sep 2019 18:43:07 +0800 Message-Id: <1567593797-26216-13-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595622; bh=AJPKIJfLU/r0XXHdbP++5690cNbK6D/Y1nv4oTVuqCQ=; h=Cc:Date:From:Reply-To:Subject:To; b=B65TI20xTMTNPryxEJa46+myVIvYyBKQqZ8ZictpNfj14+HZSQ9Ngn91Aw/Si4OI1iu muT7vDE50prPKgDfqIyw7/J54sGpJJUtA6OUBKUrr02Rp1wpeLC/iBpaTHcKOFf3FpnjH bQ9Ani6p9kms1/wrjlxkJN4BQaqEofj2ULo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RISC-V processor binding and RISC-V processor specific definitions and = macros. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/Library/BaseLib/BaseLib.inf | 18 +- MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 33 ++ MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 35 ++ MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 33 ++ MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 33 ++ MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 28 + MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 43 ++ .../Library/BaseLib/RiscV64/InternalSwitchStack.c | 61 +++ MdePkg/Library/BaseLib/RiscV64/LongJump.c | 38 ++ .../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 20 + MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 20 + MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 33 ++ .../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 61 +++ MdePkg/Library/BaseLib/RiscV64/Unaligned.c | 270 ++++++++++ MdePkg/Library/BaseLib/RiscV64/riscv_asm.h | 194 +++++++ MdePkg/Library/BaseLib/RiscV64/riscv_encoding.h | 574 +++++++++++++++++= ++++ MdePkg/Library/BaseLib/RiscV64/sbi_const.h | 53 ++ 17 files changed, 1546 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/Unaligned.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/riscv_asm.h create mode 100644 MdePkg/Library/BaseLib/RiscV64/riscv_encoding.h create mode 100644 MdePkg/Library/BaseLib/RiscV64/sbi_const.h diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb..28d5795 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -381,6 +382,21 @@ AArch64/CpuBreakpoint.asm | MSFT AArch64/SpeculationBarrier.asm | MSFT =20 +[Sources.RISCV64] + Math64.c + RiscV64/Unaligned.c + RiscV64/InternalSwitchStack.c + RiscV64/CpuBreakpoint.c + RiscV64/GetInterruptState.c + RiscV64/DisableInterrupts.c + RiscV64/EnableInterrupts.c + RiscV64/CpuPause.c + RiscV64/RiscVSetJumpLongJump.S | GCC + RiscV64/RiscVCpuBreakpoint.S | GCC + RiscV64/RiscVCpuPause.S | GCC + RiscV64/RiscVInterrupt.S | GCC + RiscV64/FlushCache.S | GCC + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Librar= y/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 0000000..763b813 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,33 @@ +/** @file + CPU breakpoint for RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuBreakpoint (VOID); + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + RiscVCpuBreakpoint (); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/Bas= eLib/RiscV64/CpuPause.c new file mode 100644 index 0000000..3094aac --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,35 @@ +/** @file + CPU pause for RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuPause (VOID); + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + RiscVCpuPause (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Li= brary/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 0000000..6f7e88c --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,33 @@ +/** @file + CPU disable interrupt function for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ +#include "BaseLibInternals.h" +#include "riscv_asm.h" +#include "riscv_encoding.h" + + +extern VOID RiscVDisableInterrupts (VOID); + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + csr_clear(CSR_SSTATUS, MSTATUS_SIE); //SIE +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Lib= rary/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 0000000..a0ce150 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,33 @@ +/** @file + CPU enable interrupt function for RISC-V + + Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" +#include "riscv_asm.h" +#include "riscv_encoding.h" + +extern VOID RiscVEnableInterrupt (VOID); + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + csr_set(CSR_SSTATUS, MSTATUS_SIE); //SIE +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S new file mode 100644 index 0000000..75ddc46 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,28 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvdInstCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvdDataCacheAsm) + + +ASM_PFX(RiscVInvdInstCacheAsm): + //fence.i + ret + +ASM_PFX(RiscVInvdDataCacheAsm): + //fence + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Li= brary/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 0000000..b12450f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,43 @@ +/** @file + CPU get interrupt state function for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" +#include "riscv_asm.h" +#include "riscv_encoding.h" + +extern UINT32 RiscVGetInterrupts (VOID); + +/** + Retrieves the current CPU interrupt state. + + Returns TRUE is interrupts are currently enabled. Otherwise + returns FALSE. + + @retval TRUE CPU interrupts are enabled. + @retval FALSE CPU interrupts are disabled. + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ) +{ + unsigned long RetValue; + + RetValue =3D csr_read(CSR_SSTATUS); + return (RetValue & MSTATUS_SIE)? TRUE: FALSE; +} + + diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/= Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 0000000..7d748a1 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,61 @@ +/** @file + Switch stack function for RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param Marker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + ) +{ + BASE_LIBRARY_JUMP_BUFFER JumpBuffer; + + DEBUG ((EFI_D_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Con= text2:%x NewStack%x\n", \ + EntryPoint, Context1, Context2, NewStack)); + JumpBuffer.RA =3D (UINTN)EntryPoint; + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *); + JumpBuffer.S0 =3D (UINT64)(UINTN)Context1; + JumpBuffer.S1 =3D (UINT64)(UINTN)Context2; + LongJump (&JumpBuffer, (UINTN)-1); + ASSERT(FALSE); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/Bas= eLib/RiscV64/LongJump.c new file mode 100644 index 0000000..bd081f2 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c @@ -0,0 +1,38 @@ +/** @file + Long jump implementation of RISC-V + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" + + +/** + Restores the CPU context that was saved with SetJump(). + + Restores the CPU context from the buffer specified by JumpBuffer. + This function never returns to the caller. + Instead is resumes execution based on the state of JumpBuffer. + + @param JumpBuffer A pointer to CPU context buffer. + @param Value The value to return when the SetJump() context is = restored. + +**/ +VOID +EFIAPI +InternalLongJump ( + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, + IN UINTN Value + ) +{ + ASSERT (FALSE); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/L= ibrary/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 0000000..3c38e4d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,20 @@ +//------------------------------------------------------------------------= ------ +// +// CpuBreakpoint for RISC-V +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint) +ASM_PFX(RiscVCpuBreakpoint): + ebreak + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 0000000..64b9fb5 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,20 @@ +//------------------------------------------------------------------------= ------ +// +// CpuPause for RISC-V +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuPause) +ASM_PFX(RiscVCpuPause): + nop + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 0000000..5782ced --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------ +// +// Cpu interrupt enable/disable for RISC-V +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVDisableInterrupts) +ASM_GLOBAL ASM_PFX(RiscVEnableInterrupt) +ASM_GLOBAL ASM_PFX(RiscVGetInterrupts) + +ASM_PFX(RiscVDisableInterrupts): + li a1, 0xaaa + csrc 0x304, a1 + ret + +ASM_PFX(RiscVEnableInterrupt): + li a1, 0x80 + csrs 0x304, a1 + ret + +ASM_PFX(RiscVGetInterrupts): + csrr a0, 0x304 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg= /Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 0000000..bd75408 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------= ------ +// +// Set/Long jump for RISC-V +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +# define REG_S sd +# define REG_L ld +# define SZREG 8 +.align 3 + .globl SetJump + +SetJump: + REG_S ra, 0*SZREG(a0) + REG_S s0, 1*SZREG(a0) + REG_S s1, 2*SZREG(a0) + REG_S s2, 3*SZREG(a0) + REG_S s3, 4*SZREG(a0) + REG_S s4, 5*SZREG(a0) + REG_S s5, 6*SZREG(a0) + REG_S s6, 7*SZREG(a0) + REG_S s7, 8*SZREG(a0) + REG_S s8, 9*SZREG(a0) + REG_S s9, 10*SZREG(a0) + REG_S s10,11*SZREG(a0) + REG_S s11,12*SZREG(a0) + REG_S sp, 13*SZREG(a0) + li a0, 0 + ret + + .globl InternalLongJump +InternalLongJump: + REG_L ra, 0*SZREG(a0) + REG_L s0, 1*SZREG(a0) + REG_L s1, 2*SZREG(a0) + REG_L s2, 3*SZREG(a0) + REG_L s3, 4*SZREG(a0) + REG_L s4, 5*SZREG(a0) + REG_L s5, 6*SZREG(a0) + REG_L s6, 7*SZREG(a0) + REG_L s7, 8*SZREG(a0) + REG_L s8, 9*SZREG(a0) + REG_L s9, 10*SZREG(a0) + REG_L s10,11*SZREG(a0) + REG_L s11,12*SZREG(a0) + REG_L sp, 13*SZREG(a0) + + add a0, s0, 0 + add a1, s1, 0 + add a2, s2, 0 + add a3, s3, 0 + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/Unaligned.c b/MdePkg/Library/Ba= seLib/RiscV64/Unaligned.c new file mode 100644 index 0000000..7068a63 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/Unaligned.c @@ -0,0 +1,270 @@ +/** @file + RISC-V specific functionality for (un)aligned memory read/write. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "BaseLibInternals.h" + +/** + Reads a 16-bit value from memory that may be unaligned. + + This function returns the 16-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 16-bit value that may be unaligned. + + @return The 16-bit value read from Buffer. + +**/ +UINT16 +EFIAPI +ReadUnaligned16 ( + IN CONST UINT16 *Buffer + ) +{ + UINT16 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D sizeof (UINT16) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 16-bit value to memory that may be unaligned. + + This function writes the 16-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 16-bit value that may be unaligned. + @param Value 16-bit value to write to Buffer. + + @return The 16-bit value to write to Buffer. + +**/ +UINT16 +EFIAPI +WriteUnaligned16 ( + OUT UINT16 *Buffer, + IN UINT16 Value + ) +{ + INT8 Count; + UINT16 ValueTemp; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT16) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 24-bit value from memory that may be unaligned. + + This function returns the 24-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 24-bit value that may be unaligned. + + @return The 24-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned24 ( + IN CONST UINT32 *Buffer + ) +{ + UINT32 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 2, Value =3D 0; Count >=3D 0 ; Count --) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 24-bit value to memory that may be unaligned. + + This function writes the 24-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 24-bit value that may be unaligned. + @param Value 24-bit value to write to Buffer. + + @return The 24-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned24 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ) +{ + INT8 Count; + UINT32 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < 3 ; Count ++) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 32-bit value from memory that may be unaligned. + + This function returns the 32-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 32-bit value that may be unaligned. + + @return The 32-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned32 ( + IN CONST UINT32 *Buffer + ) +{ + UINT32 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + + for (Count =3D sizeof (UINT32) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 32-bit value to memory that may be unaligned. + + This function writes the 32-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 32-bit value that may be unaligned. + @param Value The 32-bit value to write to Buffer. + + @return The 32-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned32 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ) +{ + INT8 Count; + UINT32 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT32) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} + +/** + Reads a 64-bit value from memory that may be unaligned. + + This function returns the 64-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 64-bit value that may be unaligned. + + @return The 64-bit value read from Buffer. + +**/ +UINT64 +EFIAPI +ReadUnaligned64 ( + IN CONST UINT64 *Buffer + ) +{ + UINT64 Value; + INT8 Count; + + ASSERT (Buffer !=3D NULL); + for (Count =3D sizeof (UINT64) - 1, Value =3D 0; Count >=3D 0 ; Count --= ) { + Value =3D Value << 8; + Value |=3D *((UINT8*)Buffer + Count); + } + return Value; +} + +/** + Writes a 64-bit value to memory that may be unaligned. + + This function writes the 64-bit value specified by Value to Buffer. Valu= e is + returned. The function guarantees that the write operation does not prod= uce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer A pointer to a 64-bit value that may be unaligned. + @param Value The 64-bit value to write to Buffer. + + @return The 64-bit value to write to Buffer. + +**/ +UINT64 +EFIAPI +WriteUnaligned64 ( + OUT UINT64 *Buffer, + IN UINT64 Value + ) +{ + INT8 Count; + UINT64 ValueTemp; + + ASSERT (Buffer !=3D NULL); + for (Count =3D 0, ValueTemp =3D Value; Count < sizeof (UINT64) ; Count += +) { + *((UINT8*)Buffer + Count) =3D (UINT8)(ValueTemp & 0xff); + ValueTemp =3D ValueTemp >> 8; + } + return Value; +} diff --git a/MdePkg/Library/BaseLib/RiscV64/riscv_asm.h b/MdePkg/Library/Ba= seLib/RiscV64/riscv_asm.h new file mode 100644 index 0000000..b050742 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/riscv_asm.h @@ -0,0 +1,194 @@ +/** @file + Macro definitions of RISC-V CSR assembly. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ =20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + =20 + SPDX-License-Identifier: BSD-2-Clause +=20 + Copyright (c) 2019 Western Digital Corporation or its affiliates. + +**/ + +#ifndef __RISCV_ASM_H__ +#define __RISCV_ASM_H__ + +#include "riscv_encoding.h" + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen =3D=3D 64 +#define __REG_SEL(a, b) __ASM_STR(a) +#elif __riscv_xlen =3D=3D 32 +#define __REG_SEL(a, b) __ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) +#define SBI_TLB_FLUSH_ALL ((unsigned long)-1) + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + +#if __SIZEOF_POINTER__ =3D=3D 8 +#define BITS_PER_LONG 64 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .dword +#define RISCV_SZPTR 8 +#define RISCV_LGPTR 3 +#else +#define RISCV_PTR ".dword" +#define RISCV_SZPTR "8" +#define RISCV_LGPTR "3" +#endif +#elif __SIZEOF_POINTER__ =3D=3D 4 +#define BITS_PER_LONG 32 +#ifdef __ASSEMBLY__ +#define RISCV_PTR .word +#define RISCV_SZPTR 4 +#define RISCV_LGPTR 2 +#else +#define RISCV_PTR ".word" +#define RISCV_SZPTR "4" +#define RISCV_LGPTR "2" +#endif +#else +#error "Unexpected __SIZEOF_POINTER__" +#endif + +#if (__SIZEOF_INT__ =3D=3D 4) +#define RISCV_INT __ASM_STR(.word) +#define RISCV_SZINT __ASM_STR(4) +#define RISCV_LGINT __ASM_STR(2) +#else +#error "Unexpected __SIZEOF_INT__" +#endif + +#if (__SIZEOF_SHORT__ =3D=3D 2) +#define RISCV_SHORT __ASM_STR(.half) +#define RISCV_SZSHORT __ASM_STR(2) +#define RISCV_LGSHORT __ASM_STR(1) +#else +#error "Unexpected __SIZEOF_SHORT__" +#endif + +#ifndef __ASSEMBLY__ + +#define csr_swap(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ + : "=3Dr" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ + : "=3Dr" (__v) : \ + : "memory"); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_set(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ + : "=3Dr" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_clear(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ + : "=3Dr" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +unsigned long csr_read_num(int csr_num); + +void csr_write_num(int csr_num, unsigned long val); + +#define wfi() \ +do { \ + __asm__ __volatile__ ("wfi" ::: "memory"); \ +} while (0) + +static inline int misa_extension(char ext) +{ + return csr_read(CSR_MISA) & (1 << (ext - 'A')); +} + +static inline int misa_xlen(void) +{ + return ((long)csr_read(CSR_MISA) < 0) ? 64 : 32; +} + +static inline void misa_string(char *out, unsigned int out_sz) +{ + unsigned long i, val =3D csr_read(CSR_MISA); + + for (i =3D 0; i < 26; i++) { + if (val & (1 << i)) { + *out =3D 'A' + i; + out++; + } + } + *out =3D '\0'; + out++; +} + +int pmp_set(unsigned int n, unsigned long prot, + unsigned long addr, unsigned long log2len); + +int pmp_get(unsigned int n, unsigned long *prot_out, + unsigned long *addr_out, unsigned long *log2len_out); + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/MdePkg/Library/BaseLib/RiscV64/riscv_encoding.h b/MdePkg/Libra= ry/BaseLib/RiscV64/riscv_encoding.h new file mode 100644 index 0000000..6f5fefd --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/riscv_encoding.h @@ -0,0 +1,574 @@ +/** @file + Definitions of RISC-V CSR. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ =20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + =20 + SPDX-License-Identifier: BSD-2-Clause +=20 + Copyright (c) 2019 Western Digital Corporation or its affiliates. + +**/ + +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +#include "sbi_const.h" + +/* TODO: Make constants usable in assembly with _AC() macro */ + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_A_TOR 0x08 +#define PMP_A_NA4 0x10 +#define PMP_A_NAPOT 0x18 +#define PMP_L 0x80 + +#define PMP_SHIFT 2 +#define PMP_COUNT 16 + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) \ + (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) =3D=3D PTE_V) + +#if __riscv_xlen =3D=3D 64 +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#define SATP_MODE SATP64_MODE +#else +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#define CSR_USTATUS 0x0 +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_UIE 0x4 +#define CSR_UTVEC 0x5 +#define CSR_USCRATCH 0x40 +#define CSR_UEPC 0x41 +#define CSR_UCAUSE 0x42 +#define CSR_UTVAL 0x43 +#define CSR_UIP 0x44 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_HYPERVISOR_ECALL 0x9 +#define CAUSE_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf + +#define INSN_MATCH_LB 0x3 +#define INSN_MASK_LB 0x707f +#define INSN_MATCH_LH 0x1003 +#define INSN_MASK_LH 0x707f +#define INSN_MATCH_LW 0x2003 +#define INSN_MASK_LW 0x707f +#define INSN_MATCH_LD 0x3003 +#define INSN_MASK_LD 0x707f +#define INSN_MATCH_LBU 0x4003 +#define INSN_MASK_LBU 0x707f +#define INSN_MATCH_LHU 0x5003 +#define INSN_MASK_LHU 0x707f +#define INSN_MATCH_LWU 0x6003 +#define INSN_MASK_LWU 0x707f +#define INSN_MATCH_SB 0x23 +#define INSN_MASK_SB 0x707f +#define INSN_MATCH_SH 0x1023 +#define INSN_MASK_SH 0x707f +#define INSN_MATCH_SW 0x2023 +#define INSN_MASK_SW 0x707f +#define INSN_MATCH_SD 0x3023 +#define INSN_MASK_SD 0x707f + +#define INSN_MATCH_FLW 0x2007 +#define INSN_MASK_FLW 0x707f +#define INSN_MATCH_FLD 0x3007 +#define INSN_MASK_FLD 0x707f +#define INSN_MATCH_FLQ 0x4007 +#define INSN_MASK_FLQ 0x707f +#define INSN_MATCH_FSW 0x2027 +#define INSN_MASK_FSW 0x707f +#define INSN_MATCH_FSD 0x3027 +#define INSN_MASK_FSD 0x707f +#define INSN_MATCH_FSQ 0x4027 +#define INSN_MASK_FSQ 0x707f + +#define INSN_MATCH_C_LD 0x6000 +#define INSN_MASK_C_LD 0xe003 +#define INSN_MATCH_C_SD 0xe000 +#define INSN_MASK_C_SD 0xe003 +#define INSN_MATCH_C_LW 0x4000 +#define INSN_MASK_C_LW 0xe003 +#define INSN_MATCH_C_SW 0xc000 +#define INSN_MASK_C_SW 0xe003 +#define INSN_MATCH_C_LDSP 0x6002 +#define INSN_MASK_C_LDSP 0xe003 +#define INSN_MATCH_C_SDSP 0xe002 +#define INSN_MASK_C_SDSP 0xe003 +#define INSN_MATCH_C_LWSP 0x4002 +#define INSN_MASK_C_LWSP 0xe003 +#define INSN_MATCH_C_SWSP 0xc002 +#define INSN_MASK_C_SWSP 0xe003 + +#define INSN_MATCH_C_FLD 0x2000 +#define INSN_MASK_C_FLD 0xe003 +#define INSN_MATCH_C_FLW 0x6000 +#define INSN_MASK_C_FLW 0xe003 +#define INSN_MATCH_C_FSD 0xa000 +#define INSN_MASK_C_FSD 0xe003 +#define INSN_MATCH_C_FSW 0xe000 +#define INSN_MASK_C_FSW 0xe003 +#define INSN_MATCH_C_FLDSP 0x2002 +#define INSN_MASK_C_FLDSP 0xe003 +#define INSN_MATCH_C_FSDSP 0xa002 +#define INSN_MASK_C_FSDSP 0xe003 +#define INSN_MATCH_C_FLWSP 0x6002 +#define INSN_MASK_C_FLWSP 0xe003 +#define INSN_MATCH_C_FSWSP 0xe002 +#define INSN_MASK_C_FSWSP 0xe003 + +#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4) + +#if __riscv_xlen =3D=3D 64 +#define LOG_REGBYTES 3 +#else +#define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#define SH_RD 7 +#define SH_RS1 15 +#define SH_RS2 20 +#define SH_RS2C 2 + +#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) +#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ + (RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 1) << 6)) +#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 2) << 6)) +#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 2) << 6)) +#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 3) << 6)) +#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ + (RV_X(x, 7, 2) << 6)) +#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 7, 3) << 6)) +#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) +#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) +#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) + +#define SHIFT_RIGHT(x, y) \ + ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) + +#define REG_MASK \ + ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) + +#define REG_OFFSET(insn, pos) \ + (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) + +#define REG_PTR(insn, pos, regs) \ + (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)) + +#define GET_RM(insn) (((insn) >> 12) & 7) + +#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) +#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) +#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) +#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) +#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) +#define GET_SP(regs) (*REG_PTR(2, 0, regs)) +#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) =3D (val)) +#define IMM_I(insn) ((s32)(insn) >> 20) +#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ + (s32)(((insn) >> 7) & 0x1f)) +#define MASK_FUNCT3 0x7000 + +#endif diff --git a/MdePkg/Library/BaseLib/RiscV64/sbi_const.h b/MdePkg/Library/Ba= seLib/RiscV64/sbi_const.h new file mode 100644 index 0000000..e6868c4 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/sbi_const.h @@ -0,0 +1,53 @@ +/** @file + Definitions of RISC-V SBI constants. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ =20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + =20 + SPDX-License-Identifier: BSD-2-Clause +=20 + Copyright (c) 2019 Western Digital Corporation or its affiliates. + +**/ + +#ifndef __SBI_CONST_H__ +#define __SBI_CONST_H__ + +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLY__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define __STR(s) #s +#define STRINGIFY(s) __STR(s) + +#endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46789): https://edk2.groups.io/g/devel/message/46789 Mute This Topic: https://groups.io/mt/33137138/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46790+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46790+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595623; cv=none; d=zoho.com; s=zohoarc; b=MRdxnsqpC+imdEMH1SkVc0MMvx7tnb+/Gt0gjSLsC5H9Z/603XSnoslYnu2C1nkllyxjGLyC1ti5/X+LaYM9PmbRFWwXK1XGWEAi/vb+DivzlFElIjPpBst4J4dceuJlIHxiSdd9YJ/1IqdeMOLjssDMewq+oXhm9W37Q1kYsPk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595623; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=yZdSiwzW26zIotk44nuhETAxLeE0VANb4rbYAvtHYJo=; b=hbQG1h/9/hFyTSmbaWdoTRDDyOYKnJ4dC0A6ndyKXzR6P6dBG1sT4dT4X4ahyo6/ZEa2WYP3xJcRbsp01wSa50NERAhGNKF50YYudiVZ6jlzo+lYBi/ERsTU+WKiudOB0Rm15Cp5wiY91V/W+nyIwqLYH8Cf4WWvhGbT0RwmVOs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46790+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595623477752.4887069033791; Wed, 4 Sep 2019 04:13:43 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:42 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84B7QGw011990 for ; Wed, 4 Sep 2019 11:13:41 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 2ut4v5k8u3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:41 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 0C30E77 for ; Wed, 4 Sep 2019 11:13:41 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 2341539; Wed, 4 Sep 2019 11:13:39 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 13/22]: MdePkg/Include: Update SmBios header file. Date: Wed, 4 Sep 2019 18:43:08 +0800 Message-Id: <1567593797-26216-14-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595623; bh=pJUnIsFWHwMsbG8/acdt9TjzV4dtSFkQI7PtQQMxUbM=; h=Cc:Date:From:Reply-To:Subject:To; b=lXrvh7dv5P9xFzQbLLX61dHh5iKFVvFQmM3sexc7ar1kanC4sQYEC1B7ofJ7o9KSa41 Qsg/ha70l3fMSmFBsK9Ob8ih98MGD3XeWVlWNm8mS/AlFGGCDI1xom8ybO1wGFtlF38Fs 5jUDkV5xPB1/ZU0NwXl242g6IaNl4Dj1Ha4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update SmBios header file to conform with SMBIOS v3.3.0. The major update is to add definitions of SMBIOS Type 44h record. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdePkg/Include/IndustryStandard/SmBios.h | 74 ++++++++++++++++++++++++++++= +++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/Indu= stryStandard/SmBios.h index f3b6f18..a744d06 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -46,7 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF =20 // -// SMBIOS type macros which is according to SMBIOS 2.7 specification. +// SMBIOS type macros which is according to SMBIOS 3.3.0 specification. // #define SMBIOS_TYPE_BIOS_INFORMATION 0 #define SMBIOS_TYPE_SYSTEM_INFORMATION 1 @@ -92,6 +93,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41 #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42 #define SMBIOS_TYPE_TPM_DEVICE 43 +#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44 =20 /// /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter = 3.3.43. @@ -727,7 +729,10 @@ typedef enum { ProcessorFamilyMII =3D 0x012E, ProcessorFamilyWinChip =3D 0x0140, ProcessorFamilyDSP =3D 0x015E, - ProcessorFamilyVideoProcessor =3D 0x01F4 + ProcessorFamilyVideoProcessor =3D 0x01F4, + ProcessorFamilyRiscvRV32 =3D 0x0200, ///< SMBIOS spec 3.3.0= added + ProcessorFamilyRiscVRV64 =3D 0x0201, ///< SMBIOS spec 3.3.0= added + ProcessorFamilyRiscVRV128 =3D 0x0202 ///< SMBIOS spec 3.3.0= added } PROCESSOR_FAMILY2_DATA; =20 /// @@ -857,6 +862,19 @@ typedef struct { } PROCESSOR_FEATURE_FLAGS; =20 typedef struct { + UINT32 ProcessorReserved1 :1; + UINT32 ProcessorUnknown :1; + UINT32 Processor64BitCapble :1; + UINT32 ProcessorMultiCore :1; + UINT32 ProcessorHardwareThread :1; + UINT32 ProcessorExecuteProtection :1; + UINT32 ProcessorEnhancedVirtulization :1; + UINT32 ProcessorPowerPerformanceCtrl :1; + UINT32 Processor128bitCapble :1; + UINT32 ProcessorReserved2 :7; +} PROCESSOR_CHARACTERISTIC_FLAGS; + +typedef struct { PROCESSOR_SIGNATURE Signature; PROCESSOR_FEATURE_FLAGS FeatureFlags; } PROCESSOR_ID_DATA; @@ -2508,6 +2526,57 @@ typedef struct { UINT8 InterfaceTypeSpecificData[4]; ///< T= his field has a minimum of four bytes } SMBIOS_TABLE_TYPE42; =20 + +/// +/// Processor Specific Block - Processor Architecture Type +/// +typedef enum{ + ProcessorSpecificBlockArchTypeReserved =3D 0x00, + ProcessorSpecificBlockArchTypeIa32 =3D 0x01, + ProcessorSpecificBlockArchTypeX64 =3D 0x02, + ProcessorSpecificBlockArchTypeItanium =3D 0x03, + ProcessorSpecificBlockArchTypeAarch32 =3D 0x04, + ProcessorSpecificBlockArchTypeAarch64 =3D 0x05, + ProcessorSpecificBlockArchTypeRiscVRV32 =3D 0x06, + ProcessorSpecificBlockArchTypeRiscVRV64 =3D 0x07, + ProcessorSpecificBlockArchTypeRiscVRV128 =3D 0x08 +} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE; + +/// +/// Processor Specific Block is the standard container of processor-specif= ic data. +/// +typedef struct { + UINT8 Length; + UINT8 ProcessorArchType; + /// + /// Below followed by Processor-specific data + /// + /// +} PROCESSOR_SPECIFIC_BLOCK; + +/// +/// Processor Additional Information(Type 44). +/// +/// The information in this structure defines the processor additional inf= ormation in case=20 +/// SMBIOS type 4 is not sufficient to describe processor characteristics. +/// The SMBIOS type 44 structure has a reference handle field to link back= to the related=20 +/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structur= es linked to the=20 +/// same SMBIOS type 4 structure. For example, when cores are not identica= l in a processor,=20 +/// SMBIOS type 44 structures describe different core-specific information. +///=20 +/// SMBIOS type 44 defines the standard header for the processor-specific = block, while the +/// contents of processor-specific data are maintained by processor=20 +/// architecture workgroups or vendors in separate documents. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_HANDLE RefHandle; ///< This f= ield refer to associated SMBIOS type 4 + /// + /// Below followed by Processor-specific block + /// + PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock; +} SMBIOS_TABLE_TYPE44; + /// /// TPM Device (Type 43). /// @@ -2586,6 +2655,7 @@ typedef union { SMBIOS_TABLE_TYPE41 *Type41; SMBIOS_TABLE_TYPE42 *Type42; SMBIOS_TABLE_TYPE43 *Type43; + SMBIOS_TABLE_TYPE44 *Type44; SMBIOS_TABLE_TYPE126 *Type126; SMBIOS_TABLE_TYPE127 *Type127; UINT8 *Raw; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46790): https://edk2.groups.io/g/devel/message/46790 Mute This Topic: https://groups.io/mt/33137139/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46791+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46791+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595624; cv=none; d=zoho.com; s=zohoarc; b=mVJm+XhPY6QMtom0r7I0oWDuTeXxp/eZU+Kp8IUr2WAlchEvxng2n9ej2ao1NCGXgesa/TkFqp1kIBZnxH8dY7r0/jbYdvakCECd2QjpbTZ4R+HeATSrlA0+a4IuUDGc5IhHMsC6P91UpVU9clcO0lVCUhGO32+6bjv4VD5xzdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595624; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=xt0ewRHMJ8pFDlLv73rtcWb1dGfQkom5eZTEdUQxyFo=; b=Vi7MtIUVw8BwTYWG1TmwUQ14/TcxdiJ7PltXrYnlPMuVIypbzvVzyLc+3GFyGLAAib0fkkfzcTk7jGwFTaKEJ/ER2raMExPJxegzdVnEgUl3ozRIr8Zj5s0PH88+7JVjaJ6ASJHWrTsgtj+b2xxorzX2Pg1yftbjJ1xcvtkloPI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46791+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595624815459.6708040072083; Wed, 4 Sep 2019 04:13:44 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:43 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBgWw020096 for ; Wed, 4 Sep 2019 11:13:43 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7x3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:43 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 5F947A2 for ; Wed, 4 Sep 2019 11:13:42 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 7653339; Wed, 4 Sep 2019 11:13:41 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 14/22]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Date: Wed, 4 Sep 2019 18:43:09 +0800 Message-Id: <1567593797-26216-15-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595624; bh=iGuRCdxAz897hkjdw80Ed2qpVVtzwT9Ld3n3gjCvPyY=; h=Cc:Date:From:Reply-To:Subject:To; b=NM2FaReu+lQS4259RFMpaakfMEi2By0BOKR/JwBzK9fFJEtS0mddRfzsX/jaGzW5GD7 qJGZHyNci3F6Z3EB0a1ONWZPuHAxcTJyKjJ1e3iFhqPl5DCkm1ynIOhqWmxevXk3dFjVq K8Qz8M3C524YwGmjn3zX6ZkNpvv7jTUyav0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add opensbi-HOWTO.txt for users to build RISC-V platform with RISC-V OpenSB= I library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/opensbi/opensbi-HOWTO.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 RiscVPkg/opensbi/opensbi-HOWTO.txt diff --git a/RiscVPkg/opensbi/opensbi-HOWTO.txt b/RiscVPkg/opensbi/opensbi-= HOWTO.txt new file mode 100644 index 0000000..aff7a69 --- /dev/null +++ b/RiscVPkg/opensbi/opensbi-HOWTO.txt @@ -0,0 +1,17 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + Instroduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +RISC-V Open Source Supervisor Binary Interface (OpenSBI) is an open source +implementation (Refer to https://github.com/riscv/opensbi) of RISC-V SBI s= pec +(Refer to https://github.com/riscv/riscv-sbi-doc), whcih is designed for t= he +platform-specific firmwares executing in RISC-V Machine mode (M-mode). +EDK2 RISC-V port leverage OpenSBI source files and build it into EDK2 RISC= -V +OpenSBI library (RiscVPkg/Library/RiscVOpensbiLib) using edk2 toolchain. + +User has to get OpenSBI source code and put it under RiscVPkg/opensbi usin= g below +command before building RISC-V platform in EDK2 build environment. + +Current supported RISC-V OpenSBI version on EDK2 is v0.4 + + $ git clone https://github.com/riscv/opensbi + $ git checkout tags/v0.4 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46791): https://edk2.groups.io/g/devel/message/46791 Mute This Topic: https://groups.io/mt/33137140/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46792+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46792+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595626; cv=none; d=zoho.com; s=zohoarc; b=T/nPdljNf4rgrEjqNTz7LWrFS6OBvT+2QcdRhshx5z+mRPBIPnl+kmwrFrmM0Pbf+wLqKYnPkCX9+at2BUW2dCggg8dXQegaCUp61mY2Kkl6+q8KTIsmVYZV6D0DZZ6CVr6C9VLqZt5taPzY/CCmsJOGU5F1OGLU2jZBkQcKvS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595626; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=uxq5K7IFU6274TQc5iYCbdftpRmmRGs/HhnaoMb5xWY=; b=AuDM1kCkNnGuf6kKvwBYyqAElUaQjpsSzk9LkADCqLeICf9jND85IITOpXhglCTE1llQL0WaH8UeexXW83+mqn18CFCINiqpYRoafkNm6s1tPx8pLbRKJ9Ld+VxRUsavgnc6o4TYUV8zqNIk3XXs0v9IiVGYke2dAiv49U2mL0E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46792+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595626244586.5234106432669; Wed, 4 Sep 2019 04:13:46 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:45 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBhcx012842 for ; Wed, 4 Sep 2019 11:13:44 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 2utc41r1j3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:44 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id B448DBA for ; Wed, 4 Sep 2019 11:13:43 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id CA9E739; Wed, 4 Sep 2019 11:13:42 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 15/22]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Date: Wed, 4 Sep 2019 18:43:10 +0800 Message-Id: <1567593797-26216-16-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595625; bh=CW5azRMjQZLomqKEGEYYOCG9eFZKiKV1m5Cz8KyXagg=; h=Cc:Date:From:Reply-To:Subject:To; b=cdtTucxOFScolsihRTKlSSWAIJGimceWgRWvyIOmjD6YyBaWj77tzXDhZca3c2MRvxi qQ/CeYoP5V6UShhFsBcciPGLFd2WEPWtWifKiuXfXiqnNezJ0qqwdIeFNWWKAhyUPekKI CKJUmbOWTWHJ2ivRRoZdX4xY1rsznJzO7hU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is the abstract driver which incorporate with platform level RTC libra= ry (RealTimeClockLib) to provide Real Time Clock Architecture Protocol. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../RealTimeClockRuntimeDxe/RealTimeClock.c | 157 +++++++++++++++++= ++++ .../RealTimeClockRuntimeDxe.inf | 44 ++++++ 2 files changed, 201 insertions(+) create mode 100644 RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeCloc= k.c create mode 100644 RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeCloc= kRuntimeDxe.inf diff --git a/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c b/R= iscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c new file mode 100644 index 0000000..c3d04e7 --- /dev/null +++ b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c @@ -0,0 +1,157 @@ +/** @file + Implementation of EFI RealTimeClock runtime services via platform RTC Li= b.=20 + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +EFI_HANDLE mHandle =3D NULL; + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ +EFI_STATUS +EFIAPI +GetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + return LibGetTime (Time, Capabilities); +} + + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ +EFI_STATUS +EFIAPI +SetTime ( + IN EFI_TIME *Time + ) +{ + return LibSetTime (Time); +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS +EFIAPI +GetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + return LibGetWakeupTime (Enabled, Pending, Time); +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +SetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + return LibSetWakeupTime (Enabled, Time); +} + + + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeRealTimeClock ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D LibRtcInitialize (ImageHandle, SystemTable); + if (EFI_ERROR (Status)) { + return Status; + } + + SystemTable->RuntimeServices->GetTime =3D GetTime; + SystemTable->RuntimeServices->SetTime =3D SetTime; + SystemTable->RuntimeServices->GetWakeupTime =3D GetWakeupTime; + SystemTable->RuntimeServices->SetWakeupTime =3D SetWakeupTime; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiRealTimeClockArchProtocolGuid, + NULL, + NULL + ); + + return Status; +} + diff --git a/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntim= eDxe.inf b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeD= xe.inf new file mode 100644 index 0000000..afc1bca --- /dev/null +++ b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf @@ -0,0 +1,44 @@ +#/** @file +# This driver installs RTC Architecture Protocol +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RealTimeClock + FILE_GUID =3D C641D483-B367-40EF-96B3-860B75A4604E + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializeRealTimeClock + +[Sources.common] + RealTimeClock.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + RealTimeClockLib + +[Protocols] + gEfiRealTimeClockArchProtocolGuid + +[Depex] + TRUE + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46792): https://edk2.groups.io/g/devel/message/46792 Mute This Topic: https://groups.io/mt/33137142/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46793+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46793+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595627; cv=none; d=zoho.com; s=zohoarc; b=GhEOT9iqULL+2hGKKm3MvcJG7zW0Yse1ezNQcvtiphAjYfOATIhmR/BP4+DRMYjEpnjwHyrkhRpu4Ic0/nEvSiiw1znFNX2oAk3nrB+BuHKWGBt0TuG7xx21Hq3diImVCFI80CZYmVtkHvP+6ql40eh/CPw7H1P33FjgaYtA5NU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595627; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=HmCH/wmYaSO0AEY49aS/aWobjQhnl21KxQjhDgGVwNc=; b=asq3CPESwj9PHmIHf3DfmqReM3UU9uKVGIz5OYWJDzLCKDTf0gahsHJdZ/SpP+qoaV1/TUqhlo6pa95FKfeH7P0/u0xduxeaA5voHHk8kQp7Cwf5MatQasidnlThfuMHp4dPHa5KfrsYSYvioYijpmZ3qcAPn9P0lPzHmV5BlGU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46793+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595627914322.3911402957307; Wed, 4 Sep 2019 04:13:47 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:46 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBwJW017058 for ; Wed, 4 Sep 2019 11:13:46 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 2usra9rcms-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:45 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 1349E77 for ; Wed, 4 Sep 2019 11:13:45 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 2A8EC39; Wed, 4 Sep 2019 11:13:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 16/22]: RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver. Date: Wed, 4 Sep 2019 18:43:11 +0800 Message-Id: <1567593797-26216-17-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595627; bh=hgvvaXSer22YzAGoR/YUPLoZX4rG8XSmlCFem1MAbdY=; h=Cc:Date:From:Reply-To:Subject:To; b=YhlJavdjzX3c3kOCipxpgmcbAEW4tK+6dppi96Wp7s8p5qt//PkbXo3o2LJaHii1w/E nCyRkD44gEoXg5df2HDCi4i+U1JTuBPwbpHkDuik/S3a9ZSH1Hv+ploW+IwiU7WKxLmms R1TpMUO8XCNl5M+4VMXlLqWb2IpS/lzY1PI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V platform le= vel timer library Due to RISC-V timer CSR is platform implementation specific, RISC-V CPU DXE= driver invokes platform level timer library to access to timer CSRs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/Universal/CpuDxe/CpuDxe.c | 324 +++++++++++++++ RiscVPkg/Universal/CpuDxe/CpuDxe.h | 212 ++++++++++ RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 66 +++ RiscVPkg/Universal/CpuDxe/CpuDxe.uni | Bin 0 -> 1564 bytes RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | Bin 0 -> 1392 bytes RiscVPkg/Universal/CpuDxe/CpuMp.h | 648 ++++++++++++++++++++++++++= ++++ 6 files changed, 1250 insertions(+) create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni create mode 100644 RiscVPkg/Universal/CpuDxe/CpuMp.h diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe= /CpuDxe.c new file mode 100644 index 0000000..37d9bcf --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.c @@ -0,0 +1,324 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "CpuDxe.h" + +// +// Global Variables +// +BOOLEAN InterruptState =3D FALSE; +EFI_HANDLE mCpuHandle =3D NULL; +BOOLEAN mIsFlushingGCD; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + InterruptState =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + InterruptState =3D FALSE; + return EFI_SUCCESS; +} + + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D InterruptState; + return EFI_SUCCESS; +} + + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + if (TimerValue =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (TimerIndex !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + *TimerValue =3D (UINT64)RiscVReadMachineTimer (); + if (TimerPeriod !=3D NULL) { + *TimerPeriod =3D DivU64x32 ( + 1000000000000000u, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ); + } + return EFI_SUCCESS; +} + + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a:Set memory attributes not supported yet\n", __FU= NCTION__)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Machine mode handler is initiated in CpuExceptionHandlerLibConstructo= r in + // CpuExecptionHandlerLib. + // + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe= /CpuDxe.h new file mode 100644 index 0000000..00f40ff --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.h @@ -0,0 +1,212 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _CPU_DXE_H_ +#define _CPU_DXE_H_ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif + diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuD= xe/CpuDxe.inf new file mode 100644 index 0000000..93638e7 --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf @@ -0,0 +1,66 @@ +## @file +# RISC-V CPU DXE module. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CpuDxe + MODULE_UNI_FILE =3D CpuDxe.uni + FILE_GUID =3D 1A1E4886-9517-440e-9FDE-3BE44CEE2136 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializeCpu + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + CpuExceptionHandlerLib + TimerLib + SynchronizationLib + HobLib + ReportStatusCodeLib + RiscVCpuLib + RiscVPlatformTimerLib + +[Sources] + CpuDxe.c + CpuDxe.h + +[Protocols] + gEfiCpuArchProtocolGuid ## PRODUCES + +[Guids] + +[Ppis] + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + CpuDxeExtra.uni diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuD= xe/CpuDxe.uni new file mode 100644 index 0000000000000000000000000000000000000000..51e3c0c06df37e5abb4be67ca2b= c73d5da4cbdd2 GIT binary patch literal 1564 zcmb7^TW`}q5QXO%iT_}wFMyf^c;EpcMA90FfX2#&!c&!NYmwBI0`j|Aa5HH#WD_7B;ho_JG;u)<$+@nO)i1ay-uM!V3H!*~A`W zpW9P=3DW-siJ{(E-cI!56>iH-33Mw{D|_1G?%pE0^}tQGypj%jcB7anCvPhOFIw8R?N z7Ap&E6@BHSnQ4FSd#8B5vbOc?^_F*;M`Qyyr+7ymHzS7}PD{okVu@LShq#FE1RhH~ zwYFy8CH@gJqYd|z-U74=3DU-@bG0`H0Q7c=3D3O_}V?)M7W_ZrAIcV)xK+IpXlxd{daD-d9c;Cs*xjTOUQG-Y%Dl>#b`sq5VDE6gEPX8bL3`S}~UPV|bQvbuK|y z@t?C2&Pc4k0gs1%IVU)f-U5F}xBgscY|OTlR@@2US(6vIAy2)Y_0<>{<`)1RFCi zO#(u74jt}Kj7Q&*yYy7kYHL{G3blr9`&gsH9d@Uz3$^PJBRj>b=3Dgdx+?|>?du1D`N z5_ioh<^W&$C~EL}i?5=3D8#eQH#%yoC;O_Y#DY+trG6?z9P5-LkEkGXNBZl#UnGf!px+rtT`-2A#dZcG=3D_O@bs5OAkpS}Z5Q}^MViW$+W{!|lnu*9?mJ5@-* zs%mn@oX)EcZrwgJIwFT5wng3O9_TjB=3DoKJ_dz@f1#u>927&Xu2-?LFID4yabTmA3L c=3DZ71xlCjC;$Ke literal 0 HcmV?d00001 diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal= /CpuDxe/CpuDxeExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..e6201a906ae37cfb24a6b501d97= 89d28f15b96f7 GIT binary patch literal 1392 zcmZXU+iwz45XR@(#Q))hzNl$I`{08yMqpPh@Z*6WH_G4DExADE@?8?Uiv6!>-we381ZZ~)adj5-VJaRQXBsiy^Dbbqwk0cZ(GB`mXKr$`U{*wyUEEXr6rXzR49}0& zvVnan6{+|S;jC=3DI^R7Ti;k0C5D6qvts)_Fu9!orRw#(HDSjMi9SV+}PnMYA#6R;*k zi@%sj*#ckDvpmB+Yt?RS6Gp||5uwwRb-_f{NXh!NPGTm{1h2%`I$hBVRa}cIN9<3Z zajCR;a4n{c|KBztrx3*<(@VKF>~-r2Jd3=3DlOEBpw{@0vjH4^Jby!Kf=3DS0+<)hu0*J zU*#Hz)Aot7>a{Jk_~1RR{>apof9hJ-xqnJU8++<+uuR}Sv!lI}Iw&{1g(k(U`<8!K)$@$nH_0SsUF;oDh0*iu19svrn{p2El8>@xUSIH4>T}X^!Jf=3Dm$|xqPzL19E@sGz>2IaMDss^`=3DPNBE1MveiJ7c5STRu{FIv)W_<{DWf_@U#=3D>7 Q;n)$D#Qz^D@j@xye-~NTv;Y7A literal 0 HcmV?d00001 diff --git a/RiscVPkg/Universal/CpuDxe/CpuMp.h b/RiscVPkg/Universal/CpuDxe/= CpuMp.h new file mode 100644 index 0000000..adb3ef3 --- /dev/null +++ b/RiscVPkg/Universal/CpuDxe/CpuMp.h @@ -0,0 +1,648 @@ +/** @file + RISC-V CPU DXE MP definitions. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _CPU_MP_H_ +#define _CPU_MP_H_ + +#include +#include +#include +#include +#include +#include + +/** + Initialize Multi-processor support. + +**/ +VOID +InitializeMpSupport ( + VOID + ); + +typedef +VOID +(EFIAPI *STACKLESS_AP_ENTRY_POINT)( + VOID + ); + +/** + Starts the Application Processors and directs them to jump to the + specified routine. + + The processor jumps to this code in flat mode, but the processor's + stack is not initialized. + + @retval EFI_SUCCESS The APs were started + +**/ +EFI_STATUS +StartApsStackless ( + VOID + ); + +/** + The AP entry point that the Startup-IPI target code will jump to. + + The processor jumps to this code in flat mode, but the processor's + stack is not initialized. + +**/ +VOID +EFIAPI +AsmApEntryPoint ( + VOID + ); + +/** + Releases the lock preventing other APs from using the shared AP + stack. + + Once the AP has transitioned to using a new stack, it can call this + function to allow another AP to proceed with using the shared stack. + +**/ +VOID +EFIAPI +AsmApDoneWithCommonStack ( + VOID + ); + +typedef enum { + CpuStateIdle, + CpuStateBlocked, + CpuStateReady, + CpuStateBusy, + CpuStateFinished, + CpuStateSleeping +} CPU_STATE; + +/** + Define Individual Processor Data block. + +**/ +typedef struct { + EFI_PROCESSOR_INFORMATION Info; + SPIN_LOCK CpuDataLock; + INTN LockSelf; + volatile CPU_STATE State; + + volatile EFI_AP_PROCEDURE Procedure; + volatile VOID* Parameter; + BOOLEAN *Finished; + INTN Timeout; + EFI_EVENT WaitEvent; + BOOLEAN TimeoutActive; + EFI_EVENT CheckThisAPEvent; + VOID *TopOfStack; +} CPU_DATA_BLOCK; + +/** + Define MP data block which consumes individual processor block. + +**/ +typedef struct { + CPU_DATA_BLOCK *CpuDatas; + UINTN NumberOfProcessors; + UINTN NumberOfEnabledProcessors; + + EFI_AP_PROCEDURE Procedure; + VOID *ProcedureArgument; + UINTN StartCount; + UINTN FinishCount; + BOOLEAN SingleThread; + UINTN **FailedList; + UINTN FailedListIndex; + INTN Timeout; + EFI_EVENT WaitEvent; + BOOLEAN TimeoutActive; + EFI_EVENT CheckAllAPsEvent; +} MP_SYSTEM_DATA; + +/** + This function is called by all processors (both BSP and AP) once and col= lects MP related data. + + @param Bsp TRUE if the CPU is BSP + @param ProcessorNumber The specific processor number + + @retval EFI_SUCCESS Data for the processor collected and filled in + +**/ +EFI_STATUS +FillInProcessorInformation ( + IN BOOLEAN Bsp, + IN UINTN ProcessorNumber + ); + +/** + This service retrieves the number of logical processor in the platform + and the number of those logical processors that are enabled on this boot. + This service may only be called from the BSP. + + This function is used to retrieve the following information: + - The number of logical processors that are present in the system. + - The number of enabled logical processors in the system at the instant + this call is made. + + Because MP Service Protocol provides services to enable and disable proc= essors + dynamically, the number of enabled logical processors may vary during the + course of a boot session. + + If this service is called from an AP, then EFI_DEVICE_ERROR is returned. + If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then + EFI_INVALID_PARAMETER is returned. Otherwise, the total number of proces= sors + is returned in NumberOfProcessors, the number of currently enabled proce= ssor + is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_MP_SERVICES= _PROTOCOL + instance. + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL. + @retval EFI_INVALID_PARAMETER NumberOfEnabledProcessors is NULL. + +**/ +EFI_STATUS +EFIAPI +GetNumberOfProcessors ( + IN EFI_MP_SERVICES_PROTOCOL *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors + ); + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + This service retrieves detailed MP-related information about any process= or + on the platform. Note the following: + - The processor information may change during the course of a boot ses= sion. + - The information presented here is entirely MP related. + + Information regarding the number of caches and their sizes, frequency of= operation, + slot numbers is all considered platform-related information and is not p= rovided + by this service. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTO= COL + instance. + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + +**/ +EFI_STATUS +EFIAPI +GetProcessorInfo ( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + ); + +/** + This service executes a caller provided function on all enabled APs. APs= can + run either simultaneously or one at a time in sequence. This service sup= ports + both blocking and non-blocking requests. The non-blocking requests use E= FI + events so the BSP can detect when the APs have finished. This service ma= y only + be called from the BSP. + + This function is used to dispatch all the enabled APs to the function sp= ecified + by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned + immediately and Procedure is not started on any AP. + + If SingleThread is TRUE, all the enabled APs execute the function specif= ied by + Procedure one by one, in ascending order of processor handle number. Oth= erwise, + all the enabled APs execute the function specified by Procedure simultan= eously. + + If WaitEvent is NULL, execution is in blocking mode. The BSP waits until= all + APs finish or TimeoutInMicroseconds expires. Otherwise, execution is in = non-blocking + mode, and the BSP returns from this service without waiting for APs. If a + non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READ= Y_TO_BOOT + is signaled, then EFI_UNSUPPORTED must be returned. + + If the timeout specified by TimeoutInMicroseconds expires before all APs= return + from Procedure, then Procedure on the failed APs is terminated. All enab= led APs + are always available for further calls to EFI_MP_SERVICES_PROTOCOL.Start= upAllAPs() + and EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NU= LL, its + content points to the list of processor handle numbers in which Procedur= e was + terminated. + + Note: It is the responsibility of the consumer of the EFI_MP_SERVICES_PR= OTOCOL.StartupAllAPs() + to make sure that the nature of the code that is executed on the BSP and= the + dispatched APs is well controlled. The MP Services Protocol does not gua= rantee + that the Procedure function is MP-safe. Hence, the tasks that can be run= in + parallel are limited to certain independent tasks and well-controlled ex= clusive + code. EFI services and protocols may not be called by APs unless otherwi= se + specified. + + In blocking execution mode, BSP waits until all APs finish or + TimeoutInMicroseconds expires. + + In non-blocking execution mode, BSP is freed to return to the caller and= then + proceed to the next task without having to wait for APs. The following + sequence needs to occur in a non-blocking execution mode: + + -# The caller that intends to use this MP Services Protocol in non-blo= cking + mode creates WaitEvent by calling the EFI CreateEvent() service. T= he caller + invokes EFI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter = WaitEvent + is not NULL, then StartupAllAPs() executes in non-blocking mode. It= requests + the function specified by Procedure to be started on all the enable= d APs, + and releases the BSP to continue with other tasks. + -# The caller can use the CheckEvent() and WaitForEvent() services to = check + the state of the WaitEvent created in step 1. + -# When the APs complete their task or TimeoutInMicroSecondss expires,= the MP + Service signals WaitEvent by calling the EFI SignalEvent() function= . If + FailedCpuList is not NULL, its content is available when WaitEvent = is + signaled. If all APs returned from Procedure prior to the timeout, = then + FailedCpuList is set to NULL. If not all APs return from Procedure = before + the timeout, then FailedCpuList is filled in with the list of the f= ailed + APs. The buffer is allocated by MP Service Protocol using AllocateP= ool(). + It is the caller's responsibility to free the buffer with FreePool(= ) service. + -# This invocation of SignalEvent() function informs the caller that i= nvoked + EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs co= mpleted + the specified task or a timeout occurred. The contents of FailedCpu= List + can be examined to determine which APs did not complete the specifi= ed task + prior to the timeout. + + @param[in] This A pointer to the EFI_MP_SERVICES_PRO= TOCOL + instance. + @param[in] Procedure A pointer to the function to be run = on + enabled APs of the system. See type + EFI_AP_PROCEDURE. + @param[in] SingleThread If TRUE, then all the enabled APs ex= ecute + the function specified by Procedure = one by + one, in ascending order of processor= handle + number. If FALSE, then all the enab= led APs + execute the function specified by Pr= ocedure + simultaneously. + @param[in] WaitEvent The event created by the caller with= CreateEvent() + service. If it is NULL, then execut= e in + blocking mode. BSP waits until all A= Ps finish + or TimeoutInMicroseconds expires. I= f it's + not NULL, then execute in non-blocki= ng mode. + BSP requests the function specified = by + Procedure to be started on all the e= nabled + APs, and go on executing immediately= . If + all return from Procedure, or Timeou= tInMicroseconds + expires, this event is signaled. The= BSP + can use the CheckEvent() or WaitForE= vent() + services to check the state of event= . Type + EFI_EVENT is defined in CreateEvent(= ) in + the Unified Extensible Firmware Inte= rface + Specification. + @param[in] TimeoutInMicroseconds Indicates the time limit in microsec= onds for + APs to return from Procedure, either= for + blocking or non-blocking mode. Zero = means + infinity. If the timeout expires be= fore + all APs return from Procedure, then = Procedure + on the failed APs is terminated. All= enabled + APs are available for next function = assigned + by EFI_MP_SERVICES_PROTOCOL.StartupA= llAPs() + or EFI_MP_SERVICES_PROTOCOL.StartupT= hisAP(). + If the timeout expires in blocking m= ode, + BSP returns EFI_TIMEOUT. If the tim= eout + expires in non-blocking mode, WaitEv= ent + is signaled with SignalEvent(). + @param[in] ProcedureArgument The parameter passed into Procedure = for + all APs. + @param[out] FailedCpuList If NULL, this parameter is ignored. = Otherwise, + if all APs finish successfully, then= its + content is set to NULL. If not all A= Ps + finish before timeout expires, then = its + content is set to address of the buf= fer + holding handle numbers of the failed= APs. + The buffer is allocated by MP Servic= e Protocol, + and it's the caller's responsibility= to + free the buffer with FreePool() serv= ice. + In blocking mode, it is ready for co= nsumption + when the call returns. In non-blocki= ng mode, + it is ready when WaitEvent is signal= ed. The + list of failed CPU is terminated by + END_OF_CPU_LIST. + + @retval EFI_SUCCESS In blocking mode, all APs have finished = before + the timeout expired. + @retval EFI_SUCCESS In non-blocking mode, function has been = dispatched + to all enabled APs. + @retval EFI_UNSUPPORTED A non-blocking mode request was made aft= er the + UEFI event EFI_EVENT_GROUP_READY_TO_BOOT= was + signaled. + @retval EFI_DEVICE_ERROR Caller processor is AP. + @retval EFI_NOT_STARTED No enabled APs exist in the system. + @retval EFI_NOT_READY Any enabled APs are busy. + @retval EFI_TIMEOUT In blocking mode, the timeout expired be= fore + all enabled APs have finished. + @retval EFI_INVALID_PARAMETER Procedure is NULL. + +**/ +EFI_STATUS +EFIAPI +StartupAllAPs ( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL + ); + +/** + This service lets the caller get one enabled AP to execute a caller-prov= ided + function. The caller can request the BSP to either wait for the completi= on + of the AP or just proceed with the next task by using the EFI event mech= anism. + See EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blo= cking + execution support. This service may only be called from the BSP. + + This function is used to dispatch one enabled AP to the function specifi= ed by + Procedure passing in the argument specified by ProcedureArgument. If Wa= itEvent + is NULL, execution is in blocking mode. The BSP waits until the AP finis= hes or + TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking = mode. + BSP proceeds to the next task without waiting for the AP. If a non-block= ing mode + is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signa= led, + then EFI_UNSUPPORTED must be returned. + + If the timeout specified by TimeoutInMicroseconds expires before the AP = returns + from Procedure, then execution of Procedure by the AP is terminated. The= AP is + available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs= () and + EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). + + @param[in] This A pointer to the EFI_MP_SERVICES_PRO= TOCOL + instance. + @param[in] Procedure A pointer to the function to be run = on + enabled APs of the system. See type + EFI_AP_PROCEDURE. + @param[in] ProcessorNumber The handle number of the AP. The ran= ge is + from 0 to the total number of logical + processors minus 1. The total number= of + logical processors can be retrieved = by + EFI_MP_SERVICES_PROTOCOL.GetNumberOf= Processors(). + @param[in] WaitEvent The event created by the caller with= CreateEvent() + service. If it is NULL, then execut= e in + blocking mode. BSP waits until all A= Ps finish + or TimeoutInMicroseconds expires. I= f it's + not NULL, then execute in non-blocki= ng mode. + BSP requests the function specified = by + Procedure to be started on all the e= nabled + APs, and go on executing immediately= . If + all return from Procedure or Timeout= InMicroseconds + expires, this event is signaled. The= BSP + can use the CheckEvent() or WaitForE= vent() + services to check the state of event= . Type + EFI_EVENT is defined in CreateEvent(= ) in + the Unified Extensible Firmware Inte= rface + Specification. + @param[in] TimeoutInMicroseconds Indicates the time limit in microsec= onds for + APs to return from Procedure, either= for + blocking or non-blocking mode. Zero = means + infinity. If the timeout expires be= fore + all APs return from Procedure, then = Procedure + on the failed APs is terminated. All= enabled + APs are available for next function = assigned + by EFI_MP_SERVICES_PROTOCOL.StartupA= llAPs() + or EFI_MP_SERVICES_PROTOCOL.StartupT= hisAP(). + If the timeout expires in blocking m= ode, + BSP returns EFI_TIMEOUT. If the tim= eout + expires in non-blocking mode, WaitEv= ent + is signaled with SignalEvent(). + @param[in] ProcedureArgument The parameter passed into Procedure = for + all APs. + @param[out] Finished If NULL, this parameter is ignored. = In + blocking mode, this parameter is ign= ored. + In non-blocking mode, if AP returns = from + Procedure before the timeout expires= , its + content is set to TRUE. Otherwise, t= he + value is set to FALSE. The caller can + determine if the AP returned from Pr= ocedure + by evaluating this value. + + @retval EFI_SUCCESS In blocking mode, specified AP finished = before + the timeout expires. + @retval EFI_SUCCESS In non-blocking mode, the function has b= een + dispatched to specified AP. + @retval EFI_UNSUPPORTED A non-blocking mode request was made aft= er the + UEFI event EFI_EVENT_GROUP_READY_TO_BOOT= was + signaled. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_TIMEOUT In blocking mode, the timeout expired be= fore + the specified AP has finished. + @retval EFI_NOT_READY The specified AP is busy. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or dis= abled AP. + @retval EFI_INVALID_PARAMETER Procedure is NULL. + +**/ +EFI_STATUS +EFIAPI +StartupThisAP ( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL + ); + +/** + This service switches the requested AP to be the BSP from that point onw= ard. + This service changes the BSP for all purposes. This call can only be p= erformed + by the current BSP. + + This service switches the requested AP to be the BSP from that point onw= ard. + This service changes the BSP for all purposes. The new BSP can take over= the + execution of the old BSP and continue seamlessly from where the old one = left + off. This service may not be supported after the UEFI Event EFI_EVENT_GR= OUP_READY_TO_BOOT + is signaled. + + If the BSP cannot be switched prior to the return from this service, then + EFI_UNSUPPORTED must be returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL i= nstance. + @param[in] ProcessorNumber The handle number of AP that is to become t= he new + BSP. The range is from 0 to the total numbe= r of + logical processors minus 1. The total numbe= r of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcess= ors(). + @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as= an + enabled AP. Otherwise, it will be disabled. + + @retval EFI_SUCCESS BSP successfully switched. + @retval EFI_UNSUPPORTED Switching the BSP cannot be completed pr= ior to + this service returning. + @retval EFI_UNSUPPORTED Switching the BSP is not supported. + @retval EFI_SUCCESS The calling processor is an AP. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BS= P or + a disabled AP. + @retval EFI_NOT_READY The specified AP is busy. + +**/ +EFI_STATUS +EFIAPI +SwitchBSP ( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP + ); + +/** + This service lets the caller enable or disable an AP from this point onw= ard. + This service may only be called from the BSP. + + This service allows the caller enable or disable an AP from this point o= nward. + The caller can optionally specify the health status of the AP by Health.= If + an AP is being disabled, then the state of the disabled AP is implementa= tion + dependent. If an AP is enabled, then the implementation must guarantee t= hat a + complete initialization sequence is performed on the AP, so the AP is in= a state + that is compatible with an MP operating system. This service may not be = supported + after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled. + + If the enable or disable AP operation cannot be completed prior to the r= eturn + from this service, then EFI_UNSUPPORTED must be returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL i= nstance. + @param[in] ProcessorNumber The handle number of AP that is to become t= he new + BSP. The range is from 0 to the total numbe= r of + logical processors minus 1. The total numbe= r of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcess= ors(). + @param[in] EnableAP Specifies the new state for the processor f= or + enabled, FALSE for disabled. + @param[in] HealthFlag If not NULL, a pointer to a value that spec= ifies + the new health status of the AP. This flag + corresponds to StatusFlag defined in + EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo()= . Only + the PROCESSOR_HEALTH_STATUS_BIT is used. Al= l other + bits are ignored. If it is NULL, this para= meter + is ignored. + + @retval EFI_SUCCESS The specified AP was enabled or disabled= successfully. + @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be co= mpleted + prior to this service returning. + @retval EFI_UNSUPPORTED Enabling or disabling an AP is not suppo= rted. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND Processor with the handle specified by P= rocessorNumber + does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP. + +**/ +EFI_STATUS +EFIAPI +EnableDisableAP ( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL + ); + +/** + This return the handle number for the calling processor. This service m= ay be + called from the BSP and APs. + + This service returns the processor handle number for the calling process= or. + The returned value is in the range from 0 to the total number of logical + processors minus 1. The total number of logical processors can be retrie= ved + with EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may = be + called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALI= D_PARAMETER + is returned. Otherwise, the current processors handle number is returned= in + ProcessorNumber, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL i= nstance. + @param[out] ProcessorNumber The handle number of AP that is to become t= he new + BSP. The range is from 0 to the total numbe= r of + logical processors minus 1. The total numbe= r of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcess= ors(). + + @retval EFI_SUCCESS The current processor handle number was = returned + in ProcessorNumber. + @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL. + +**/ +EFI_STATUS +EFIAPI +WhoAmI ( + IN EFI_MP_SERVICES_PROTOCOL *This, + OUT UINTN *ProcessorNumber + ); + +/** + Terminate AP's task and set it to idle state. + + This function terminates AP's task due to timeout by sending INIT-SIPI, + and sends it to idle state. + + @param CpuData the pointer to CPU_DATA_BLOCK of specified AP + +**/ +VOID +ResetProcessorToIdleState ( + IN CPU_DATA_BLOCK *CpuData + ); + +/** + Prepares Startup Code for APs. + This function prepares Startup Code for APs. + + @retval EFI_SUCCESS The APs were started + @retval EFI_OUT_OF_RESOURCES Cannot allocate memory to start APs + +**/ +EFI_STATUS +PrepareAPStartupCode ( + VOID + ); + +/** + Free the code buffer of startup AP. + +**/ +VOID +FreeApStartupCode ( + VOID + ); + +/** + Resets the Application Processor and directs it to jump to the + specified routine. + + The processor jumps to this code in flat mode, but the processor's + stack is not initialized. + + @param ProcessorId the AP of ProcessorId was reset +**/ +VOID +ResetApStackless ( + IN UINT32 ProcessorId + ); + +#endif // _CPU_MP_H_ + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46793): https://edk2.groups.io/g/devel/message/46793 Mute This Topic: https://groups.io/mt/33137143/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46794+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46794+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595628; cv=none; d=zoho.com; s=zohoarc; b=aYaDM1yffyU/dSElK42R0mT7h5s2Ds0wnUIAjJ/3YqMb4WlYCshArqM2+tnHV5G8BP6BHcqm4VgowDRlQSHfOQVA327hmOw/R2A4ORHW43QOpRrxrBOwK3SGL0pPZqFWGZUFTJEYG/ZCNW+ZdBgafOPjs1AtNP3HBkoXmaXgp7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595628; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=9J8scwWcQ5DymZr6d9LmO5Go6VFobXtw9dL3NB0Vf5Y=; b=AQjkiR5Y7KlOa8cuPdVxLjvZOHr0lcIbTLwWzxQhdIGkZarSj97hhGbGA7FwzG1+P5BLaHRlSXGyFUfMSIacX87hafe8zh9zSQ8kYnmSeRcmWEolgZx9dLelU68bDiLP9yzgaF8bDvIVnZvuy1IQ+Pc3HucJkscwN6iE+CMdtRU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46794+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595628691169.62167753340566; Wed, 4 Sep 2019 04:13:48 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:48 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBjSZ010417 for ; Wed, 4 Sep 2019 11:13:47 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usgabm564-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:46 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 6745DB0 for ; Wed, 4 Sep 2019 11:13:46 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 7DFEC39; Wed, 4 Sep 2019 11:13:45 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 17/22]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS DXE driver Date: Wed, 4 Sep 2019 18:43:12 +0800 Message-Id: <1567593797-26216-18-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595628; bh=2BsC1Kp6LALG4AtW2px9XlsgPaI6OGzJsoKmob3jis4=; h=Cc:Date:From:Reply-To:Subject:To; b=m+NyaBJmVzuM2U4jIPoXNL8+LXHUeVpM43rd7pmemyBTQMBYyazdys3xBYrgyeSINka Y33ylJeL0xW65eSHN33IfKuLppUD0jvtxRYFLtP6Sz719Cc45PEF96NmjHStLnzZCYuTG 0DsckTzy+fNIfKTxbC31KN1R/tKqfLjGQ88= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7 and = type 44 records. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 343 +++++++++++++++++= ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 38 +++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 63 ++++ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | Bin 0 -> 1542 bytes .../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | Bin 0 -> 1438 bytes 5 files changed, 444 insertions(+) create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.c new file mode 100644 index 0000000..b59af1a --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -0,0 +1,343 @@ +/** @file + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and t= ype 44 records. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "RiscVSmbiosDxe.h" + +#define RISCV_SMBIOS_DEBUG_INFO 1 + +EFI_SMBIOS_PROTOCOL *Smbios; + +/** + This function builds SMBIOS type 7 record according to=20 + the given RISC_V_PROCESSOR_TYPE7_DATA_HOB. + =20 + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB =20 + @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_DATA_HOB + @param SmbiosHandle Pointer to SMBIOS_HANDLE + =20 + @retval EFI_STATUS + +**/ +static +EFI_STATUS +BuildSmbiosType7 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + IN RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob, + OUT SMBIOS_HANDLE *SmbiosHandle +) +{ + EFI_STATUS Status; + SMBIOS_HANDLE Handle; + + if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob->PrcessorGu= id) || + Type4DataHob->ProcessorUid !=3D Type7DataHob->ProcessorUid) { + return EFI_INVALID_PARAMETER; + } + Handle =3D SMBIOS_HANDLE_PI_RESERVED; + Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMATIO= N;=20 + Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE7); + Type7DataHob->SmbiosType7Cache.Hdr.Handle =3D 0; + Status =3D Smbios->Add (Smbios, NULL, &Handle, &Type7DataHob->SmbiosType= 7Cache.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type= 7\n")); + return Status; + } + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was added. S= MBIOS Handle: 0x%x\n", Handle)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((EFI_D_INFO, " Cache belone to processor = GUID: %g\n", &Type7DataHob->PrcessorGuid)); + DEBUG ((EFI_D_INFO, " Cache belone processor UI= D: %d\n", Type7DataHob->ProcessorUid)); + DEBUG ((EFI_D_INFO, " =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((EFI_D_INFO, " Socket Designation: %d\n",= Type7DataHob->SmbiosType7Cache.SocketDesignation)); + DEBUG ((EFI_D_INFO, " Cache Configuration: 0x%x\= n", Type7DataHob->SmbiosType7Cache.CacheConfiguration)); + DEBUG ((EFI_D_INFO, " Maximum Cache Size: 0x%x\n= ", Type7DataHob->SmbiosType7Cache.MaximumCacheSize)); + DEBUG ((EFI_D_INFO, " Installed Size: 0x%x\n", T= ype7DataHob->SmbiosType7Cache.InstalledSize)); + DEBUG ((EFI_D_INFO, " Supported SRAM Type: 0x%x\= n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType)); + DEBUG ((EFI_D_INFO, " Current SRAMT ype: 0x%x\n"= , Type7DataHob->SmbiosType7Cache.CurrentSRAMType)); + DEBUG ((EFI_D_INFO, " Cache Speed: 0x%x\n", Type= 7DataHob->SmbiosType7Cache.CacheSpeed)); + DEBUG ((EFI_D_INFO, " Error Correction Type: 0x%= x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType)); + DEBUG ((EFI_D_INFO, " System Cache Type: 0x%x\n"= , Type7DataHob->SmbiosType7Cache.SystemCacheType)); + DEBUG ((EFI_D_INFO, " Associativity: 0x%x\n", Ty= pe7DataHob->SmbiosType7Cache.Associativity)); +#endif + + *SmbiosHandle =3D Handle; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 4 record according to=20 + the given RISC_V_PROCESSOR_TYPE4_DATA_HOB. + + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB + @param SmbiosHandle Pointer to SMBIOS_HANDLE + =20 + @retval EFI_STATUS + +**/ +static +EFI_STATUS +BuildSmbiosType4 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + OUT SMBIOS_HANDLE *SmbiosHandle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData; + SMBIOS_HANDLE Cache; + SMBIOS_HANDLE Processor; + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: Building Type 4.\n")); + DEBUG ((EFI_D_INFO, " Processor GUID: %g\n", &Ty= pe4DataHob->PrcessorGuid)); + DEBUG ((EFI_D_INFO, " Processor UUID: %d\n", Typ= e4DataHob->ProcessorUid)); + + Type4DataHob->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4DataHob->SmbiosType4Processor.L2CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + Type4DataHob->SmbiosType4Processor.L3CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED; + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType7GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS Type7 = data HOB found.\n")); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processo= rs. + // + do { + Type7HobData =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)GET_GUID_HOB_DATA = (GuidHob); + Status =3D BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache); + if (EFI_ERROR (Status)) { + return Status; + } + if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CON= FIGURATION_CACHE_LEVEL_MASK) =3D=3D=20 + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) { + Type4DataHob->SmbiosType4Processor.L1CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=20 + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) { + Type4DataHob->SmbiosType4Processor.L2CacheHandle =3D Cache; + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=20 + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) { + Type4DataHob->SmbiosType4Processor.L3CacheHandle =3D Cache; + } else { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Improper cache level = of SMBIOS handle %d\n", Cache)); + } + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e7GuidHobGuid), GET_NEXT_HOB(GuidHob));=20 + } while (GuidHob !=3D NULL); + + // + // Build SMBIOS Type 4 record + // + Processor =3D SMBIOS_HANDLE_PI_RESERVED; + Type4DataHob->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_IN= FORMATION;=20 + Type4DataHob->SmbiosType4Processor.Hdr.Length =3D sizeof(SMBIOS_TABLE_TY= PE4); + Type4DataHob->SmbiosType4Processor.Hdr.Handle =3D 0; + Status =3D Smbios->Add (Smbios, NULL, &Processor, &Type4DataHob->SmbiosT= ype4Processor.Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type= 4\n")); + return Status; + } + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was added. S= MBIOS Handle: 0x%x\n", Processor)); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((EFI_D_INFO, " Socket StringID: %d\n", Ty= pe4DataHob->SmbiosType4Processor.Socket)); + DEBUG ((EFI_D_INFO, " Processor Type: 0x%x\n", T= ype4DataHob->SmbiosType4Processor.ProcessorType)); + DEBUG ((EFI_D_INFO, " Processor Family: 0x%x\n",= Type4DataHob->SmbiosType4Processor.ProcessorFamily)); + DEBUG ((EFI_D_INFO, " Processor Manufacture Stri= ngID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture)); + DEBUG ((EFI_D_INFO, " Processor Id: 0x%x:0x%x\n"= , \ + Type4DataHob->SmbiosType4Processor.ProcessorId.Signature, Type4D= ataHob->SmbiosType4Processor.ProcessorId.FeatureFlags)); + DEBUG ((EFI_D_INFO, " Processor Version StringID= : %d\n", Type4DataHob->SmbiosType4Processor.ProcessorVersion)); + DEBUG ((EFI_D_INFO, " Voltage: 0x%x\n", Type4Dat= aHob->SmbiosType4Processor.Voltage)); + DEBUG ((EFI_D_INFO, " External Clock: 0x%x\n", T= ype4DataHob->SmbiosType4Processor.ExternalClock)); + DEBUG ((EFI_D_INFO, " Max Speed: 0x%x\n", Type4D= ataHob->SmbiosType4Processor.MaxSpeed)); + DEBUG ((EFI_D_INFO, " Current Speed: 0x%x\n", Ty= pe4DataHob->SmbiosType4Processor.CurrentSpeed)); + DEBUG ((EFI_D_INFO, " Status: 0x%x\n", Type4Data= Hob->SmbiosType4Processor.Status)); + DEBUG ((EFI_D_INFO, " ProcessorUpgrade: 0x%x\n",= Type4DataHob->SmbiosType4Processor.ProcessorUpgrade)); + DEBUG ((EFI_D_INFO, " L1 Cache Handle: 0x%x\n", = Type4DataHob->SmbiosType4Processor.L1CacheHandle)); + DEBUG ((EFI_D_INFO, " L2 Cache Handle: 0x%x\n",T= ype4DataHob->SmbiosType4Processor.L2CacheHandle)); + DEBUG ((EFI_D_INFO, " L3 Cache Handle: 0x%x\n", = Type4DataHob->SmbiosType4Processor.L3CacheHandle)); + DEBUG ((EFI_D_INFO, " Serial Number StringID: %d= \n", Type4DataHob->SmbiosType4Processor.SerialNumber)); + DEBUG ((EFI_D_INFO, " Asset Tag StringID: %d\n",= Type4DataHob->SmbiosType4Processor.AssetTag)); + DEBUG ((EFI_D_INFO, " Part Number StringID: %d\n= ", Type4DataHob->SmbiosType4Processor.PartNumber)); + DEBUG ((EFI_D_INFO, " Core Count: %d\n", Type4Da= taHob->SmbiosType4Processor.CoreCount)); + DEBUG ((EFI_D_INFO, " Enabled CoreCount: %d\n", = Type4DataHob->SmbiosType4Processor.EnabledCoreCount)); + DEBUG ((EFI_D_INFO, " Thread Count: %d\n", Type4= DataHob->SmbiosType4Processor.ThreadCount)); + DEBUG ((EFI_D_INFO, " Processor Characteristics:= 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics)); + DEBUG ((EFI_D_INFO, " Processor Family2: 0x%x\n"= , Type4DataHob->SmbiosType4Processor.ProcessorFamily2)); + DEBUG ((EFI_D_INFO, " Core Count 2: %d\n", Type4= DataHob->SmbiosType4Processor.CoreCount2)); + DEBUG ((EFI_D_INFO, " Enabled CoreCount : %d\n",= Type4DataHob->SmbiosType4Processor.EnabledCoreCount2)); + DEBUG ((EFI_D_INFO, " Thread Count 2: %d\n", Typ= e4DataHob->SmbiosType4Processor.ThreadCount2)); +#endif + + *SmbiosHandle =3D Processor; + return EFI_SUCCESS; +} + +/** + This function builds SMBIOS type 44 record according.. + + @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB=20 + @param Type4Handle SMBIOS handle of type 4 + + @retval EFI_STATUS + +**/ +EFI_STATUS +BuildSmbiosType44 ( + IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob, + IN SMBIOS_HANDLE Type4Handle + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData; + SMBIOS_HANDLE RiscVType44; + SMBIOS_TABLE_TYPE44 *Type44Ptr; + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: Building Type 44 for...\n"= )); +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((EFI_D_INFO, " Processor GUID: %g\n", &Ty= pe4DataHob->PrcessorGuid)); + DEBUG ((EFI_D_INFO, " Processor UUID: %d\n", Typ= e4DataHob->ProcessorUid)); +#endif + + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC_V_PROCESSOR_SPE= CIFIC_DATA_HOB found.\n")); + return EFI_NOT_FOUND; + } + // + // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for multiple cores. + // + do { + ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)GET_GU= ID_HOB_DATA (GuidHob); + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4Da= taHob->PrcessorGuid) || + ProcessorSpecificData->ParentProcessorUid !=3D Type4DataHob->Process= orUid) { + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + if (GuidHob =3D=3D NULL) { + break; + } + continue;=20 + } + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((EFI_D_INFO, "[ =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"= )); + DEBUG ((EFI_D_INFO, "[ Core GUID: %g\n", &Proce= ssorSpecificData->CoreGuid)); +#endif + + Type44Ptr =3D AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SM= BIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));=20 + if (Type44Ptr =3D=3D NULL) { + return EFI_NOT_FOUND; + } + Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION; + Type44Ptr->Hdr.Handle =3D 0; + Type44Ptr->Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA); + Type44Ptr->RefHandle =3D Type4Handle;=20 + Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof(RISC_V_PROCESSOR_S= PECIFIC_DATA_HOB); + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =3D Type4DataHob->= SmbiosType4Processor.ProcessorFamily2 -=20 + ProcessorFamilyR= iscvRV32 + \ + ProcessorSpecifi= cBlockArchTypeRiscVRV32; + CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->Proc= essorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA)); + +#if RISCV_SMBIOS_DEBUG_INFO + DEBUG ((EFI_D_INFO, "[ Core type: %d\n", Type44= Ptr->ProcessorSpecificBlock.ProcessorArchType)); + DEBUG ((EFI_D_INFO, " HartId =3D 0x%x\n", ((= SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L)= ); + DEBUG ((EFI_D_INFO, " Is Boot Hart? =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId= )); + DEBUG ((EFI_D_INFO, " PrivilegeModeSupported= =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->P= rivilegeModeSupported)); + DEBUG ((EFI_D_INFO, " MModeExcepDelegation = =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MM= odeExcepDelegation.Value64_L)); + DEBUG ((EFI_D_INFO, " MModeInterruptDelegati= on =3D 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))-= >MModeInterruptDelegation.Value64_L)); + DEBUG ((EFI_D_INFO, " HartXlen =3D 0x%x\n", = ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen)); + DEBUG ((EFI_D_INFO, " MachineModeXlen =3D 0x= %x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineM= odeXlen)); + DEBUG ((EFI_D_INFO, " SupervisorModeXlen =3D= 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->Super= visorModeXlen)); + DEBUG ((EFI_D_INFO, " UserModeXlen =3D 0x%x\= n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXle= n)); + DEBUG ((EFI_D_INFO, " InstSetSupported =3D 0= x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSet= Supported)); + DEBUG ((EFI_D_INFO, " MachineVendorId =3D 0x= %x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineV= endorId.Value64_L)); + DEBUG ((EFI_D_INFO, " MachineArchId =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArc= hId.Value64_L)); + DEBUG ((EFI_D_INFO, " MachineImplId =3D 0x%x= \n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImp= lId.Value64_L)); +#endif + + // + // Add to SMBIOS table. + // + RiscVType44 =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Ty= pe 44\n")); + return Status; + } + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was added= . SMBIOS Handle: 0x%x\n", RiscVType44)); + + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificD= ataGuidHobGuid), GET_NEXT_HOB(GuidHob)); + } while (GuidHob !=3D NULL); + return EFI_SUCCESS; +} + +/** + Entry point of RISC-V SMBIOS builder. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +RiscVSmbiosBuilderEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData; + SMBIOS_HANDLE Processor; + + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: %a entry\n", __FUNCTION__)= ); + + Status =3D gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&Smbios + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS Protocol = fail\n")); + return Status; + } + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType4GuidHobGuid)); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS inform= ation found.\n")); + return EFI_NOT_FOUND; + } + Type4HobData =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)GET_GUID_HOB_DATA (G= uidHob); + Status =3D EFI_NOT_FOUND; + // + // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processo= rs. + // + do { + Status =3D BuildSmbiosType4 (Type4HobData, &Processor); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type= 4 created.\n")); + ASSERT (FALSE); + } + Status =3D BuildSmbiosType44 (Type4HobData, Processor); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type= 44 found.\n")); + ASSERT (FALSE); + } + =20 + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e4GuidHobGuid), GET_NEXT_HOB(GuidHob));=20 + } while (GuidHob !=3D NULL); + DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: %a exit\n", __FUNCTION__)); + return Status;=20 +} + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Unive= rsal/SmbiosDxe/RiscVSmbiosDxe.h new file mode 100644 index 0000000..9f7577f --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h @@ -0,0 +1,38 @@ +/** @file + RISC-V SMBIOS Builder DXE module header file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _RISC_V_SMBIOS_DXE_H_ +#define _RISC_V_SMBIOS_DXE_H_ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#endif + diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.inf new file mode 100644 index 0000000..5624226 --- /dev/null +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf @@ -0,0 +1,63 @@ +## @file +# RISC-V SMBIOS DXE module. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVSmbiosDxe + MODULE_UNI_FILE =3D RiscVSmbiosDxe.uni + FILE_GUID =3D 5FC01647-AADD-42E1-AD99-DF4CB89F5A92 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D RiscVSmbiosBuilderEntry + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + HobLib + +[Sources] + RiscVSmbiosDxe.c + RiscVSmbiosDxe.h + +[Protocols] + gEfiSmbiosProtocolGuid # Consumed + +[Guids] + + +[Pcd] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + +[Depex] + gEfiSmbiosProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVSmbiosDxeExtra.uni diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Uni= versal/SmbiosDxe/RiscVSmbiosDxe.uni new file mode 100644 index 0000000000000000000000000000000000000000..e35ce629d3c92f24ef55f9ac136= 059716f2a81bb GIT binary patch literal 1542 zcmb7^TW`}q6ok(+68~Y9z5r?yK$Q>(A(GZW1k_gIPh&L zTh?8I4~z`g+A~^n*lK?5Ppjvk$F5(>#9Q%e^<*94nzo!C+K5u?zPSqRrB+hHDZ(-rC*9w(3kfkbXIY7E~T&1 zKVzmmBdPulYFE|o&XjK6f*Se$XY8T$K$=3D!t&MMbdoW%>zNM)h2qi}rgUN>pyoKS1W z{eqDZ$cY{7%rs%S;IBQYTPZmlp(`PiVtY&3wvY6?xT;K5oif@b*9NpA_j+I_)Dh$I zq-3biq09Y=3DK=3DhqCrlp)#*`OA$SR2$G@2j`JrS6n@vBn-T*eR%7RrD{^@0pQu-Q8#%rQAhipEo=3D;dlxSfGD|U!xp9?mRUP~-DPIna z>EGMrPkE0@|IT2F;TXUc*%^xDmz-_mR*If~eS4gy?!!45Go)1hDJKr#lF|koa`1?e zPxKSAW9gYvc;4ua^@-jA75j<~OuCP{pE>LArd;Q)Xo{L_y#AZ||0}PRggfsd<*m}~ a2zKb_`OM2hdU`ph{;KH}E;zS(kG}wCE9rRv literal 0 HcmV?d00001 diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPk= g/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..ccfdb2aa9e6bb05715d27beb7c5= d1edec7aca7cf GIT binary patch literal 1438 zcmZ{kTW=3DFV42AuS#D5s2FM!$vcmp9s(kwKhO`=3D@5JXN`nbVY93q%Gmc1K;uPWR(J1 z?Tp9cIX?E-^ZQrLY8LpP@dbNlGfQn@-|VqHLaV)=3DwXARFc4nVg_3g?UXgWv%>DKM1 zoXA*T+S(>I0wJ}Z=3D%#*R$6jhHo7LY*)6!N@MgF=3DX`%-dp|q38*G9-0sSfS zOM7lF?3JA&Ux0A$oOf>1#lytDGiL55DZFI1ajY%&!J3SB{0mrYY>6ZmilA#%<~lnI zW--sbi+hHh&S!phisc(}(6hJy;6H$K>JiKD8k7u9OHg74c36mu_)f4`!bE%fB3l8? z2v+i!A}v5G^P~85TDhJet(=3D)M8}W5oHzUm*zixJ9V@Bz2IT7zIGRb`{opnSJGg+oE zNnKVZ)>KMBlSj~?8k(#xkGPav?>!e2#=3DoOYVIxFg<@u7YEo((RhG+DvdkHoue9qX( z??|kFVD*sIac1&t?y(ws{4-+6b0AJ-1qSd{NgI3Z9iaNivn%_|b6w?Z#*NkUH zXwh8>7JWzVAgQ7?R+#$*dWE^+Yxy`ma0~Vsuj18lk6PF9BxY^&El`Egaqm4=3D;x3(h z4zQAqyyjN#vDL}1%pchib9HV~c*&zk?8^bCL~oIcE_EfJP5Le7EzZGTuA1wmJ2_O2 z-W$DF%H4I5-7YA-Lj>1gcR(G2pJ3C5 (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595631137303.8775661103963; Wed, 4 Sep 2019 04:13:51 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:49 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBfPI020087 for ; Wed, 4 Sep 2019 11:13:48 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7y2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:48 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id BA5FEAE for ; Wed, 4 Sep 2019 11:13:47 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D19F839; Wed, 4 Sep 2019 11:13:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 18/22]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Date: Wed, 4 Sep 2019 18:43:13 +0800 Message-Id: <1567593797-26216-19-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595630; bh=YStOs07AaCSxtOEu4BS89pR+Bj5m1XHZ1XLneL1FuEw=; h=Cc:Date:From:Reply-To:Subject:To; b=UMrkdildPk+YalCOu3veG0FAc/8r1R7VI9AxxiPv1epUNELFc/mO8CLwBM4mseWDx/3 OMnyQQJJmKK7sIyH/JbXEECrRIKuWqfH0E4rWcPoIWjbGac2VWZYPACOodIbm2O/oaDZe RtgT1a4zqqavTcuflGjREvVAR5KAxwNcibk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RiscVCpuLib: Add RISC-V CPU Library. - This library provides CSR assembly functions to read/write RISC-V specifi= c Control and Status registers. RiscVDxeIplHandoffLib RiscVDxeIplHandoffOpenSbiLib - Provide DxeIpl platform implementation-specifc library for RISC-V platfor= m. Two libraries are provided in this commit, * Defualt library which simply switch stack and transfer control to DXE core. * Switch stack, privilege mode and then transfer control to DXE core through RISC-V opensbi. RiscvOpensbiLib - EDK2 RISC-V OpenSBI library which pull in external source files under Ris= cVPkg/opensbi to the build process. PeiServicesTablePointerLibOpenSbi - Library instance of PEI Service Table for RISC-V platform based on OpenSB= I. RiscVPlatformTempMemoryInitLibNull - NULL lib to return temporary memory information. RiscVDxeIplHandoffOpenSbiLib - This is the instance of platform level DXE IPL library based on RISC-V Op= enSBI implementation. RiscVExceptionLib - Initial RISC-V Supervisor Mode trap handler RiscVTimerLib - Add RiscVTimerLib library. - Due to RISC-V timer CSR is platform implementation specific, RISC-V timer= library invokes platform level timer library mputo access to timer CSRs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../PeiServicesTablePointerLibOpenSbi.inf | 45 +++++ .../PeiServicesTablePointerLibOpenSbi.uni | Bin 0 -> 2462 bytes .../PeiServicesTablePointerOpenSbi.c | 127 +++++++++++++ RiscVPkg/Library/RiscVCpuLib/Cpu.s | 121 +++++++++++++ RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 46 +++++ .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 47 +++++ .../RiscVDxeIplHandoffLib.inf | 39 ++++ .../RiscVDxeIplHandoffOpenSbiLib.c | 108 +++++++++++ .../RiscVDxeIplHandoffOpenSbiLib.inf | 39 ++++ .../RiscVExceptionLib/CpuExceptionHandler.s | 94 ++++++++++ .../CpuExceptionHandlerDxeLib.inf | 47 +++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 187 +++++++++++++++++= ++ .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | Bin 0 -> 1516 bytes .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 65 +++++++ .../RiscVPlatformTempMemoryInitLibNull.inf | 42 +++++ .../Riscv64/TempMemInit.s | 31 ++++ .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 40 ++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 201 +++++++++++++++++= ++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 26 +++ 19 files changed, 1305 insertions(+) create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerLibOpenSbi.inf create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerLibOpenSbi.uni create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiS= ervicesTablePointerOpenSbi.c create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.s create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHando= ffLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHando= ffLib.inf create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeI= plHandoffOpenSbiLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeI= plHandoffOpenSbiLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerD= xeLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerL= ib.c create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerL= ib.uni create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Ris= cVPlatformTempMemoryInitLibNull.inf create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Ris= cv64/TempMemInit.s create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServices= TablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpe= nSbi/PeiServicesTablePointerLibOpenSbi.inf new file mode 100644 index 0000000..c49377b --- /dev/null +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePo= interLibOpenSbi.inf @@ -0,0 +1,45 @@ +## @file +# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI Firm= wareContext. +# +# PEI Services Table Pointer Library implementation that retrieves a poin= ter to the +# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context = structure. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiServicesTablePointerLibOpenSbi + MODULE_UNI_FILE =3D PeiServicesTablePointerLibOpenSbi.uni + FILE_GUID =3D B4054E46-FE75-4290-B442-4836B1265D8F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiServicesTablePointerLib|PEIM PEI_C= ORE + + CONSTRUCTOR =3D PeiServicesTablePointerLibOpenSbiCons= tructor + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PeiServicesTablePointerOpenSbi.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[Pcd] + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServices= TablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpe= nSbi/PeiServicesTablePointerLibOpenSbi.uni new file mode 100644 index 0000000000000000000000000000000000000000..e7a0c4702e4b6db9a4dd433d212= f34195baf6290 GIT binary patch literal 2462 zcmchZ+iwy<6vof9iT}fdzNl$IebX2tSZaw{2&Gn^8tx@>%d)igpI3k18J2}wZDXn- zyR$QMF5i6TGW_^nvXTX!C;WoFv4M?jY<+uZ4_Ga&$6z&^+QL$6Gj@>(HbXjC!>a5B zJ7z7h3-qx_#tkE4$yYUR)#2PHj3*R@C1C`#@7O#M|S4eg?NCb_zNEEO(p}8+vGBMyc1&6MQ`aR zyNO>#U``Zu<{>T&23`z7ganzZW7`-0aSzhW)u}U+&3U##4s_HMtl4HGeF1oybJ*_fY7G*2)C12_Z z;=3DV(MWPTNw){3(M>oG#YtQx(JX`7b-yKV0Y9cM)O8W|9xbc0uAT1q5ddZ$tjMs6ja z`00x1Cd9LJjr#>F9gz3vG27mYSUKm(^IRu6BsW!?O}f!L-evp9TwO}}sj=3Dlg@6KIz`n!ukGa4YjDvZpX76Y zgSR}VbhpHtL~D9>)>#v)C-QfOr8+iFuvVpGl{tIdDZ^F^1i$<3c)iHhk{lU&-Y6IL zuqC7g(EYF5YY3JZ*`+QJ=3Dsv1`^@QvujQuz3{2KGU?K`62T-}{7Wt;9z-Jgwhgm2>P zcD}Oey`S6tU*4U6cW3@NO6p%nL{Yt}?J?Z$$nox;Akp*gmiI+ + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Caches a pointer PEI Services Table. + + Caches the pointer to the PEI Services Table specified by PeiServicesTab= lePointer + in a CPU specific manner as specified in the CPU binding section of the = Platform Initialization + Pre-EFI Initialization Core Interface Specification. + + If PeiServicesTablePointer is NULL, then ASSERT(). + + @param PeiServicesTablePointer The address of PeiServices pointer. +**/ +VOID +EFIAPI +SetPeiServicesTablePointer ( + IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatfor= m->firmware_context; + FirmwareContext->PeiServiceTable =3D (VOID *)(UINTN)PeiServicesTablePoin= ter; + + DEBUG ((EFI_D_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Contex= t at 0x%x\n", + PeiServicesTablePointer, + ThisSbiPlatform->firmware_context + )); +} + +/** + Retrieves the cached value of the PEI Services Table pointer. + + Returns the cached value of the PEI Services Table pointer in a CPU spec= ific manner + as specified in the CPU binding section of the Platform Initialization P= re-EFI + Initialization Core Interface Specification. + + If the cached PEI Services Table pointer is NULL, then ASSERT(). + + @return The pointer to PeiServices. + +**/ +CONST EFI_PEI_SERVICES ** +EFIAPI +GetPeiServicesTablePointer ( + VOID + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatfor= m->firmware_context; + return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable; +} + +/** + The constructor function caches the pointer to PEI services. + =20 + The constructor function caches the pointer to PEI services. + It will always return EFI_SUCCESS. + + @param FileHandle The handle of FFS header the loaded driver. + @param PeiServices The pointer to the PEI services. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +PeiServicesTablePointerLibOpenSbiConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + SetPeiServicesTablePointer (PeiServices); + return EFI_SUCCESS; +} + +/** + Perform CPU specific actions required to migrate the PEI Services Table + pointer from temporary RAM to permanent RAM. + + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in + a dedicated CPU register. This means that there is no memory storage + associated with storing the PEI Services Table pointer, so no additional + migration actions are required for Itanium or ARM CPUs. + +**/ +VOID +EFIAPI +MigratePeiServicesTablePointer ( + VOID + ) +{ + // + // PEI Services Table pointer is cached in the global variable. No addi= tional + // migration actions are required. + // + return; +} diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.s b/RiscVPkg/Library/RiscVCpu= Lib/Cpu.s new file mode 100644 index 0000000..ccd7e87 --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.s @@ -0,0 +1,121 @@ +//------------------------------------------------------------------------= ------=20 +// +// RISC-V CPU functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVSetScratch) +.global ASM_PFX(RiscVGetScratch) +.global ASM_PFX(RiscVGetMachineTrapCause) +.global ASM_PFX(RiscVReadMachineIE) +.global ASM_PFX(RiscVReadMachineIP) +.global ASM_PFX(RiscVReadMachineStatus) +.global ASM_PFX(RiscVWriteMachineStatus) +.global ASM_PFX(RiscVReadMachineTvec) +.global ASM_PFX(RiscVReadMisa) +.global ASM_PFX(RiscVReadMVendorId) +.global ASM_PFX(RiscVReadMArchId) +.global ASM_PFX(RiscVReadMImplId) +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVSetScratch): + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVGetScratch): + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_PFX (RiscVGetMachineTrapCause): + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_PFX (RiscVReadMachineIE): + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_PFX (RiscVReadMachineIP): + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_PFX(RiscVReadMachineStatus): + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_PFX(RiscVWriteMachineStatus): + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_PFX(RiscVReadMachineTvec): + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_PFX(RiscVReadMisa): + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_PFX(RiscVReadMVendorId): + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_PFX(RiscVReadMArchId): + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_PFX(RiscVReadMImplId): + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Librar= y/RiscVCpuLib/RiscVCpuLib.inf new file mode 100644 index 0000000..2d8a32d --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -0,0 +1,46 @@ +## @file +# Memory Status Code Library for UEFI drivers +# +# Lib to provide memory journal status code reporting Routines +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVCpuLib + FILE_GUID =3D 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVCpuLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + Cpu.s + +[Sources.RISCV64] + Cpu.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c= b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c new file mode 100644 index 0000000..309cb19 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c @@ -0,0 +1,47 @@ +/** @file + RISC-V platform level DXE core hand off library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + =20 + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack=20 + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + + // + // Transfer the control to the entry point of DxeCore. + // + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint, + HobList.Raw, + NULL, + TopOfStack + ); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.i= nf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf new file mode 100644 index 0000000..62599ac --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVPlatformDxeIplLib + FILE_GUID =3D 2A77EE71-9F55-43F9-8773-7854A5B56086 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVDxeIplHandoffLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + +[Pcd] diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHando= ffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplH= andoffOpenSbiLib.c new file mode 100644 index 0000000..37b4d32 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS= biLib.c @@ -0,0 +1,108 @@ +/** @file + RISC-V DXE IPL to DXE core handoff platform library using OpenSBI + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/** + RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.=20 + This function is executed in RISC-V Supervisor mode. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + =20 + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack=20 + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVDxeIplHandoffOpenSbiHandler ( + IN UINTN HardId, + IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext + ) +{ + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff hand= ler entry\n")); + + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint, + ThisSwitchContext->HobList.Raw, + NULL, + ThisSwitchContext->TopOfStack + ); + + // + // Shold never came back. + // + __builtin_unreachable(); +} + + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + =20 + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack=20 + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + struct sbi_scratch *ThisScratch; + OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext; + + DEBUG ((EFI_D_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n")); + // + // Setup next address in OpenSBI scratch + // + OpenSbiSwitchModeContext.BaseOfStack =3D BaseOfStack; + OpenSbiSwitchModeContext.TopOfStack =3D TopOfStack; + OpenSbiSwitchModeContext.HobList =3D HobList; + OpenSbiSwitchModeContext.DxeCoreEntryPoint =3D DxeCoreEntryPoint; + ThisScratch =3D sbi_scratch_thishart_ptr (); + ThisScratch->next_arg1 =3D (unsigned long)(UINTN)&OpenSbiSwitchModeConte= xt; + ThisScratch->next_addr =3D (unsigned long)(UINTN)RiscVDxeIplHandoffOpenS= biHandler; + ThisScratch->next_mode =3D PRV_S; + + DEBUG ((EFI_D_INFO, " Base address of satck: 0x%x\n", BaseOfSta= ck)); + DEBUG ((EFI_D_INFO, " Top address of satck: 0x%x\n", TopOfStack= )); + DEBUG ((EFI_D_INFO, " HOB list address: 0x%x\n", &HobList)); + DEBUG ((EFI_D_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreE= ntryPoint)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN= )&OpenSbiSwitchModeContext)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode handler address: 0x%x= \n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode to privilege 0x%x\n",= PRV_S)); + sbi_init (ThisScratch); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHando= ffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIp= lHandoffOpenSbiLib.inf new file mode 100644 index 0000000..3ddfe41 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenS= biLib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library using O= penSBI +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVPlatformDxeIplLib + FILE_GUID =3D 906A4BB9-8DE2-4CE0-A609-23818A8FF514=20 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVDxeIplHandoffOpenSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + +[Pcd] diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s b/Ris= cVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s new file mode 100644 index 0000000..a987c9b --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s @@ -0,0 +1,94 @@ +/** @file + RISC-V Processor supervisor mode trap handler + =20 + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 + + This program and the accompanying materials are licensed and made availa= ble under=20 + the terms and conditions of the BSD License that accompanies this distri= bution. =20 + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. = =20 + =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + +**/ + +#include +#include +#include +#include +#include +#include +#include + + .align 3 + .section .entry, "ax", %progbits + .globl _strap_handler +_strap_handler: + addi sp, sp, -34*8 + /* Save all general regisers except SP and T0 */ + sd ra, 1*8(sp) + sd gp, 2*8(sp) + sd tp, 3*8(sp) + sd t1, 4*8(sp) + sd t2, 5*8(sp) + sd s0, 6*8(sp) + sd s1, 7*8(sp) + sd a0, 8*8(sp) + sd a1, 9*8(sp) + sd a2, 10*8(sp) + sd a3, 11*8(sp) + sd a4, 12*8(sp) + sd a5, 13*8(sp) + sd a6, 14*8(sp) + sd a7, 15*8(sp) + sd s2, 16*8(sp) + sd s3, 17*8(sp) + sd s4, 18*8(sp) + sd s5, 19*8(sp) + sd s6, 20*8(sp) + sd s7, 21*8(sp) + sd s8, 22*8(sp) + sd s9, 23*8(sp) + sd s10, 24*8(sp) + sd s11, 25*8(sp) + sd t3, 26*8(sp) + sd t4, 27*8(sp) + sd t5, 28*8(sp) + sd t6, 29*8(sp) + + /* Call C routine */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP and T0 */ + ld ra, 1*8(sp) + ld gp, 2*8(sp) + ld tp, 3*8(sp) + ld t1, 4*8(sp) + ld t2, 5*8(sp) + ld s0, 6*8(sp) + ld s1, 7*8(sp) + ld a0, 8*8(sp) + ld a1, 9*8(sp) + ld a2, 10*8(sp) + ld a3, 11*8(sp) + ld a4, 12*8(sp) + ld a5, 13*8(sp) + ld a6, 14*8(sp) + ld a7, 15*8(sp) + ld s2, 16*8(sp) + ld s3, 17*8(sp) + ld s4, 18*8(sp) + ld s5, 19*8(sp) + ld s6, 20*8(sp) + ld s7, 21*8(sp) + ld s8, 22*8(sp) + ld s9, 23*8(sp) + ld s10, 24*8(sp) + ld s11, 25*8(sp) + ld t3, 26*8(sp) + ld t4, 27*8(sp) + ld t5, 28*8(sp) + ld t6, 29*8(sp) + addi sp, sp, 34*8 + sret \ No newline at end of file diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.i= nf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf new file mode 100644 index 0000000..04bdd6a --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf @@ -0,0 +1,47 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CpuExceptionHandlerLib + MODULE_UNI_FILE =3D CpuExceptionHandlerLib.uni + FILE_GUID =3D 16309FCF-E900-459C-B071-052118394D11 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuExceptionHandlerLib + CONSTRUCTOR =3D CpuExceptionHandlerLibConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources.RISCV64] + CpuExceptionHandler.s + +[Sources.common] + CpuExceptionHandlerLib.c + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + DebugLib + RiscVCpuLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/= RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c new file mode 100644 index 0000000..7be18af --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c @@ -0,0 +1,187 @@ +/** @file + RISC-V Exception Handler library implementition. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include +#include +#include +#include +#include +#include +#include + + +extern void _strap_handler(void); +EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2]; +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Initializes all CPU interrupt/exceptions entries and provides the defaul= t interrupt/exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS All CPU interrupt/exception entries have b= een successfully initialized + with default interrupt/exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuInterruptHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + + DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n"= , InterruptType, InterruptHandler)); + gInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} +/** + Machine mode trap handler. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + VOID + ) +{ + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + // + // Check scasue register. + // + if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] !=3D NULL) { + gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CO= NST EFI_SYSTEM_CONTEXT)RiscVSystemContext); + } +} + +/** + Initializes all CPU exceptions entries with optional extra initializatio= ns. + + By default, this method should include all functionalities implemented by + InitializeCpuExceptionHandlers(), plus extra initialization works, if an= y. + This could be done by calling InitializeCpuExceptionHandlers() directly + in this method besides the extra works. + + InitData is optional and its use and content are processor arch dependen= t. + The typical usage of it is to convey resources which have to be reserved + elsewhere and are necessary for the extra initializations of exception. + + @param[in] VectorInfo Pointer to reserved vector list. + @param[in] InitData Pointer to data optional for extra initializat= ions + of exception. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid + content. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlersEx ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + ) +{ + return InitializeCpuExceptionHandlers (VectorInfo); +} + +/** + The constructor function to initial interrupt handlers in + RISCV_MACHINE_MODE_CONTEXT. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The destructor completed successfully. + @retval Other value The destructor did not complete successfully. + +**/ +EFI_STATUS +EFIAPI +CpuExceptionHandlerLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Set Superviosr mode trap handler. + // + csr_write(CSR_STVEC, _strap_handler); + + return EFI_SUCCESS; +} diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni = b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..ef38a57603a7a20e05391e4b47c= bd0e3764107a9 GIT binary patch literal 1516 zcmc(fUvCmY6vfZ8iQi#EU(~dqKKNja5$LMK+9edMJ~jMnyAcWj+RB$#e`khe5%s|* zLw4@Wojd2Ad*%*5zSmS!!uNzJ#;qaiJ0Wsc!I(SW;7orJtIYFNN&%DPW3Gg}d1F6KLg$COC# ztvPo?e1fOH;hr;_fL7wWKA)ZtJq-NK%(w-Ht~}S!8H!rHT`ncp`=3DG^;@%L(T*cj1jM7^AA$=3Dccv;92DLy;xPV zzr-JJ$eh0sv(M>QU80t2q6VAuvyB2~wA#_townj8UWR^j54ty&RD25~D_v#2;C^a* z+Ar}8h#cu?Z>I{%HD9Snm%dG5)24eey<@EFBkLAQx;t&Vcw6*Wk69Y@?dcSo;jlW)!`1ObM}pzg^Y>LiRuJqr}$f-8Y2tYJFLvz zKIiNb>lkN^QE!QL_Al5E?3lUVYr4r2t4Q^Ei&LVv(4tK@Ip;BY7rGTT3I8AQ-@-nB z2iu;BZzt+^0a6A=3D542PlFtT1&wvJj|`26j6z#aMxTygJxMt7Y%;Rq}$w71Itsh0m$$4~Ue B=3Ds5rY literal 0 HcmV?d00001 diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPk= g/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000..05180da --- /dev/null +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,65 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials are licensed and made +# available under the terms and conditions of the BSD License which +# accompanies this distribution. The full text of the license may +# be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVOpensbiLib + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVOpensbiLib + +[Sources] + ../../opensbi/lib/sbi/riscv_asm.c + ../../opensbi/lib/sbi/riscv_atomic.c + ../../opensbi/lib/sbi/riscv_hardfp.S + ../../opensbi/lib/sbi/riscv_locks.c + ../../opensbi/lib/sbi/riscv_unpriv.c + ../../opensbi/lib/sbi/sbi_console.c + ../../opensbi/lib/sbi/sbi_ecall.c + ../../opensbi/lib/sbi/sbi_emulate_csr.c + ../../opensbi/lib/sbi/sbi_fifo.c + ../../opensbi/lib/sbi/sbi_hart.c + ../../opensbi/lib/sbi/sbi_illegal_insn.c + ../../opensbi/lib/sbi/sbi_init.c + ../../opensbi/lib/sbi/sbi_ipi.c + ../../opensbi/lib/sbi/sbi_misaligned_ldst.c + ../../opensbi/lib/sbi/sbi_scratch.c + ../../opensbi/lib/sbi/sbi_string.c + ../../opensbi/lib/sbi/sbi_system.c + ../../opensbi/lib/sbi/sbi_timer.c + ../../opensbi/lib/sbi/sbi_tlb.c + ../../opensbi/lib/sbi/sbi_trap.c + ../../opensbi/lib/utils/sys/clint.c + ../../opensbi/lib/utils/irqchip/plic.c + ../../opensbi/lib/utils/serial/sifive-uart.c + ../../opensbi/lib/utils/serial/uart8250.c + ../../opensbi/lib/utils/libfdt/fdt.c + ../../opensbi/lib/utils/libfdt/fdt_ro.c + ../../opensbi/lib/utils/libfdt/fdt_wip.c + ../../opensbi/lib/utils/libfdt/fdt_rw.c + ../../opensbi/lib/utils/libfdt/fdt_sw.c + ../../opensbi/lib/utils/libfdt/fdt_strerror.c + ../../opensbi/lib/utils/libfdt/fdt_empty_tree.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatf= ormTempMemoryInitLibNull.inf b/RiscVPkg/Library/RiscVPlatformTempMemoryInit= LibNull/RiscVPlatformTempMemoryInitLibNull.inf new file mode 100644 index 0000000..193452f --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTemp= MemoryInitLibNull.inf @@ -0,0 +1,42 @@ +## @file +# RISC-V platform temporary memory library. +# +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVPlatformTempMemoryInitLibNull + FILE_GUID =3D 67294857-C0F8-4ACB-8237-D91FE506B710 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformTempMemoryInitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + +[Sources.RISCV64] + Riscv64/TempMemInit.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/Te= mpMemInit.s b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/T= empMemInit.s new file mode 100644 index 0000000..22ff329 --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemIn= it.s @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V RiscVPlatformTemporaryMemInit. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVPlatformTemporaryMemInit) + +// +// @retval a0 Temporary memory base. +// a1 Temporary memory size. +// +ASM_PFX(RiscVPlatformTemporaryMemInit): + li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase) + li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize) + ret diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPk= g/Library/RiscVTimerLib/BaseRiscVTimerLib.inf new file mode 100644 index 0000000..66e821b --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf @@ -0,0 +1,40 @@ +## @file +# RISC-V Timer Library Instance. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# +# This program and the accompanying materials are licensed and made +# available under the terms and conditions of the BSD License which +# accompanies this distribution. The full text of the license may +# be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseRiscVTimerLib + FILE_GUID =3D FB648CF5-91BE-4737-9023-FD807AC6D96D + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + +[Sources] + RiscVTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + RiscVPlatformTimerLib + diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Libr= ary/RiscVTimerLib/RiscVTimerLib.c new file mode 100644 index 0000000..5dd4a4e --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -0,0 +1,201 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD Li= cense + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D RiscVReadMachineTimer () + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPA= RE_BITS - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadMachineTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRisc= VMachineTimerFrequencyInHerz), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u)= , PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)); + + return NanoSeconds; +} diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Libr= ary/RiscVTimerLib/RiscVTimerLib.h new file mode 100644 index 0000000..1704bbb --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h @@ -0,0 +1,26 @@ +/** @file + RISC-V timer library definitions. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + + +#ifndef _RISCV_TIMER_LIB_INTERNAL_H_ +#define _RISCV_TIMER_LIB_INTERNAL_H_ + +#include +#include +#include +#include + +#include + +#endif // _RISCV_TIMER_LIB_INTERNAL_H_ --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46795): https://edk2.groups.io/g/devel/message/46795 Mute This Topic: https://groups.io/mt/33137145/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46796+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46796+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595631; cv=none; d=zoho.com; s=zohoarc; b=feZus904aL0cx+nCqEEPn8WdE7LR1MVtXpDwTIQaOf5+l36EdN8gSPgC2/nfZeF83cpidedJiiV/0kdSPYvUYrlGXMFTZb7tlPJPQukJZ0DLmAUwL2vqdvJSccHejl2M5goI9BgWybmBCBX/H5cwX49hyZDKk+Y7K/0CZZ7H7SY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595631; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=whwIBg3U+us06yyYV/UU7AVmRHh8oJAZo021Wkr1J9M=; b=T72NrCmG544RWEBBKTbYV8jBE7wSkmJBhUAiyIvZkmaE+sebfyZfK6trScbfiOy0XAJ9QTuW816M0vvjoV0d15VVgvHMoGETmYEgyLWzsT5JeY8j0Cq+SKs9sNPWhqgS5z3QUDmqE0FufURH+mf5PRJZjOaIZFTLbMMu4AsVbsU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46796+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595631390905.8842171750161; Wed, 4 Sep 2019 04:13:51 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:50 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBh3e002226 for ; Wed, 4 Sep 2019 11:13:49 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut7enj5df-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:49 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 19D18A8 for ; Wed, 4 Sep 2019 11:13:49 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 309BD39; Wed, 4 Sep 2019 11:13:47 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 19/22]: MdeModulePkg/DxeIplPeim:RISC-V platform DXEIPL. Date: Wed, 4 Sep 2019 18:43:14 +0800 Message-Id: <1567593797-26216-20-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595631; bh=dvXtyqG9Imvbf5R1fkv3CufOGqP8TjUw9goYj8I6uxI=; h=Cc:Date:From:Reply-To:Subject:To; b=szpzp2H+gCGuz7LeUkznFbf++i3fy8A/+TltUC6PAUm3u1KTEwLKqknnYkg2athAJTp oS3innHzCjbq7SYPnwWrsdtvkBwXnQxBdkxX4Hdz22tJnY+4JkrImFi2KY7VtLxYA6nwK zFf/GjqlJyfdOJiXe9nAkPxmvRN9rsdWBws= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Implement RISC-V DxeIpl. - Provide DxeIpl platform implementation-specifc library for RISC-V platfor= m. Two libraries are provided in this commit, * Defualt library which simply switch stack and transfer control to DXE core. * Switch stack, privilege mode and then transfer control to DXE core through RISC-V opensbi. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++- MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 76 ++++++++++++++++++= ++++ 2 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 98bc17f..5532323 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -7,6 +7,7 @@ # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 RISCV64 # =20 [Sources] @@ -49,6 +50,9 @@ [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c =20 +[Sources.RISCV64] + RiscV64/DxeLoadFunc.c + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -56,6 +60,9 @@ [Packages.ARM, Packages.AARCH64] ArmPkg/ArmPkg.dec =20 +[Packages.RISCV64] + RiscVPkg/RiscVPkg.dec + [LibraryClasses] PcdLib MemoryAllocationLib @@ -75,6 +82,10 @@ [LibraryClasses.ARM, LibraryClasses.AARCH64] ArmMmuLib =20 +[LibraryClasses.RISCV64] + RiscVPlatformDxeIplLib + RiscVOpensbiLib + [Ppis] gEfiDxeIplPpiGuid ## PRODUCES gEfiPeiDecompressPpiGuid ## PRODUCES diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModule= Pkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c new file mode 100644 index 0000000..934dfa5 --- /dev/null +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c @@ -0,0 +1,76 @@ +/** @file + RISC-V specific functionality for DxeLoad. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "DxeIpl.h" +#include "Library/RiscVPlatformDxeIpl.h" + +typedef +VOID* +(EFIAPI *DXEENTRYPOINT) ( + IN VOID *HobStart + ); + +/** + Transfers control to DxeCore. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +HandOffToDxeCore ( + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + VOID *BaseOfStack; + VOID *TopOfStack; + EFI_STATUS Status; + // + // + // Allocate 128KB for the Stack + // + BaseOfStack =3D AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE)); + ASSERT (BaseOfStack !=3D NULL); + + // + // Compute the top of the stack we were allocated. Pre-allocate a UINTN + // for safety. + // + TopOfStack =3D (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_= SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); + TopOfStack =3D ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); + + // + // End of PEI phase signal + // + Status =3D PeiServicesInstallPpi (&gEndOfPeiSignalPpi); + ASSERT_EFI_ERROR (Status); + + // + // Update the contents of BSP stack HOB to reflect the real stack info p= assed to DxeCore. + // + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE); + + DEBUG ((EFI_D_INFO, "DXE Core new stack at %x, stack pointer at %x\n", B= aseOfStack, TopOfStack)); + + // + // Transfer the control to the entry point of DxeCore. + // + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoin= t, HobList); +} + --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46796): https://edk2.groups.io/g/devel/message/46796 Mute This Topic: https://groups.io/mt/33137146/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46797+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46797+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595632; cv=none; d=zoho.com; s=zohoarc; b=IeQ4r9z91HF5/r2fOJdj0XCzn7k6+ivnVVZeT4YwaeYseGSRLLc1meIytHq1kbHXaDgZeiAriIsL97/OZyHg9ZB0y8fF8lRax7vUT/vLwt+TBIyialM9m1JZ25r/+fxMSuShThVKv4iz0tnIgXus6gCfnjC3EVeFXQj6zPCbH7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595632; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=9/VPrabaTTe855p/+PjW0I+FHKxGKjutyjsDnty4fLY=; b=DK2lRodfOkfvLZG6lF/VPkAAuBdvyl0ueiHhCJ+pl99flSOxv/w2M2QNJsnsETWdVlJA9SHVW4L0wsKzwPfw7N7N2XFnlORiNa0rRulJWZxhBRby+NdcbccJ7p/yAha5d9Fb/Yzy629/k8ceNymOFo6uOZ3qdeuXXt9xwFNNvwU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46797+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595632511460.94716560909603; Wed, 4 Sep 2019 04:13:52 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:51 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBgru017977 for ; Wed, 4 Sep 2019 11:13:51 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 2usyw7vrhu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:50 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 766E077 for ; Wed, 4 Sep 2019 11:13:50 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 841DE39; Wed, 4 Sep 2019 11:13:49 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 20/22]: MdeModulePkg/Logo Date: Wed, 4 Sep 2019 18:43:15 +0800 Message-Id: <1567593797-26216-21-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595632; bh=JkLujUXWE8FiCV2Zc/HTGOQ0a26fY35dcMhtXtcGo98=; h=Cc:Date:From:Reply-To:Subject:To; b=QNqXonMR6Al0kvT5H+X5rN1HZymSAV3a0XHmstKkFHPsWTd+7Av6QAwNVWbXlZILCgY crErT6moOLPqUeBP+b06SZFSjcVYRB0rYCyJRFVVThMB7ixKH1l05PBqnvJm/AWdfsFVW vUFfoYoe73K8QjpgSZ2dPYKSLIUjNeUFR6c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISCV64 Arch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- MdeModulePkg/Logo/Logo.inf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf index 0182025..243748c 100644 --- a/MdeModulePkg/Logo/Logo.inf +++ b/MdeModulePkg/Logo/Logo.inf @@ -19,7 +19,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Binaries] --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46797): https://edk2.groups.io/g/devel/message/46797 Mute This Topic: https://groups.io/mt/33137147/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46798+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46798+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595634; cv=none; d=zoho.com; s=zohoarc; b=hPuVJy7EnTzgOqjGJaUNHuxmfxak7fpBomHh3Zp+zI2UMI+OFpjqYC+Zr5kFfgyN2p1WWJMu6C/7uMdCbtrW9vMRLEucBY149wl+EeBoJgqedviSXCkKCbarVeqzvmeBfqy/pGeFk2soM169ZmoPrJsKlr+Gbz1oX5j+He07hwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595634; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Ply1+fwfX83m4+wG/e2tzTlsCFO550GC16zJRehiq18=; b=aikOJVexePhNPa+3anPNfWEpuARRYWb7uWfA3LyuqmpGhxiHX4jrpNr/1zTbq1RxC/qEGDJGWBNjT7cA9KHdPDcyW4C3fBpdJf5hxt8N0cNf4IgahD5uezmjBlssEb+1ARV0UIA0nFbQI4zG7zxVOLLTwbHhqzfFauG2E0CQNIA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46798+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156759563408882.56924588154664; Wed, 4 Sep 2019 04:13:54 -0700 (PDT) Return-Path: X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:53 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBgtN020137 for ; Wed, 4 Sep 2019 11:13:52 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7yg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:52 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id D441A77 for ; Wed, 4 Sep 2019 11:13:51 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id E0E2C42; Wed, 4 Sep 2019 11:13:50 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 21/22]: NetworkPkg Date: Wed, 4 Sep 2019 18:43:16 +0800 Message-Id: <1567593797-26216-22-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595633; bh=YXG4MU42IHceH8tN7FQTQ+UNjOfWiAyJKuxmhm7XWvg=; h=Cc:Date:From:Reply-To:Subject:To; b=douZw/4f/Qhy8gZNseuG9pIqPXvmUAABNfKDW3n4TCk9/2/QaG+1GoFHgdeIOofHjUW neX0QTP7UdN+9IaXI3vPX1CAWIucb/r/4wEQbDsBSq/SQMXNnTNlhHgM59MVLz72NCzHB oVUQo+leYfQ1mqBprQxYU10ri9YWAzo5nvQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add RISCV64 Arch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- NetworkPkg/Network.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc index c7f4328..b484f9b 100644 --- a/NetworkPkg/Network.dsc.inc +++ b/NetworkPkg/Network.dsc.inc @@ -34,7 +34,7 @@ !include NetworkPkg/NetworkComponents.dsc.inc =20 !else -[Components.IA32, Components.X64, Components.ARM, Components.AARCH64] +[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Comp= onents.RISCV64] !include NetworkPkg/NetworkComponents.dsc.inc =20 !endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46798): https://edk2.groups.io/g/devel/message/46798 Mute This Topic: https://groups.io/mt/33137148/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 00:44:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46799+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46799+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1567595635; cv=none; d=zoho.com; s=zohoarc; b=PBZIeGcUj8G7rSkuvOqjz8zxhhrEylRIAw6RSsfIxYUcSCOwV60qLPIYSFYCmnFXnN1M48Uhx8s5ekCc8iqKYSEZVe0sgFkfRG3QLNsytf5Tlof9ScUuWDmycoh8RGyysoDWVUqOo8ojeS4T7M4JUQMI7hBKHvidHKrn6/DAJNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567595635; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=JANIHEB8qm4BJ9TEhoorp7rkVXI1ktL4AK+SsUayXWs=; b=Xx+PIYEkmaqf56krFMTfic84GW8Rm2VRgiYliEha+T6vNj7j46kpmEYYH5dHoSJA/ja/RDGku3EbyEc5Tz+99aI7eVWiwlo26Oz66kPSw4IYkVSZ+imxKKfguXoQRZ3Gy7jEcC48xstDj9D4/BEVsGYGCcgUdesmh9CwGEtU3ak= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46799+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567595635434138.57469805732342; Wed, 4 Sep 2019 04:13:55 -0700 (PDT) Return-Path: X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:54 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBhJD022273 for ; Wed, 4 Sep 2019 11:13:53 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 2uswj5wrak-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:53 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 3623777 for ; Wed, 4 Sep 2019 11:13:53 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 4B2D839; Wed, 4 Sep 2019 11:13:52 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v1 22/22]: BaseTools/Scripts Date: Wed, 4 Sep 2019 18:43:17 +0800 Message-Id: <1567593797-26216-23-git-send-email-abner.chang@hpe.com> In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567595635; bh=hBpSb87f4FYdmKj99aZZHQtH/7s/fQJUzAM/p/gceBk=; h=Cc:Date:From:Reply-To:Subject:To; b=OfiK9B3xk1BJbYJ2oAsUh0UHJsb1k+i5xc4j29gCoSAwi5/ps4oJCNzBv4bMfwt0Prd l9lFxAzJQmJsK8lQF3r0dQXUXMULzip1D3Dq/Qa7YPcffcgWkh3o0uRsVcNDspMAAktYp ZpgT9Z0iUAL8nmrDr7SXso06BWvo+4sTPDU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds cau= ses PE32 relocation error. This is the temporaty solution untill we find th= e root casue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- BaseTools/Scripts/GccBaseRiscV.lds | 71 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBase= RiscV.lds new file mode 100644 index 0000000..b24086d --- /dev/null +++ b/BaseTools/Scripts/GccBaseRiscV.lds @@ -0,0 +1,71 @@ +/** @file + + Unified linker script for GCC based builds + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble under + the terms and conditions of the BSD License that accompanies this distri= bution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +SECTIONS { + + /* + * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequenc= e of + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs + * between 32-bit and 64-bit builds). The actual start of the .text sect= ion + * will be rounded up based on its actual alignment. + */ + . =3D PECOFF_HEADER_SIZE; + + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) { + *(.text .text.* .stub .gnu.linkonce.t.*) + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.got .got.*) + + /* + * The contents of AutoGen.c files are constant from the POV of the pr= ogram, + * but most of its contents end up in .data or .bss by default since f= ew of + * the variable definitions that get emitted are declared as CONST. + */ + *:AutoGen.obj(.data.g*Guid) =20 + } + + /* + * The alignment of the .data section should be less than or equal to the + * alignment of the .text section. This ensures that the relative offset + * between these sections is the same in the ELF and the PE/COFF version= s of + * this binary. + */ + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) { + *(.data .data.* .gnu.linkonce.d.*) + *(.bss .bss.*) + } + + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : { + KEEP (*(.eh_frame)) + } + + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : { + *(.rela .rela.*) + } + + /DISCARD/ : { + *(.note.GNU-stack) + *(.gnu_debuglink) + *(.interp) + *(.dynsym) + *(.dynstr) + *(.dynamic) + *(.hash) + *(.comment) + *(COMMON) + } +} --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46799): https://edk2.groups.io/g/devel/message/46799 Mute This Topic: https://groups.io/mt/33137150/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-