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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:31 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 02/10] Marvell/Cn9130Db: Add ACPI tables Date: Thu, 15 Aug 2019 04:54:06 +0200 Message-Id: <1565837654-13258-3-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837676; bh=ArJB+jhX8dkAQH1yX53cmnwWajc7mah/XKpZHa4c7LI=; h=Cc:Date:From:Reply-To:Subject:To; b=oywjlqwL+tH7VAAbsYgD33nD4sV4D+Xyk0CuwmXnbtK42KhhyjdeAW/ULh9FCBFJEI8 38GxtFLsCiY7lViYmSTId7QNkseSzoipMtmIOk7JcIqxMeTJNMNwCbKke185e3cLp2xFa qD7+ibjjksVU2bePlIaILQRvAoK3g/zkCJA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds ACPI tables and necessary headers, which are common for Cn913x SoCs and the CN9130 development board (variant A). Wiring up of support will be done in the follow-up commits. Signed-off-by: Marcin Wojtas Acked-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 37 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++= ++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 ++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 ++++++++= +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 +++ 11 files changed, 1046 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.= asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.= aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf new file mode 100644 index 0000000..191a747 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -0,0 +1,56 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9130 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h new file mode 100644 index 0000000..b5fd397 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -0,0 +1,37 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} +#define ACPI_OEM_REVISION 0 +#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define ACPI_CREATOR_REVISION 0 + +#if defined(CN9130) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#endif + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define __ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h b/Sil= icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h new file mode 100644 index 0000000..634bd8d --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h @@ -0,0 +1,20 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x10000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xDFF00000 +#define PCI_ECAM_BASE 0xD0008000 +#define PCI_ECAM_SIZE 0x10000000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h new file mode 100644 index 0000000..6befe2a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -0,0 +1,36 @@ +/** + + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Glossary - abbreviations used in Marvell SampleAtReset library implement= ation: + ICU - Interrupt Consolidation Unit + AP - Application Processor hardware block (CN913x incorporates AP807) + CP - South Bridge hardware blocks (CN913x incorporates CP115) + +**/ + +#define CP_GIC_SPI_CP0_PCI0 64 +#define CP_GIC_SPI_CP0_PCI1 65 +#define CP_GIC_SPI_CP0_PCI2 66 +#define CP_GIC_SPI_CP0_SDMMC 67 +#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 +#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 +#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 +#define CP_GIC_SPI_CP0_EIP_RNG0 105 +#define CP_GIC_SPI_CP0_USB_H1 112 +#define CP_GIC_SPI_CP0_USB_H0 113 +#define CP_GIC_SPI_CP0_SATA_H0 114 + +#define CP_GIC_SPI_CP1_PCI0 288 +#define CP_GIC_SPI_CP1_PCI1 289 +#define CP_GIC_SPI_CP1_PCI2 290 +#define CP_GIC_SPI_CP1_SDMMC 291 +#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 +#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 +#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 +#define CP_GIC_SPI_CP1_EIP_RNG0 329 +#define CP_GIC_SPI_CP1_USB_H1 336 +#define CP_GIC_SPI_CP1_USB_H0 337 +#define CP_GIC_SPI_CP1_SATA_H0 338 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl new file mode 100644 index 0000000..3dcf78a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -0,0 +1,324 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xDbA/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (COM1) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xCFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + PCI_ECAM_SIZE + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc b/= Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc new file mode 100644 index 0000000..88f59ab --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc @@ -0,0 +1,41 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" +#include "Cn913xDbA/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Fadt.aslc new file mode 100644 index 0000000..ea396bd --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc @@ -0,0 +1,80 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \ + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_6_0_HEADLESS + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepStatusReg +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Gtdt.aslc new file mode 100644 index 0000000..46bfe37 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc @@ -0,0 +1,58 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +// active low, level triggered +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILI= TY + +// active high, level triggered +#define GTDT_WDG_FLAGS 0x0 + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog; +} ACPI_6_0_GTDT_STRUCTURE; +#pragma pack() + +ACPI_6_0_GTDT_STRUCTURE Gtdt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_GTDT_STRUCTURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= Address + 0x1, // UINT32 PlatformTim= erCount + sizeof (Gtdt.Header) // UINT32 PlatformTim= erOffset + }, { + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof (Gtdt.SbsaWatchdog), // UINT16 Length + 0x0, // UINT8 Reserved + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFram= ePhysicalAddress + FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogCon= trolFramePhysicalAddress + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTim= erGSIV + GTDT_WDG_FLAGS // UINT32 WatchdogTim= erFlags + }, +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Madt.aslc new file mode 100644 index 0000000..abd3cfc --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc @@ -0,0 +1,135 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceB= ase) +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define GICH_BASE 0xF0240000 +#define GICV_BASE 0xF0260000 +#define VGIC_MAINT_INT 25 + +#define GIC_MSI_FRAME0 0xF0280000 +#define GIC_MSI_FRAME1 0xF0290000 +#define GIC_MSI_FRAME2 0xF02A0000 +#define GIC_MSI_FRAME3 0xF02B0000 + +#define PMU_INTERRUPT_CPU0 130 +#define PMU_INTERRUPT_CPU1 131 +#define PMU_INTERRUPT_CPU2 132 +#define PMU_INTERRUPT_CPU3 133 + +#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_= PERFORMANCE_INTERRUPT_MODEL + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicC[4]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4]; +} ACPI_6_0_MADT_STRUCTURE; +#pragma pack(pop) + + +ACPI_6_0_MADT_STRUCTURE Madt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MADT_STRUCTURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId + 0x000, // AcpiCpu= Uid + 0x000, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU0, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId + 0x001, // AcpiCpu= Uid + 0x001, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU1, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId + 0x100, // AcpiCpu= Uid + 0x100, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU2, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId + 0x101, // AcpiCpu= Uid + 0x101, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU3, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDist= HwId + GICD_BASE, // GicDist= Base + 0x0, // GicDist= Vector + EFI_ACPI_6_0_GIC_V2 // GicVers= ion + ), + { + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiF= rameId + GIC_MSI_FRAME0, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiF= rameId + GIC_MSI_FRAME1, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiF= rameId + GIC_MSI_FRAME2, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiF= rameId + GIC_MSI_FRAME3, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Pptt.aslc new file mode 100644 index 0000000..f37c751 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc @@ -0,0 +1,210 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define NUM_CORES FixedPcdGet64 (PcdCoreCount) + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_2_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_2_PPTT_CORE Cores[2]; +} ACPI_6_2_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + ACPI_6_2_PPTT_CLUSTER Clusters[NUM_C= ORES / 2]; +} ACPI_6_2_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_2_PPTT_PACKAGE Packages[1]; +} ACPI_6_2_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 256 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + 3 * SIZE_16KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 3, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2C= ache), \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_512KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE(pid, cid, 0), = \ + PPTT_CORE(pid, cid, 1), = \ + } = \ +} + +ACPI_6_2_PPTT_STRUCTURE Pptt =3D { + { + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTU= RE_SIGNATURE, + ACPI_6_2_PPTT_STRUCTURE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVIS= ION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResour= ces */ + }, { + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 1, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_1MB, /* Size */ + 2048, /* NumberOfSets */ + 8, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#endif + } + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc new file mode 100644 index 0000000..f663d8a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -0,0 +1,49 @@ +/** @file + Serial Port Console Redirection Table (SPCR) + + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include +#include + +#include "AcpiHeader.h" + +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + { EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] + MV_UART_AS32 (FixedPcdGet64(PcdSerialRegisterBase)), //= BaseAddress + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //= InterruptType + 0, //= Irq + 51, //= GlobalSystemInterrupt + 0, //= BaudRate + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //= Parity + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //= StopBits + 0, //= FlowControl + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //= TerminalType + EFI_ACPI_RESERVED_BYTE, //= Language + 0xFFFF, //= PciDeviceId + 0xFFFF, //= PciVendorId + 0, //= PciBusNumber + 0, //= PciDeviceNumber + 0, //= PciFunctionNumber + 0, //= PciFlags + 0, //= PciSegment + EFI_ACPI_RESERVED_DWORD //= Reserved2 +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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