From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45664+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45664+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837675; cv=none; d=zoho.com; s=zohoarc; b=Zq6yJO3TzaTI1aTjd5Bt3KyF1nxIX+fwOwUOaff4opUEsB6TceOqq/0v+RicHeASVJBWsO652sd2yXU1Lx3NZNXqFSF+XeSk7f8LuBjhgieGQYcb6jgAs+EuEzGFHwOT4B8yIPVM3cmxQR4CDvoOMOX/BdxwIY9IPH5gRJ1iQgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837675; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=3vVLBJLaweLEqi0+nN5yW/FekouyziITnmeneqK1Da0=; b=TU32qx/W7d+00ejRE9ZWUSUAMUnFUM2od94OZn8JIASh3MpLSiu+7MXAifLz1zFQPK2LNoFYeI9VKC7UENfr9zMaHOIV1aTyAeeNDvF7nzkpHUUUpTvR7SQBPaunaui1jwP50qqBG+9oq6BdHlPv7D8CXuBbk3udUz/tprh1h84= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45664+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837675753594.4586930098302; Wed, 14 Aug 2019 19:54:35 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:33 -0700 X-Received: by mail-lf1-f68.google.com with SMTP id s19so702934lfb.9 for ; Wed, 14 Aug 2019 19:54:33 -0700 (PDT) X-Gm-Message-State: APjAAAVitvRHtJe00YssKm+06zckc448Y3Ocw9BQ/3IUZJp0Obt248zP bXxu/6WOn85llPuqLetEdlHqV7b10tBeBg== X-Google-Smtp-Source: APXvYqxDt8437lUe/mPwkrKjqRKbf0ZhTpjiaY0NzWYStAJ9+VxX8+LxvFWpNg8evf9Qb5m0kwdsFg== X-Received: by 2002:ac2:48bc:: with SMTP id u28mr1359987lfg.126.1565837671367; Wed, 14 Aug 2019 19:54:31 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:30 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 01/10] Marvell/Armada7k8k: Fix 32-bit compilation Date: Thu, 15 Aug 2019 04:54:05 +0200 Message-Id: <1565837654-13258-2-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837674; bh=nfY5Yr/l75jw8obD9kirIUpYuobJlinOFjRD2IsA8T4=; h=Cc:Date:From:Reply-To:Subject:To; b=OK8tBAQcVA9gIMzA9fpL0PvmgZaWeOCvQ5dmp0Er1NVz86ddf9zJvjJjT76cJGtUi5Y DdqFQE8oIefM1NcdKtD9dGZn6RftSt4rU3pgrcaqJblVtX/aimn8bOd0IfOoknX/sXdQZ G89wsJhf4/Z3XZ++z6QNGy9EdaT8FXfvDgw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It turned out, that the recently added features broke ARM compilation. Fix all issues: * Use SIGNATURE_32 only * Do not shift address by 32-bit in ICU * Limit memory for ARM build to 1GB and stop using non-existent PCD Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h |= 2 +- Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h |= 2 +- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c |= 4 ++++ Silicon/Marvell/Library/IcuLib/IcuLib.c |= 7 ++++++- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S |= 11 ----------- 5 files changed, 12 insertions(+), 14 deletions(-) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.h index a6f551b..7ecb4e1 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include =20 -#define MV_BOARD_DESC_SIGNATURE SIGNATURE_64 ('M', 'V', 'B', 'R', 'D', 'D'= , 'S', 'C') +#define MV_BOARD_DESC_SIGNATURE SIGNATURE_32 ('B', 'D', 'S', 'C') =20 typedef struct { MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h b/Silicon/M= arvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h index 1cb006a..600d5db 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h @@ -23,7 +23,7 @@ =20 #include =20 -#define MV_GPIO_SIGNATURE SIGNATURE_64 ('M', 'V','_','G', 'P', 'I',= 'O',' ') +#define MV_GPIO_SIGNATURE SIGNATURE_32 ('G', 'P', 'I', 'O') =20 // Marvell MV_GPIO Controller Registers #define MV_GPIO_DATA_OUT_REG (0x0) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index a735fe5..5ff6bb1 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -36,6 +36,7 @@ GetDramSize ( IN OUT UINT64 *MemSize ) { +#if defined(MDE_CPU_AARCH64) ARM_SMC_ARGS SmcRegs =3D {0}; EFI_STATUS Status; =20 @@ -48,6 +49,9 @@ GetDramSize ( ArmCallSmc (&SmcRegs); =20 *MemSize =3D SmcRegs.Arg0; +#else + *MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); +#endif =20 return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c index 343c21b..422388c 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.c +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -185,10 +185,15 @@ IcuConfigure ( for (Index =3D 0; Index < IcuGroupMax; Index++, Msi++) { MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group), Msi->SetSpiAddr & 0xFFFFFFFF); - MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >>= 32); MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group), Msi->ClrSpiAddr & 0xFFFFFFFF); +#if defined(MDE_CPU_AARCH64) + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >>= 32); MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >>= 32); +#else + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), 0); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), 0); +#endif } =20 /* Mask all ICU interrupts */ diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatfo= rmHelper.S b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatfo= rmHelper.S index 4416163..db43b0f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelpe= r.S +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelpe= r.S @@ -28,17 +28,6 @@ ASM_FUNC(ArmPlatformPeiBootAction) .err PcdSystemMemoryBase should be 0x0 on this platform! .endif =20 - .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapT= arget) - // - // Use the low range for UEFI itself. The remaining memory will be map= ped - // and added to the GCD map later. - // - ADRL (r0, mSystemMemoryEnd) - MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) - mov r3, #0 - strd r2, r3, [r0] - .endif - bx lr =20 //UINTN --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45664): https://edk2.groups.io/g/devel/message/45664 Mute This Topic: https://groups.io/mt/32882732/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45665+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45665+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837678; cv=none; d=zoho.com; s=zohoarc; b=Z9IWRgZFMXXHqVvcIE7Csekt+Peg/iUWQEuBsC7dUvXy7RzrgG0qeGiVz4rOjjNXGwNDPjKP5vYG3BdNIgqKNR1jyyFnDs4gajWuA3yJ4l3N30Hq2qttIx+mlfcLN1MFlc/n90dJWltcq4nijOpkVYck7XhTHeH4/ZrtgOHaWDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837678; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=E5skUN9Zb39ED3/J9SZLZ7dGpfojD0gunI5AXMNg61I=; b=SOQCw2J52iCEfdZfzwfTKErwYdY0YvhS/ItXaY5qL2xFeFfozRE7w009iTSSQXLRTp12eilWfEmdOjHR4y+DuEDrUu7Ct5xG+klpoige60d7CLnGra8kbghVYgQyZ3ShLIJRmzyYfys3TLcvkN6OlGT9/T4SqxRWMxF4wf3+cVE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45665+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837677934750.77269948372; Wed, 14 Aug 2019 19:54:37 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:36 -0700 X-Received: by mail-lf1-f65.google.com with SMTP id h28so720767lfj.5 for ; Wed, 14 Aug 2019 19:54:35 -0700 (PDT) X-Gm-Message-State: APjAAAWOI89LD0dq701hay4QZM8x9jpijoX2xjyyAxXem6z1dVn4Bac4 Lbn04ynjxP4CF8wNv9+K/IeFQ2sahT8+MQ== X-Google-Smtp-Source: APXvYqzlfQPvLSm2h75jvBxgLSCkjKmIgme3Rr2udX3S1DKiAGyb7vMaeZzJsZGZG9ORjGLF5kJnGA== X-Received: by 2002:ac2:44ac:: with SMTP id c12mr1256280lfm.33.1565837672625; Wed, 14 Aug 2019 19:54:32 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:31 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 02/10] Marvell/Cn9130Db: Add ACPI tables Date: Thu, 15 Aug 2019 04:54:06 +0200 Message-Id: <1565837654-13258-3-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837676; bh=ArJB+jhX8dkAQH1yX53cmnwWajc7mah/XKpZHa4c7LI=; h=Cc:Date:From:Reply-To:Subject:To; b=oywjlqwL+tH7VAAbsYgD33nD4sV4D+Xyk0CuwmXnbtK42KhhyjdeAW/ULh9FCBFJEI8 38GxtFLsCiY7lViYmSTId7QNkseSzoipMtmIOk7JcIqxMeTJNMNwCbKke185e3cLp2xFa qD7+ibjjksVU2bePlIaILQRvAoK3g/zkCJA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds ACPI tables and necessary headers, which are common for Cn913x SoCs and the CN9130 development board (variant A). Wiring up of support will be done in the follow-up commits. Signed-off-by: Marcin Wojtas Acked-by: Leif Lindholm --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 37 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++= ++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 ++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 ++++++++= +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 +++ 11 files changed, 1046 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.= asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.= aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf new file mode 100644 index 0000000..191a747 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -0,0 +1,56 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9130 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h new file mode 100644 index 0000000..b5fd397 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -0,0 +1,37 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} +#define ACPI_OEM_REVISION 0 +#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define ACPI_CREATOR_REVISION 0 + +#if defined(CN9130) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#endif + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define __ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h b/Sil= icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h new file mode 100644 index 0000000..634bd8d --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h @@ -0,0 +1,20 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x10000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xDFF00000 +#define PCI_ECAM_BASE 0xD0008000 +#define PCI_ECAM_SIZE 0x10000000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h new file mode 100644 index 0000000..6befe2a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -0,0 +1,36 @@ +/** + + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Glossary - abbreviations used in Marvell SampleAtReset library implement= ation: + ICU - Interrupt Consolidation Unit + AP - Application Processor hardware block (CN913x incorporates AP807) + CP - South Bridge hardware blocks (CN913x incorporates CP115) + +**/ + +#define CP_GIC_SPI_CP0_PCI0 64 +#define CP_GIC_SPI_CP0_PCI1 65 +#define CP_GIC_SPI_CP0_PCI2 66 +#define CP_GIC_SPI_CP0_SDMMC 67 +#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 +#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 +#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 +#define CP_GIC_SPI_CP0_EIP_RNG0 105 +#define CP_GIC_SPI_CP0_USB_H1 112 +#define CP_GIC_SPI_CP0_USB_H0 113 +#define CP_GIC_SPI_CP0_SATA_H0 114 + +#define CP_GIC_SPI_CP1_PCI0 288 +#define CP_GIC_SPI_CP1_PCI1 289 +#define CP_GIC_SPI_CP1_PCI2 290 +#define CP_GIC_SPI_CP1_SDMMC 291 +#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 +#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 +#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 +#define CP_GIC_SPI_CP1_EIP_RNG0 329 +#define CP_GIC_SPI_CP1_USB_H1 336 +#define CP_GIC_SPI_CP1_USB_H0 337 +#define CP_GIC_SPI_CP1_SATA_H0 338 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl new file mode 100644 index 0000000..3dcf78a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -0,0 +1,324 @@ +/** @file + + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Cn913xDbA/Pcie.h" +#include "IcuInterrupts.h" + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) +{ + Scope (_SB) + { + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x000) // _UID: Unique ID + } + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x001) // _UID: Unique ID + } + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x100) // _UID: Unique ID + } + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID + Name (_UID, 0x101) // _UID: Unique ID + } + + Device (AHC0) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_SATA_H0 + } + }) + } + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2500000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H0 + } + }) + } + + Device (XHC1) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF2510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_USB_H1 + } + }) + } + + Device (COM1) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + 51 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + + Device (PP20) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + Device (ETH1) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 1 }, + Package () { "gop-port-id", 2 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + Device (ETH2) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP0_PORT2 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 2 }, + Package () { "gop-port-id", 3 }, + Package () { "phy-mode", "rgmii-id"}, + } + }) + } + } + + Device (RNG0) + { + Name (_HID, "PRP0001") // _HID= : Hardware ID + Name (_UID, 0x00) // _UID= : Unique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + CP_GIC_SPI_CP0_EIP_RNG0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "inside-secure,safexcel-eip= 76" }, + } + }) + } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xCFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + PCI_ECAM_SIZE + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } + } +} diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc b/= Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc new file mode 100644 index 0000000..88f59ab --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc @@ -0,0 +1,41 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" +#include "Cn913xDbA/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Fadt.aslc new file mode 100644 index 0000000..ea396bd --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc @@ -0,0 +1,80 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \ + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_6_0_HEADLESS + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepStatusReg +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Gtdt.aslc new file mode 100644 index 0000000..46bfe37 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc @@ -0,0 +1,58 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +// active low, level triggered +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILI= TY + +// active high, level triggered +#define GTDT_WDG_FLAGS 0x0 + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog; +} ACPI_6_0_GTDT_STRUCTURE; +#pragma pack() + +ACPI_6_0_GTDT_STRUCTURE Gtdt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_GTDT_STRUCTURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= Address + 0x1, // UINT32 PlatformTim= erCount + sizeof (Gtdt.Header) // UINT32 PlatformTim= erOffset + }, { + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof (Gtdt.SbsaWatchdog), // UINT16 Length + 0x0, // UINT8 Reserved + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFram= ePhysicalAddress + FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogCon= trolFramePhysicalAddress + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTim= erGSIV + GTDT_WDG_FLAGS // UINT32 WatchdogTim= erFlags + }, +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Madt.aslc new file mode 100644 index 0000000..abd3cfc --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc @@ -0,0 +1,135 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceB= ase) +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define GICH_BASE 0xF0240000 +#define GICV_BASE 0xF0260000 +#define VGIC_MAINT_INT 25 + +#define GIC_MSI_FRAME0 0xF0280000 +#define GIC_MSI_FRAME1 0xF0290000 +#define GIC_MSI_FRAME2 0xF02A0000 +#define GIC_MSI_FRAME3 0xF02B0000 + +#define PMU_INTERRUPT_CPU0 130 +#define PMU_INTERRUPT_CPU1 131 +#define PMU_INTERRUPT_CPU2 132 +#define PMU_INTERRUPT_CPU3 133 + +#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_= PERFORMANCE_INTERRUPT_MODEL + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicC[4]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4]; +} ACPI_6_0_MADT_STRUCTURE; +#pragma pack(pop) + + +ACPI_6_0_MADT_STRUCTURE Madt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MADT_STRUCTURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId + 0x000, // AcpiCpu= Uid + 0x000, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU0, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId + 0x001, // AcpiCpu= Uid + 0x001, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU1, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId + 0x100, // AcpiCpu= Uid + 0x100, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU2, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId + 0x101, // AcpiCpu= Uid + 0x101, // Mpidr + PMU_INTERRUPT_FLAG, // Flags + PMU_INTERRUPT_CPU3, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDist= HwId + GICD_BASE, // GicDist= Base + 0x0, // GicDist= Vector + EFI_ACPI_6_0_GIC_V2 // GicVers= ion + ), + { + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiF= rameId + GIC_MSI_FRAME0, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiF= rameId + GIC_MSI_FRAME1, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiF= rameId + GIC_MSI_FRAME2, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiF= rameId + GIC_MSI_FRAME3, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Pptt.aslc new file mode 100644 index 0000000..f37c751 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc @@ -0,0 +1,210 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiHeader.h" + +#define NUM_CORES FixedPcdGet64 (PcdCoreCount) + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_2_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_2_PPTT_CORE Cores[2]; +} ACPI_6_2_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + ACPI_6_2_PPTT_CLUSTER Clusters[NUM_C= ORES / 2]; +} ACPI_6_2_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_2_PPTT_PACKAGE Packages[1]; +} ACPI_6_2_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 256 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + 3 * SIZE_16KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 3, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2C= ache), \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_512KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE(pid, cid, 0), = \ + PPTT_CORE(pid, cid, 1), = \ + } = \ +} + +ACPI_6_2_PPTT_STRUCTURE Pptt =3D { + { + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTU= RE_SIGNATURE, + ACPI_6_2_PPTT_STRUCTURE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVIS= ION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResour= ces */ + }, { + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 1, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_1MB, /* Size */ + 2048, /* NumberOfSets */ + 8, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#endif + } + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc new file mode 100644 index 0000000..f663d8a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -0,0 +1,49 @@ +/** @file + Serial Port Console Redirection Table (SPCR) + + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (c) 2019, Marvell International Ltd. and its affiliates. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include +#include + +#include "AcpiHeader.h" + +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + { EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] + MV_UART_AS32 (FixedPcdGet64(PcdSerialRegisterBase)), //= BaseAddress + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //= InterruptType + 0, //= Irq + 51, //= GlobalSystemInterrupt + 0, //= BaudRate + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //= Parity + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //= StopBits + 0, //= FlowControl + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //= TerminalType + EFI_ACPI_RESERVED_BYTE, //= Language + 0xFFFF, //= PciDeviceId + 0xFFFF, //= PciVendorId + 0, //= PciBusNumber + 0, //= PciDeviceNumber + 0, //= PciFunctionNumber + 0, //= PciFlags + 0, //= PciSegment + EFI_ACPI_RESERVED_DWORD //= Reserved2 +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:33 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 03/10] Marvell/Cn9130Db: Add DeviceTree Date: Thu, 15 Aug 2019 04:54:07 +0200 Message-Id: <1565837654-13258-4-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837678; bh=CIhAhtdr/xZ5TXYj6+gPpAA0Zsj0iDCy/a4e+Vo/XSU=; h=Cc:Date:From:Reply-To:Subject:To; b=rfyCwLZMEFnjUXDAewddiRqE0gpYcZlcOzayEUI/l/eQcfRfbJOwuj/jdDn2cVNeAGg 8axm5SbBipa8yqgWECtC+s2S/ITmXxPZZ2eiaCB1UysfXBWi9dED5HgVJlLHLw30psO7M kNrcXOLkKf2p3daosCCICHR5Q5wQhxnb4d4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds device tree sources which are common for Cn913x SoCs and the CN9130 development board (variant A). Wiring up of support will be done in the follow-up commits. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 +++++= +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 +++++= +++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++= ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 173 ++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 76 +++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 151 ++++++ 12 files changed, 1799 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.d= tsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf new file mode 100644 index 0000000..091a5b4 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9130-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model =3D "Marvell Armada AP806 Quad"; + compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x001>; + enable-method =3D "psci"; + }; + cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72", "arm,armv8"; + reg =3D <0x101>; + enable-method =3D "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +/dts-v1/; + +/ { + model =3D "Marvell Armada AP806"; + compatible =3D "marvell,armada-ap806"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + gpio0 =3D &ap_gpio; + spi0 =3D &spi0; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + ap806 { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + config-space@f0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + interrupts =3D ; + reg =3D <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x280000 0x1000>; + arm,msi-base-spi =3D <160>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m1: v2m@290000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x290000 0x1000>; + arm,msi-base-spi =3D <192>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2a0000 0x1000>; + arm,msi-base-spi =3D <224>; + arm,msi-num-spis =3D <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible =3D "arm,gic-v2m-frame"; + msi-controller; + reg =3D <0x2b0000 0x1000>; + arm,msi-base-spi =3D <256>; + arm,msi-num-spis =3D <32>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupt-parent =3D <&pic>; + interrupts =3D <17>; + }; + + odmi: odmi@300000 { + compatible =3D "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames =3D <4>; + reg =3D <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base =3D <128>, <136>, <144>, = <152>; + }; + + gicp: gicp@3f0040 { + compatible =3D "marvell,ap806-gicp"; + reg =3D <0x3f0040 0x10>; + marvell,spi-ranges =3D <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible =3D "marvell,armada-8k-pic"; + reg =3D <0x3f0100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + }; + + xor@400000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2"; + reg =3D <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent =3D <&gic_v2m0>; + clocks =3D <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x510600 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + i2c0: i2c@511000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x511000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + timeout-ms =3D <1000>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart0: serial@512000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + }; + + uart1: serial@512100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x512100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clocks =3D <&ap_clk 3>; + status =3D "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>; + interrupts =3D ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible =3D "marvell,armada-ap806-sdhci= "; + reg =3D <0x6e0000 0x300>; + interrupts =3D ; + clock-names =3D "core"; + clocks =3D <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status =3D "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x6f4000 0x2000>; + + ap_clk: clock { + compatible =3D "marvell,ap806-cloc= k"; + #clock-cells =3D <1>; + }; + + ap_pinctrl: pinctrl { + compatible =3D "marvell,ap806-pinc= trl"; + + uart0_pins: uart0-pins { + marvell,pins =3D "mpp11", = "mpp19"; + marvell,function =3D "uart= 0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible =3D "marvell,armada-8k-= gpio"; + offset =3D <0x1040>; + ngpios =3D <20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>; + }; + }; + + ap_thermal: thermal@6f808c { + compatible =3D "marvell,armada-ap806-therm= al"; + reg =3D <0x6f808c 0x4>, + <0x6f8084 0x8>; + }; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/S= ilicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi new file mode 100644 index 0000000..b6e5ded --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP110. + */ + +#include "armada-common.dtsi" + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0= xf00000) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP110_NAME: CP110_NAME { }; +}; + +&CP110_NAME { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&CP110_LABEL(icu)>; + ranges; + + config-space@CP110_BASE { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; + + CP110_LABEL(ethernet): ethernet@0 { + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>, + <&CP110_LABEL(core_clk)>; + clock-names =3D "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <0>; + gop-port-id =3D <0>; + status =3D "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <1>; + gop-port-id =3D <2>; + status =3D "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id =3D <2>; + gop-port-id =3D <3>; + status =3D "disabled"; + }; + }; + + CP110_LABEL(comphy): phy@120000 { + compatible =3D "marvell,comphy-cp110"; + reg =3D <0x120000 0x6000>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + CP110_LABEL(comphy0): phy@0 { + reg =3D <0>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy1): phy@1 { + reg =3D <1>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy2): phy@2 { + reg =3D <2>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy3): phy@3 { + reg =3D <3>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy4): phy@4 { + reg =3D <4>; + #phy-cells =3D <1>; + }; + + CP110_LABEL(comphy5): phy@5 { + reg =3D <5>; + #phy-cells =3D <1>; + }; + }; + + CP110_LABEL(mdio): mdio@12a200 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x12a200 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xmdio): mdio@12a600 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,xmdio"; + reg =3D <0x12a600 0x10>; + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(icu): interrupt-controller@1e0000 { + compatible =3D "marvell,cp110-icu"; + reg =3D <0x1e0000 0x440>; + #interrupt-cells =3D <3>; + interrupt-controller; + msi-parent =3D <&gicp>; + }; + + CP110_LABEL(rtc): rtc@284000 { + compatible =3D "marvell,armada-8k-rtc"; + reg =3D <0x284000 0x20>, <0x284080 0x24>; + reg-names =3D "rtc", "rtc-soc"; + interrupts =3D ; + status =3D "disabled"; + }; + + CP110_LABEL(thermal): thermal@400078 { + compatible =3D "marvell,armada-cp110-thermal"; + reg =3D <0x400078 0x4>, + <0x400070 0x8>; + }; + + CP110_LABEL(syscon0): system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + + CP110_LABEL(clk): clock { + compatible =3D "marvell,cp110-clock"; + status =3D "disabled"; + #clock-cells =3D <2>; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x100>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + + CP110_LABEL(gpio2): gpio@140 { + compatible =3D "marvell,armada-8k-gpio"; + offset =3D <0x140>; + ngpios =3D <31>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>; + interrupt-controller; + interrupts =3D , + , + , + ; + status =3D "disabled"; + }; + }; + + CP110_LABEL(usb3_0): usb3@500000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x500000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(usb3_1): usb3@510000 { + compatible =3D "marvell,armada-8k-xhci", + "generic-xhci"; + reg =3D <0x510000 0x4000>; + dma-coherent; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(sata0): sata@540000 { + compatible =3D "marvell,armada-8k-ahci", + "generic-ahci"; + reg =3D <0x540000 0x30000>; + dma-coherent; + interrupts =3D ; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(xor0): xor@6a0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(xor1): xor@6c0000 { + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2"; + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, + <&CP110_LABEL(x2core_clk)>; + }; + + CP110_LABEL(spi0): spi@700600 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700600 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(spi1): spi@700680 { + compatible =3D "marvell,armada-380-spi"; + reg =3D <0x700680 0x50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c0): i2c@701000 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(i2c1): i2c@701100 { + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x701100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart0): serial@702000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart1): serial@702100 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702100 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart2): serial@702200 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702200 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(uart3): serial@702300 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x702300 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-names =3D "baudclk", "apb_pclk"; + clocks =3D <&CP110_LABEL(slow_io_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible =3D "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg =3D <0x720000 0x54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(nand_clk)>, + <&CP110_LABEL(x2core_clk)>; + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>; + status =3D "disabled"; + }; + + CP110_LABEL(trng): trng@760000 { + compatible =3D "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg =3D <0x760000 0x7d>; + interrupts =3D ; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + status =3D "okay"; + }; + + CP110_LABEL(sdhci0): sdhci@780000 { + compatible =3D "marvell,armada-cp110-sdhci"; + reg =3D <0x780000 0x300>; + interrupts =3D ; + clock-names =3D "core", "axi"; + clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>; + dma-coherent; + status =3D "disabled"; + }; + + CP110_LABEL(crypto): crypto@800000 { + compatible =3D "inside-secure,safexcel-eip197"; + reg =3D <0x800000 0x200000>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(x2core_clk)>, + <&CP110_LABEL(x2core_clk)>; + dma-coherent; + }; + }; + + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_B= ASE(0) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_B= ASE(1) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie"; + reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names =3D "ctrl", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + msi-parent =3D <&gic_v2m0>; + + bus-range =3D <0 0xff>; + ranges =3D + /* non-prefetchable memory */ + <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_B= ASE(2) 0 0xf00000>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; + + num-lanes =3D <1>; + clock-names =3D "core", "reg"; + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>; + status =3D "disabled"; + }; + + /* 1 GHz fixed main PLL */ + CP110_LABEL(mainpll): CP110_LABEL(mainpll) { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(core_clk): CP110_LABEL(core_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <2>; + clock-div =3D <5>; + }; + + CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <3>; + }; + + CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { + compatible =3D "fixed-factor-clock"; + clocks =3D <&CP110_LABEL(mainpll)>; + #clock-cells =3D <0>; + clock-mult =3D <1>; + clock-div =3D <4>; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts new file mode 100644 index 0000000..9e4aa51 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "cn9130-db.dtsi" + +/ { + model =3D "Model: Marvell CN9130 development board (CP NOR) setup(= A)"; + compatible =3D "marvell,cn9130-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + i2c0 =3D &cp0_i2c0; + ethernet0 =3D &cp0_eth0; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth2; + }; + + memory@00000000 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +/* on-board eMMC - U9 */ +&ap_sdhci0 { + pinctrl-names =3D "default"; + bus-width =3D <8>; + status =3D "okay"; + vqmmc-supply =3D <&ap0_reg_sd_vccq>; +}; + +/* + * CP related configuration + */ +&cp0_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +&cp0_i2c1 { + status =3D "okay"; +}; + +/* CON 28 */ +&cp0_sdhci0 { + status =3D "okay"; +}; + +/* U54 */ +&cp0_nand_controller { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nand_pins>; + + nand@0 { + reg =3D <0>; + label =3D "main-storage"; + nand-rb =3D <0>; + nand-ecc-mode =3D "hw"; + nand-on-flash-bbt; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0 0x200000>; + }; + partition@200000 { + label =3D "Linux"; + reg =3D <0x200000 0xd00000>; + }; + partition@1000000 { + label =3D "Filesystem"; + reg =3D <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* U55 */ +&cp0_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_spi0_pins>; + reg =3D <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>; /* CS0 */ + status =3D "disabled"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency =3D <40000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; +}; + +/* SLM-1521-V2, CON6 */ +&cp0_pcie0 { + status =3D "okay"; + num-lanes =3D <4>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + status =3D "okay"; + /* SLM-1521-V2, CON2 */ +}; + +&cp0_mdio { + status =3D "okay"; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp0_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp0_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp0_sfp_eth0>; +}; + +/* CON56 */ +&cp0_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +/* CON57 */ +&cp0_eth2 { + status =3D "okay"; + phy =3D <&phy1>; + phy-mode =3D "rgmii-id"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi new file mode 100644 index 0000000..eeb96f6 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +#include "cn9130.dtsi" /* include SoC device tree */ + +/ { + model =3D "DB-CN-9130"; + compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy0: cp0_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus0>; + }; + + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0-xhci1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy1: cp0_usb3_phy1 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp0_reg_usb3_vbus1>; + }; + + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 15 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 + 3300000 0x0>; + }; + + ap0_reg_sd_vccq: ap0_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "ap0_sd_vccq"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&expander0 8 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 + 3300000 0x0>; + }; + + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp0_sd_vcc"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + cp0_sfp_eth0: sfp-eth0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp0_sfpp0_i2c>; + los-gpio =3D <&cp0_moudle_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp0_moudle_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp0_moudle_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp0_moudle_expander1 8 GPIO_ACTIVE_HIG= H>; + status =3D "disabled"; + }; +}; + +/* + * CP0 + */ +&cp0_i2c0 { + clock-frequency =3D <100000>; + + /* U36 */ + expander0: pca953x@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + status =3D "okay"; + }; + + /* U42 */ + eeprom0: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + pagesize =3D <0x20>; + }; + + /* U38 */ + eeprom1: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <0x20>; + }; +}; + +&cp0_i2c1 { + clock-frequency =3D <100000>; + + /* SLM-1521-V2 - U3 */ + i2c-mux@72 { /* verify address - depends on dpr */ + compatible =3D "nxp,pca9544"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x72>; + cp0_sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + /* U12 */ + cp0_moudle_expander1: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + + }; + }; +}; + + +&cp0_sdhci0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_sdhci_pins>; + bus-width =3D <4>; + no-1-8-v; + vqmmc-supply =3D <&cp0_reg_sd_vccq>; + vmmc-supply =3D <&cp0_reg_sd_vcc>; +}; + +&cp0_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy0>; + phy-names =3D "usb"; +}; + +&cp0_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy1>; + phy-names =3D "usb"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/= Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi new file mode 100644 index 0000000..97ea923 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +/* + * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and + * three CP110. + */ + +#include "armada-ap806-quad.dtsi" + +/ { + aliases { + gpio1 =3D &cp0_gpio1; + gpio2 =3D &cp0_gpio2; + spi1 =3D &cp0_spi0; + spi2 =3D &cp0_spi1; + }; +}; + +/* This defines used to calculate the base address of each CP */ +#define CP110_PCIE_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : = 0xf00000) +#define CP110_PCIE_BUS_MEM_CFG (0x82000000) + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 +#define CP110_BASE f2000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : \ + (0xe0000000 + (iface - 1) * 0x100= 0000)) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +#undef CP110_NUM +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/ { + model =3D "Marvell CN 9130"; + compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad", + "marvell,armada-ap806"; +}; + +&cp0_crypto { + status =3D "okay"; +}; + +&cp0_gpio1 { + status =3D "okay"; +}; + +&cp0_gpio2 { + status =3D "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,armada-7k-pinctrl"; + + cp0_devbus_pins: cp0-devbus-pins { + marvell,pins =3D "mpp15", "mpp16", "mpp17", + "mpp18", "mpp19", "mpp20", + "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function =3D "dev"; + }; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins =3D "mpp0", "mpp1", "mpp2", + "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11"; + marvell,function =3D "ge0"; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins =3D "mpp44", "mpp45", "mpp46", + "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52", + "mpp53", "mpp54", "mpp55"; + marvell,function =3D "ge1"; + }; + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { + marvell,pins =3D "mpp43"; + marvell,function =3D "gpio"; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins =3D "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; + marvell,function =3D "spi1"; + }; + nand_pins: nand-pins { + marvell,pins =3D + "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23", "mpp24", + "mpp25", "mpp26", "mpp27"; + marvell,function =3D "dev"; + }; + nand_rb: nand-rb { + marvell,pins =3D "mpp13"; + marvell,function =3D "nf"; + }; + }; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts new file mode 100644 index 0000000..f08a748 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "cn9130-db-A.dts" +#include "cn9131-db.dtsi" + +/ { + model =3D "Marvell CN9131 development board (CP NOR) setup(A)"; + compatible =3D "marvell,cn9131-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; +}; + +&cp1_ethernet { + status =3D "okay"; +}; + +/* CON50 */ +&cp1_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp1_sfp_eth1>; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi new file mode 100644 index 0000000..c8e425a --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NUM 1 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1= 000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) + +#include "armada-cp110.dtsi" + +/ { + model =3D "Marvell CN9131 development board"; + compatible =3D "marvell,cn9131-db", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + aliases { + gpio3 =3D &cp1_gpio1; + gpio4 =3D &cp1_gpio2; + ethernet3 =3D &cp1_eth0; + ethernet4 =3D &cp1_eth1; + }; + + cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_xhci0_vbus_pins>; + regulator-name =3D "cp1-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + cp1_usb3_0_phy0: cp1_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp1_reg_usb3_vbus0>; + }; + + cp1_sfp_eth1: sfp-eth1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp1_i2c0>; + los-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; + tx-disable-gpio =3D <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_sfp_pins>; + status =3D "disabled"; + }; +}; + +&cp1_crypto { + status =3D "okay"; +}; + +&cp1_gpio1 { + status =3D "okay"; +}; + +&cp1_gpio2 { + status =3D "okay"; +}; + +&cp1_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_i2c0_pins>; + status =3D "okay"; + clock-frequency =3D <100000>; +}; + +/* CON40 */ +&cp1_pcie0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_pcie_reset_pins>; + num-lanes =3D <2>; + num-viewport =3D <8>; + marvell,reset-gpio =3D <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy0 0 + &cp1_comphy1 0>; +}; + +&cp1_sata0 { + status =3D "okay"; + /* CON32 */ + sata-port@1 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy5 1>; + }; +}; + +/* U24 */ +&cp1_spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp1_spi0_pins>; + reg =3D <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>; /* CS0 */ + status =3D "okay"; + + spi-flash@0 { + #address-cells =3D <0x1>; + #size-cells =3D <0x1>; + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency =3D <40000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "U-Boot"; + reg =3D <0x0 0x200000>; + }; + + partition@400000 { + label =3D "Filesystem"; + reg =3D <0x200000 0xe00000>; + }; + }; + }; + +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp1_i2c0_pins: cp1-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp1_spi0_pins: cp1-spi-pins-0 { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= "; + marvell,function =3D "spi1"; + }; + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { + marvell,pins =3D "mpp3"; + marvell,function =3D "gpio"; + }; + cp1_sfp_pins: sfp-pins { + marvell,pins =3D "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function =3D "gpio"; + }; + cp1_pcie_reset_pins: cp1-pcie-reset-pins { + marvell,pins =3D "mpp0"; + marvell,function =3D "gpio"; + }; + }; +}; + +/* CON58 */ +&cp1_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy3 1>; + phy-names =3D "usb"; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts new file mode 100644 index 0000000..e9464f8 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -0,0 +1,76 @@ +/* + * copyright (c) 2019 marvell international ltd. + * + * spdx-license-identifier: gpl-2.0 + * https://spdx.org/licenses + */ + +#include "cn9131-db-A.dts" +#include "cn9132-db.dtsi" + +/ { + model =3D "Model: Marvell CN9132 development board (CP NOR) setup(= A)"; + compatible =3D "marvell,cn9132-db-A", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + aliases { + gpio5 =3D &cp2_gpio1; + gpio6 =3D &cp2_gpio2; + ethernet5 =3D &cp2_eth0; + }; +}; + +&cp2_ethernet { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp2_eth0 { + status =3D "okay"; + phy-mode =3D "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy4 0>; + managed =3D "in-band-status"; + sfp =3D <&cp2_sfp_eth0>; +}; + +/* SLM-1521-V2, CON6 */ +&cp2_pcie0 { + status =3D "okay"; + num-lanes =3D <2>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy0 0 + &cp2_comphy1 0>; +}; + +/* SLM-1521-V2, CON8 */ +&cp2_pcie2 { + status =3D "okay"; + num-lanes =3D <1>; + num-viewport =3D <8>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy5 2>; +}; + +&cp2_sata0 { + status =3D "okay"; + /* SLM-1521-V2, CON4 */ + sata-port@0 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy2 0>; + }; +}; + +/* CON 2 on SLM-1683 - microSD */ +&cp2_sdhci0 { + status =3D "okay"; +}; + +/* SLM-1521-V2, CON11 */ +&cp2_usb3_1 { + status =3D "okay"; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp2_comphy3 1>; +}; diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi new file mode 100644 index 0000000..8613607 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -0,0 +1,151 @@ +/* + * copyright (c) 2019 marvell international ltd. + * + * spdx-license-identifier: gpl-2.0 + * https://spdx.org/licenses + */ + +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NUM 2 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1= 000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) + +#include "armada-cp110.dtsi" + +/ { + model =3D "DB-CN-9132"; + compatible =3D "marvell,cn9132", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; + + cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp2-xhci0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + cp2_usb3_0_phy0: cp2_usb3_phy0 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp2_reg_usb3_vbus0>; + }; + + cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cp2-xhci1-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + cp2_usb3_0_phy1: cp2_usb3_phy1 { + compatible =3D "usb-nop-xceiv"; + vcc-supply =3D <&cp2_reg_usb3_vbus1>; + }; + + cp2_reg_sd_vccq: cp2_sd_vccq@0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "cp2_sd_vcc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1 3300000 0x0>; + }; + + cp2_sfp_eth0: sfp-eth0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp2_sfpp0_i2c>; + los-gpio =3D <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio =3D <&cp2_moudle_expander1 10 GPIO_ACTIVE_LO= W>; + tx-disable-gpio =3D <&cp2_moudle_expander1 9 GPIO_ACTIVE_H= IGH>; + tx-fault-gpio =3D <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIG= H>; + status =3D "disabled"; + }; +}; + +&cp2_crypto { + status =3D "okay"; +}; + +&cp2_gpio1 { + status =3D "okay"; +}; + +&cp2_gpio2 { + status =3D "okay"; +}; + +&cp2_i2c0 { + clock-frequency =3D <100000>; + + /* SLM-1521-V2 - U3 */ + i2c-mux@72 { + compatible =3D "nxp,pca9544"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x72>; + cp2_sfpp0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + /* U12 */ + cp2_moudle_expander1: pca9555@21 { + compatible =3D "nxp,pca9555"; + pinctrl-names =3D "default"; + gpio-controller; + #gpio-cells =3D <2>; + reg =3D <0x21>; + }; + }; + }; +}; + +&cp2_sdhci0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp2_sdhci_pins>; + bus-width =3D <4>; + cd-gpios =3D <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; + vqmmc-supply =3D <&cp2_reg_sd_vccq>; +}; + +&cp2_syscon0 { + cp2_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp2_i2c0_pins: cp2-i2c-pins-0 { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + cp2_sdhci_pins: cp2-sdhi-pins-0 { + marvell,pins =3D "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + }; +}; + +&cp2_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp2_usb3_0_phy0>; + phy-names =3D "usb"; +}; + +&cp2_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp2_usb3_0_phy1>; + phy-names =3D "usb"; +}; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45666): https://edk2.groups.io/g/devel/message/45666 Mute This Topic: https://groups.io/mt/32882735/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45667+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45667+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837680; cv=none; d=zoho.com; s=zohoarc; b=QNzZ5ZUm6jhhJB/6V7gjYmVhtNWZMeOFAvhxBCIV6Ul8ZfCMRf2CTTrtqyH2CcERNv08kW8f2A6fFlxJ1N2SKQKgOkx0k6Nb32taR1kPEEIQBzTj0tbxHy4cdhcrtqS52vKKsJWnm59Uk5I/WHw85wTUawbAv9GYnAPIA3o522A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837680; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=W1Q2TO2VizjkvEy2706hZa2aJkyGn+lSzdPy4vzLcoU=; b=VNnRRRhudrzeDJMevg2v6/b8NW4P50lm0brBb/Hbs1BHT8PKzV/ApX+ivSRXRH5up+F8BDFvVp1pjZ8TSHNBtoGoWD9r+AHCzYzdRaCib+Yc7R5M3axyI25pIMqXqLbOdMp9dMnZa/Zh8XuxShFxnuqoZT9nbh3vx9PZTC+uhOE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45667+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837680451640.2137615147509; Wed, 14 Aug 2019 19:54:40 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:38 -0700 X-Received: by mail-lj1-f175.google.com with SMTP id t14so998730lji.4 for ; Wed, 14 Aug 2019 19:54:37 -0700 (PDT) X-Gm-Message-State: APjAAAUGfBPA5+bwo6MEi2LbwcfSx8zXj37y/xwoSZGxXXLbQgjXcRIV e99WkFma4o5tL6ZckzNwNvirwKbYhlJkUA== X-Google-Smtp-Source: APXvYqwiHuaVkC76Zf1vAVO6igJwDjXROWqsvtNBsYmWynZUQ196qTqeEFbH20c4hiCr4g5jk1fWow== X-Received: by 2002:a05:651c:153:: with SMTP id c19mr1424109ljd.152.1565837675480; Wed, 14 Aug 2019 19:54:35 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:34 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 04/10] Marvell/Cn9130Db: Introduce board support Date: Thu, 15 Aug 2019 04:54:08 +0200 Message-Id: <1565837654-13258-5-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837679; bh=CcmXXEsoqQA99ADXPqay6cFUQ8KlvDIFxv70ZYTfhLU=; h=Cc:Date:From:Reply-To:Subject:To; b=twb6f0ubZbBUtsXk2mJO42ayIS6XEmAqw2PR62MFe5nCPuAorbmkAH83Y7+7HAPvuTy KekGP5Yjg6z4s5ziAfHw0yxX5n7ITBqy0kzMXS5XBwWf23HIq0DjYBz9DKwXCf08RwnBT vZlP9lWKRzquEqI9n99MMnl3LmLQRBrc20o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9130-DB setup A. Because the board is modular and can be extended to support also CN9131 and CN9132 SoC variants, extract common part into .dsc.inc file, which will be included by them. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc = | 107 +++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 46 +++++++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf = | 29 ++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.in= f | 37 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 19 +++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c = | 126 +++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 144 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc = | 18 +++ 8 files changed, 526 insertions(+) create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbA= BoardDescLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.h create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbA= BoardDescLib.c create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDis= coverableInitLib.c create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc new file mode 100644 index 0000000..33fb7cc --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -0,0 +1,107 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|2 + + # APN807 MPP + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP115 #0 MPP + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0x9 } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + + # SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + # PCIE + gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 + + # RTC + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + + # SoC Configuration Space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 + + # Variable store + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc new file mode 100644 index 0000000..d77785d --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -0,0 +1,46 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Cn9130DbA + PLATFORM_GUID =3D 087305a1-8ddd-4027-89ca-68a3ef78fcc7 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001000B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Cn913xDb/Cn913xDbA.f= df.inc + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc + +[Components.common] + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf + +[Components.AARCH64] + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf + +[LibraryClasses.common] + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDes= cLib.inf new file mode 100644 index 0000000..dfbdc84 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbABoardDescLib + FILE_GUID =3D d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaBoardDescLib + +[Sources] + Cn9130DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscove= rableInitLib.inf new file mode 100644 index 0000000..f7cfb36 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9130DbANonDiscoverableInitLib + FILE_GUID =3D 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NonDiscoverableInitLib + +[Sources] + NonDiscoverableInitLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + MvGpioLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Depex] + gMarvellPlatformInitCompleteProtocolGuid diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h new file mode 100644 index 0000000..2533c35 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -0,0 +1,19 @@ +/** +* +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef __NON_DISCOVERABLE_INIT_LIB_H__ +#define __NON_DISCOVERABLE_INIT_LIB_H__ + +#define CN9130_DB_IO_EXPANDER0 0 +#define CN9130_DB_VBUS0_PIN 0 +#define CN9130_DB_VBUS0_LIMIT_PIN 4 +#define CN9130_DB_VBUS1_PIN 1 +#define CN9130_DB_VBUS1_LIMIT_PIN 5 +#define CN9130_DB_SDMMC_VCC_PIN 14 +#define CN9130_DB_SDMMC_VCCQ_PIN 15 + +#endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescL= ib.c new file mode 100644 index 0000000..2b46d14 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -0,0 +1,126 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander =3D { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount =3D 1; + *GpioExpanders =3D &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xD0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xDFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x10000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D MAX_UINT64, + .PcieMmio64WinSize =3D 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc =3D mSdMmcDescTemplate; + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c new file mode 100644 index 0000000..598c649 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -0,0 +1,144 @@ +/** +* +* Copyright (c) 2017, Linaro Ltd. All rights reserved. +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "NonDiscoverableInitLib.h" + +STATIC +EFI_STATUS +EFIAPI +ConfigurePins ( + IN CONST MV_GPIO_PIN *VbusPin, + IN UINTN PinCount, + IN MV_GPIO_DRIVER_TYPE DriverType + ) +{ + EMBEDDED_GPIO_MODE Mode; + EMBEDDED_GPIO_PIN Gpio; + EMBEDDED_GPIO *GpioProtocol; + EFI_STATUS Status; + UINTN Index; + + Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _)); + return Status; + } + + for (Index =3D 0; Index < PinCount; Index++) { + Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0; + Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber); + GpioProtocol->Set (GpioProtocol, Gpio, Mode); + VbusPin++; + } + + return EFI_SUCCESS; +} + +STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0XhciVbusPins, + ARRAY_SIZE (mCp0XhciVbusPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCC_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCCQ_PIN, + FALSE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0SdMmcInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0SdMmcPins, + ARRAY_SIZE (mCp0SdMmcPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +NON_DISCOVERABLE_DEVICE_INIT +EFIAPI +NonDiscoverableDeviceInitializerGet ( + IN NON_DISCOVERABLE_DEVICE_TYPE Type, + IN UINTN Index + ) +{ + if (Type =3D=3D NonDiscoverableDeviceTypeXhci) { + switch (Index) { + case 0: + case 1: + return Cp0XhciInit; + } + } + + if (Type =3D=3D NonDiscoverableDeviceTypeSdhci) { + switch (Index) { + case 1: + return Cp0SdMmcInit; + } + } + + return NULL; +} diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn913xDbA.fdf.inc new file mode 100644 index 0000000..0c321d1 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -0,0 +1,18 @@ +# +# Copyright (C) 2019 Marvell International Ltd. and its affiliates +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-board additional content of the DXE phase firmware volume + + INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf + +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf +!endif --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45667): https://edk2.groups.io/g/devel/message/45667 Mute This Topic: https://groups.io/mt/32882736/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45668+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45668+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837680; cv=none; d=zoho.com; s=zohoarc; b=BwzFeXIImZp01ztdbNRwQ+Nan4HwnboKTmUEF27BlTCOXcy770UKni90K0gLXUqx2gSAceONiaqE8Gx2aUFxA7yeDz+6lzivaVHwPPESkQDdGyeNgQxcBHrnuV62R0o/ppL9vdi13U2pV8ijMLJjH17T8ZAKnZp/RUPa+FF7mTA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837680; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=azdSaVjPfbOEj8CMoKfUdo+ZWRtOVcngjXWZltrqMaE=; b=S+1IRFgYWpsrO1p8gls8gjI9cMT2Ivgp5rr+cJVrPBPLGPxaTNEznhkSSycN0nC6z+sOAa9dXFvVBE8u4ub94mWhz/acr7/dI93mVaK8Sx5jjd8P49rRWDprledoRtuNpHqosUpfVuyxjvzdDbOmfzXmgR55ZIgq2vfbaS23px4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45668+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837680867990.4244939157893; Wed, 14 Aug 2019 19:54:40 -0700 (PDT) Return-Path: X-Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:39 -0700 X-Received: by mail-lf1-f68.google.com with SMTP id v16so697920lfg.11 for ; Wed, 14 Aug 2019 19:54:38 -0700 (PDT) X-Gm-Message-State: APjAAAUjvFwJDWOND3euk2jeuAEGOF5OdMKOBPajGb6kuuyX95AyVHqm c//NEvJIbcxPOmHmGyGpqpmN2gyuLATD2w== X-Google-Smtp-Source: APXvYqwPbcflQxyxxx/c5Ajzf1NxpNdx7zB/gSpMBYIi5iQekMyRL4WzZ3jgvxhQe7Sh6Nqf+MFRnA== X-Received: by 2002:ac2:5ec3:: with SMTP id d3mr1220517lfq.44.1565837676811; Wed, 14 Aug 2019 19:54:36 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:36 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 05/10] Marvell/Library: ArmadaSoCDescLib: Extend Xenon information Date: Thu, 15 Aug 2019 04:54:09 +0200 Message-Id: <1565837654-13258-6-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837679; bh=BfOSuD4gW51lREzpLTyXv9P0XVi1pLqvAAM3QL04kZo=; h=Cc:Date:From:Reply-To:Subject:To; b=ZLyxluy6uaN1l84swbJacIHCdKaVqYUI67NRNLhcGVTyBDuZu8e0R7+JK3huCdxo/Km uKtFHwhhifmVajMPVJmbsLXDx2F9c3v6wlHrpB4QdlClsTrFo7EbkkP4EEqCcHPkAYkv3 0Vpwm16Lo1ZqxjDoJY4ZpYBVd0lnouxqouI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hitherto SoC description library code assumed that there could be only two Xenon SdMmc controller instances in the SoC. Remove this limitation, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 5 +-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 34 +++++++++++++------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 0296d43..265b4f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -90,8 +90,9 @@ // // Platform description of SDMMC controllers // -#define MV_SOC_MAX_SDMMC_COUNT 2 -#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) +#define MV_SOC_SDMMC_PER_CP_COUNT 1 +#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000 +#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000) =20 // // Platform description of UTMI PHY's diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 5947601..3ffd57e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -349,26 +349,36 @@ EFI_STATUS EFIAPI ArmadaSoCDescSdMmcGet ( IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, - IN OUT UINTN *DescCount + IN OUT UINTN *Count ) { - MV_SOC_SDMMC_DESC *Desc; - UINTN Index; + MV_SOC_SDMMC_DESC *SdMmc; + UINTN CpCount, CpIndex; =20 - Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); - if (Desc =3D=3D NULL) { + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT; + SdMmc =3D AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC)); + if (SdMmc =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); return EFI_OUT_OF_RESOURCES; } =20 - for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { - Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); - Desc[Index].SdMmcMemSize =3D SIZE_1KB; - Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; - } + *SdMmcDesc =3D SdMmc; + + /* AP80x controller */ + SdMmc->SdMmcBaseAddress =3D MV_SOC_AP80X_SDMMC_BASE; + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; =20 - *SdMmcDesc =3D Desc; - *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + /* CP11x controllers */ + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + SdMmc->SdMmcBaseAddress =3D MV_SOC_CP_SDMMC_BASE (CpIndex); + SdMmc->SdMmcMemSize =3D SIZE_1KB; + SdMmc->SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; + } =20 return EFI_SUCCESS; } --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:37 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 06/10] Marvell/Library: MppLib: Allow to configure more Xenon PHYs Date: Thu, 15 Aug 2019 04:54:10 +0200 Message-Id: <1565837654-13258-7-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837681; bh=LSbAvE0ZaCdGMCxl6gU/wA8spm53A9GF2S6UKsmWYTc=; h=Cc:Date:From:Reply-To:Subject:To; b=Cf+s9vc13kX6ZhqGG8Ky4NsDcwuBJNe4SrlBtM8U+iFO052QgYpir3jjOa+nQ2YdTtX iQO+9kHA4waUEL1xGg+v96qxqquGJ5ELLanhSZztK5JCIDy8Mw6jWl8aS/tkmVUz74tqL cS3HLVh6jbQocd7iI4AG/jJ3jED0/ztL8O8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hitherto MppLib code assumed that there could be only two Xenon SdMmc controllers' PHYs. Remove this limitation, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Library/MppLib/MppLib.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Libr= ary/MppLib/MppLib.c index 40d9077..f20668d 100644 --- a/Silicon/Marvell/Library/MppLib/MppLib.c +++ b/Silicon/Marvell/Library/MppLib/MppLib.c @@ -139,11 +139,9 @@ SetSdMmcPhyMpp ( case 0: Offset =3D SD_MMC_PHY_AP_MPP_OFFSET; break; - case 1: + default: Offset =3D SD_MMC_PHY_CP0_MPP_OFFSET; break; - default: - return; } =20 /* --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:38 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 07/10] Marvell/Library: IcuLib: Fix debug information Date: Thu, 15 Aug 2019 04:54:11 +0200 Message-Id: <1565837654-13258-8-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837682; bh=19Itv7sACm2HatdxKoUj+BaFOTrPYhC5CpOffqpwM7s=; h=Cc:Date:From:Reply-To:Subject:To; b=t+hnBCOBMyCTD8PUhCfd6HZUO5ppeYRsW5PWgDJKyibM+YX6A7tk+0t83wJ0VoF5eMj jzAbQOiKZwbA8OZ48lq3imQNCxRgy6dII8EZhvJNeZ1NOihVSsAQZg73IPo9oAKxCfnLf OGxNLqKxz6UZ0kiheLeI3dp5bTYpGJxilzI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In case the number of CP11x components exceeded the maximum of currently supported, the user is informed with the information. It turned out that the print arguments were incorrect - fix it. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c index 422388c..8d99409 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.c +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -285,8 +285,8 @@ ArmadaIcuInitialize ( if (CpCount > ICU_MAX_SUPPORTED_UNITS) { DEBUG ((DEBUG_ERROR, "%a: Default ICU to GIC mapping is available for maximum %d CP110 un= its", - ICU_MAX_SUPPORTED_UNITS, - __FUNCTION__)); + __FUNCTION__, + ICU_MAX_SUPPORTED_UNITS)); CpCount =3D ICU_MAX_SUPPORTED_UNITS; } =20 --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45670): https://edk2.groups.io/g/devel/message/45670 Mute This Topic: https://groups.io/mt/32882740/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45671+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45671+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837684; cv=none; d=zoho.com; s=zohoarc; b=YDZRBeGtGUSoCtefWw0tYoO9h97hy1QE1A6FONxI4KsIlGyWr72kWAqZ/vhvIRxT8EVGfHuv501TuUxvtkqE+pJdgw3XAixlfA+b/UqRmvq5wHd4W56bMKNM1IC37KKZTiy7YmJ+BEiZMzuvYGHcoJubkG6OjQ7HRIfeTvweWic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837684; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=IG+WsyQVnIjLIPYU6f4H1bDhSzXbsVlrB+eHtC/YEIY=; b=CXyZe/LaZ590fFGGcL4D3TeWEIdb9WM6Pum8Ms0+tp3C2++xhvnmgYy0jZZcpRdqPBn1u2ctYTGw8ndYdJHT1ubjNz9nk5PLQ39lF56kuK25sNuFACQ6fhq2GPAH3nxzBJ0UUbMxu5hlXUpEOGzk+iagtfG5bLIMqdP9oocRsRE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45671+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837684688393.82096596495967; Wed, 14 Aug 2019 19:54:44 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:43 -0700 X-Received: by mail-lj1-f169.google.com with SMTP id f9so952769ljc.13 for ; Wed, 14 Aug 2019 19:54:42 -0700 (PDT) X-Gm-Message-State: APjAAAXrnTvXqgGkdtDVMx+ql+GhsOopeDn1+XDa1Q25TG3pM7J2rOId ziSxRusYTLYoaL/an9xLeNO/gT94mgjDvw== X-Google-Smtp-Source: APXvYqx3g/Pr76yf/pjCktdn+fUr4/eTtNDb4olbT62lfnSqVhhQlDDTAcgfijTJNke2XFEMZSUnXw== X-Received: by 2002:a2e:b042:: with SMTP id d2mr1371414ljl.202.1565837680598; Wed, 14 Aug 2019 19:54:40 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:39 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 08/10] Marvell/Cn9131Db: Introduce board support Date: Thu, 15 Aug 2019 04:54:12 +0200 Message-Id: <1565837654-13258-9-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837683; bh=pMnz+BBYrDMvmmxXi04T8IdAjq/0b6ZG5qRXw1B5kyY=; h=Cc:Date:From:Reply-To:Subject:To; b=xGTdIxS4raRUJUxSon1i0RnthCSlkX4q7xSH5z6HbXjjbZYkKs575mWaW2/BVdpCyV6 wkGw3Kh8jZguRw5Oxovm3h1UWpIR3f/hWHIGBzmyH30vGKlKHio1bnR6pzlVkMmCPWzwP rxXdI3kYJR6rvbuvFm2yubCu2TAF9buohO8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9131-DB setup A. In order to build this variant, '-D CN9131' flag should be added. Otherwise the default (CN9130) will be compiled. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc = | 72 ++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 7 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf = | 57 ++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf = | 22 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h = | 2 + Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 29 ++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl = | 98 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi = | 26 +++--- 9 files changed, 303 insertions(+), 12 deletions(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.= asl diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.dsc.inc new file mode 100644 index 0000000..7235b9f --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9131 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # CP115 #1 MPP + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0= x7, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: UNCONNECTED + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_D= EFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index d77785d..5aca5a1 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -13,7 +13,11 @@ # ##########################################################################= ###### [Defines] +!if $(CN9131) + PLATFORM_NAME =3D Cn9131DbA +!else PLATFORM_NAME =3D Cn9130DbA +!endif PLATFORM_GUID =3D 087305a1-8ddd-4027-89ca-68a3ef78fcc7 PLATFORM_VERSION =3D 0.1 DSC_SPECIFICATION =3D 0x0001000B @@ -34,6 +38,9 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +!if $(CN9131) +!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc +!endif =20 [Components.common] Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf new file mode 100644 index 0000000..bbf1b51 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -0,0 +1,57 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn9131DbA/Ssdt.asl + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9131 diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf new file mode 100644 index 0000000..8108197 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9131DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9131-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index 2533c35..6618737 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -15,5 +15,7 @@ #define CN9130_DB_VBUS1_LIMIT_PIN 5 #define CN9130_DB_SDMMC_VCC_PIN 14 #define CN9130_DB_SDMMC_VCCQ_PIN 15 +#define CN9131_DB_VBUS0_PIN 3 +#define CN9131_DB_VBUS0_LIMIT_PIN 2 =20 #endif diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index b5fd397..2838676 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -18,6 +18,8 @@ =20 #if defined(CN9130) #define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#elif defined (CN9131) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ',= ' ') #endif =20 /** diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index 598c649..dded150 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -91,6 +91,33 @@ Cp0XhciInit ( MV_GPIO_DRIVER_TYPE_PCA95XX); } =20 +STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp1XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp1XhciVbusPins, + ARRAY_SIZE (mCp1XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet ( case 0: case 1: return Cp0XhciInit; + case 2: + return Cp1XhciInit; } } =20 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl new file mode 100644 index 0000000..99bc751 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -0,0 +1,98 @@ +/** @file + + Secondary System Description Table Fields (SSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_USB_H1 + } + }) + } + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + } + } +} diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi index c8e425a..9c9dfb6 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi @@ -6,15 +6,23 @@ */ =20 #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE =20 /* CP110-1 Settings */ +#define CP110_NAME cp1 #define CP110_NUM 1 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1= 000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) +#define CP110_BASE f4000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) =20 #include "armada-cp110.dtsi" =20 @@ -93,12 +101,6 @@ =20 &cp1_sata0 { status =3D "okay"; - /* CON32 */ - sata-port@1 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 1>; - }; }; =20 /* U24 */ @@ -138,7 +140,7 @@ =20 &cp1_syscon0 { cp1_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; + compatible =3D "marvell,armada-7k-pinctrl"; =20 cp1_i2c0_pins: cp1-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:41 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 09/10] Marvell/Cn9132Db: Introduce board support Date: Thu, 15 Aug 2019 04:54:13 +0200 Message-Id: <1565837654-13258-10-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837685; bh=RKwoA7++oYlHVv/slFrUCoSnVb5CTeTslmAasnK7blw=; h=Cc:Date:From:Reply-To:Subject:To; b=f7CDOmQXgQWyLpmRG6kBhDMs2P0n4nPTy27bKBQZAhuDLHYSs2Y6vGztuXa4h/R6zc0 uZuChNTJK91z1tNTJu5d18bHHJ+oGJrnXurOhHZC6AsbcN6qo4VeMtgDNkRvplR7KuLdS 1EDaWe5s2Ga+01PE9A9VqzUNhTsiKFjIhrs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9132-DB setup A. Note the ACPI is not yet available for this variant, due to the current ICU (CP1xx interrupt controller) support implementation. In order to build this variant, '-D CN9132' flag should be added. Otherwise the default (CN9130) will be compiled. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc = | 72 +++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc = | 15 ++- Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf = | 29 +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf = | 22 ++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 4 + Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c = | 135 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 42 ++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc = | 2 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts = | 6 - Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi = | 20 ++- 10 files changed, 333 insertions(+), 14 deletions(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbA= BoardDescLib.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbA= BoardDescLib.c diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9132DbA.dsc.inc new file mode 100644 index 0000000..a0b90fa --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9132 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|4 + + # CP115 #2 MPP + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x9, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0= x0, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: SATA0 5 Gbps + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0= } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index 5aca5a1..1b28fae 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -13,7 +13,9 @@ # ##########################################################################= ###### [Defines] -!if $(CN9131) +!if $(CN9132) + PLATFORM_NAME =3D Cn9132DbA +!elseif $(CN9131) PLATFORM_NAME =3D Cn9131DbA !else PLATFORM_NAME =3D Cn9130DbA @@ -38,16 +40,25 @@ =20 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc -!if $(CN9131) +!if $(CN9131) || $(CN9132) !include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc !endif +!if $(CN9132) +!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc +!endif =20 [Components.common] Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf =20 +!ifndef $(CN9132) [Components.AARCH64] Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf +!endif =20 [LibraryClasses.common] +!if $(CN9132) + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132D= bABoardDescLib.inf +!else ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf +!endif NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDes= cLib.inf new file mode 100644 index 0000000..27a0214 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9132DbABoardDescLib + FILE_GUID =3D cf7a0f12-45fe-417b-9c34-053605973b68 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaBoardDescLib + +[Sources] + Cn9132DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf new file mode 100644 index 0000000..c9e3b04 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9132DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9132-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index 6618737..084bea0 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -17,5 +17,9 @@ #define CN9130_DB_SDMMC_VCCQ_PIN 15 #define CN9131_DB_VBUS0_PIN 3 #define CN9131_DB_VBUS0_LIMIT_PIN 2 +#define CN9132_DB_VBUS0_PIN 2 +#define CN9132_DB_VBUS0_LIMIT_PIN 0 +#define CN9132_DB_VBUS1_PIN 3 +#define CN9132_DB_VBUS1_LIMIT_PIN 1 =20 #endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescL= ib.c new file mode 100644 index 0000000..d2846dd --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c @@ -0,0 +1,135 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander =3D { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount =3D 1; + *GpioExpanders =3D &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0xD0000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0xDFF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x10000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D MAX_UINT64, + .PcieMmio64WinSize =3D 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF6780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc =3D mSdMmcDescTemplate; + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index dded150..42dc54a 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -118,6 +118,45 @@ Cp1XhciInit ( MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); } =20 +STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp2XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp2XhciVbusPins, + ARRAY_SIZE (mCp2XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet ( return Cp0XhciInit; case 2: return Cp1XhciInit; + case 3: + case 4: + return Cp2XhciInit; } } =20 diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn913xDbA.fdf.inc index 0c321d1..78bdb79 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -12,7 +12,9 @@ # DTB INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf =20 +!ifndef $(CN9132) !if $(ARCH) =3D=3D AARCH64 # ACPI support INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf !endif +!endif diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts index e9464f8..724d7dc 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -55,12 +55,6 @@ =20 &cp2_sata0 { status =3D "okay"; - /* SLM-1521-V2, CON4 */ - sata-port@0 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp2_comphy2 0>; - }; }; =20 /* CON 2 on SLM-1683 - microSD */ diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi index 8613607..7dc6c6e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -6,15 +6,23 @@ */ =20 #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE =20 /* CP110-1 Settings */ +#define CP110_NAME cp2 #define CP110_NUM 2 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1= 000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) +#define CP110_BASE f6000000 +#define CP110_PCIE0_BASE f6600000 +#define CP110_PCIE1_BASE f6620000 +#define CP110_PCIE2_BASE f6640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) =20 #include "armada-cp110.dtsi" =20 @@ -124,7 +132,7 @@ =20 &cp2_syscon0 { cp2_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; + compatible =3D "marvell,armada-7k-pinctrl"; =20 cp2_i2c0_pins: cp2-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45672): https://edk2.groups.io/g/devel/message/45672 Mute This Topic: https://groups.io/mt/32882742/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 4 12:24:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45673+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45673+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565837686; cv=none; d=zoho.com; s=zohoarc; b=NmSZWEnHaJTHm28V2+ifCNefX4kCbrRl9Ph8Aqy5W1BACpbk0bqvuuLn9ydOfwiOuFC3vSXEwWfuxR1j5P7Mcqx5XEWDrvLB91yyXzaHzSo0bxXOFFZ46KMeRr0LGOkm6kskYV7a5e32lE3N47KwJefMGmiI3r2TzMnYzWvs1wQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837686; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Mert53W6mIKWVVjDfpLjb94FvDHEJ+YgFNt5PvZl6oY=; b=dPJfrqYPkm1aIaMpQs5mFWdh+w7mvTKcOJvi0dY5lX16FA27Ow5laL8qJLM28JFOdnuJurCX+oopgDhEkqlIWuxNW/tWnuEUhijd5NigpKZNa5GuQSlHXxFGF07JVLKuMXpRdKNonEc69jQCG215k9wmncN08MRoZW85heqFqoA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45673+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837686974404.68985283422876; Wed, 14 Aug 2019 19:54:46 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:45 -0700 X-Received: by mail-lj1-f194.google.com with SMTP id l14so974068ljj.9 for ; Wed, 14 Aug 2019 19:54:44 -0700 (PDT) X-Gm-Message-State: APjAAAVEV2EllhM4k5phjtFMn0kEgUMuOezQsH63Tu79tBdao8G7YInI 0Xer+vGOsXoQDji6JIOtwgFjSdGspBekbg== X-Google-Smtp-Source: APXvYqwLI5ubd/puBr2A4LbywTqxjopsnFXev7+aOW2pVdLxE1BL2/jHuwJlPrhdlfDkJueKPJAh9g== X-Received: by 2002:a2e:7018:: with SMTP id l24mr1403483ljc.165.1565837682919; Wed, 14 Aug 2019 19:54:42 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:42 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2 10/10] Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name Date: Thu, 15 Aug 2019 04:54:14 +0200 Message-Id: <1565837654-13258-11-git-send-email-mw@semihalf.com> In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837685; bh=tPL9BLChiyBkwEf6rhwmER9nLD1CgEC2/g0vUuOLINM=; h=Cc:Date:From:Reply-To:Subject:To; b=Ko/4BmfO5v92c+UbBAiYKGsjVBXM439v8CGqGN8zPfMW7aDMrgXjDkRHrxw/xdyjrDJ mp9Yc7JX2tVv3hf4K7RpEHL7Ba/3ahRA3UA8i1EjFsAAqClqzM38aVrOt86sfTnTTJ2UD ZcrW7y+NtK7Y70hOK4paXlH8tZzLNKv3CXc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SmbiosPlatformDxe is used both by Armada 7k8k and CN913x platforms. Replace board name placeholder in order to avoid confusion. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index 08f4fa7..cdacd90 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -102,7 +102,7 @@ STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 =3D { =20 STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] =3D { "Marvell \0",/* Manufacturer */ - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ + "Marvell Development Board \0",/* Product Name placeholder*/ "Revision unknown \0",/* Version placeholder */ " \0",/* 32 character buffer */ NULL @@ -130,7 +130,7 @@ STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 =3D { =20 STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] =3D { "Marvell \0",/* Manufacturer */ - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ + "Marvell Development Board \0",/* Product Name placeholder*/ "Revision unknown \0",/* Version placeholder */ "Serial Not Set \0",/* Serial */ "Base of Chassis \0",/* Board location */ --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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