From nobody Mon Feb 9 19:53:35 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45048+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45048+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565220663; cv=none; d=zoho.com; s=zohoarc; b=jVcAmWqskVE+8052NKSO9rtjAeBbEP/ouEN2H1RH3ZZ6pas2X2+uw0rXkqxs4ujnAmp3Tn/smapTFZzugKn/WNHBk00zDGjwY/QP5y34AJgPAa+br0zTJp4aEEzd6Vpxzc/DB2iW7r50nPklvf7oK+6YO46pKY+414/h4J43X+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565220663; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZL5jcgYc/ekJDnSV5yjsVq5xYRaPxDzoaN9wBEbT4oc=; b=FV8lNR0+0KqqoYFL16ek8P/Reb88yFD1fIn/jL2XSDrmpxrm22HITGAh1nWQa5RxfiJBKFvTXwU9/rKPhfaG4y2xysp5fl0fThIBEX04Hu/jnn9QGTN0tpwR1FFmYnvF6GhoK3XyiMBoGSDm1kh7cCFmoOAe5YZ+foyEibcVyXY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45048+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565220663077631.9112090696096; Wed, 7 Aug 2019 16:31:03 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by groups.io with SMTP; Wed, 07 Aug 2019 16:31:01 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id d24so87054617ljg.8 for ; Wed, 07 Aug 2019 16:31:01 -0700 (PDT) X-Gm-Message-State: APjAAAV/A/G9geTn2ZW5x3zEQyUjUcs9idMNnhwGVEbOOsI8fbzpCL8M kHxNEhyzDCfTG1FNFrt3DxbHEsqxjkhMvQ== X-Google-Smtp-Source: APXvYqwQQsettCpGsaLsa1FK7ztd00UkrS1PE7c+xvrRfh2b4urtmtfzebwtN4VC1gp0bJbsKrKGOQ== X-Received: by 2002:a05:651c:1105:: with SMTP id d5mr6187093ljo.161.1565220659013; Wed, 07 Aug 2019 16:30:59 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id i62sm18359206lji.14.2019.08.07.16.30.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Aug 2019 16:30:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH 7/9] Marvell/Cn9131Db: Introduce board support Date: Thu, 8 Aug 2019 01:30:28 +0200 Message-Id: <1565220630-1653-8-git-send-email-mw@semihalf.com> In-Reply-To: <1565220630-1653-1-git-send-email-mw@semihalf.com> References: <1565220630-1653-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565220662; bh=fM9s7illukIoUgt/krlvinEj56yYWXbofpoZt5LXk28=; h=Cc:Date:From:Reply-To:Subject:To; b=HY/wBTKuRg2ugLZcxicjJvJDQhFaQypgDufpMW4Q+lWYh/kms6xi3KQiPkZWTFGXZGy DRFjCT+FxrXBYAV661XZVSZGp83xF52I/O1sBk9fCXAai1jIV1V2W9xt5BpqIbE2pbDA9 Lg33vTpDxBpipOVbxxw1UPqWUvvACFV91co= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces all necessary components required for building EDK2 firmware for CN9131-DB setup A. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc = | 72 ++++++++++++++ Platform/Marvell/Cn913xDb/Cn9131DbA.dsc = | 47 ++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf = | 57 ++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf = | 22 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h = | 2 + Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 29 ++++++ Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc = | 18 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl = | 98 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi = | 26 +++--- 10 files changed, 361 insertions(+), 12 deletions(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.= asl diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.dsc.inc new file mode 100644 index 0000000..7235b9f --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9131 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # CP115 #1 MPP + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0= x7, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: UNCONNECTED + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_D= EFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn9131DbA.dsc new file mode 100644 index 0000000..8f926cf --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc @@ -0,0 +1,47 @@ +## @file +# Component description file for the CN9131 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Cn9131DbA + PLATFORM_GUID =3D 9fcb32d0-ea4e-4e9c-863d-06d90b160855 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001000B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Cn913xDb/Cn9131DbA.f= df.inc + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc + +[Components.common] + Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf + +[Components.AARCH64] + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf + +[LibraryClasses.common] + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130D= bABoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/= NonDiscoverableInitLib.inf diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf new file mode 100644 index 0000000..bbf1b51 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -0,0 +1,57 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PlatformAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Cn9131DbA/Ssdt.asl + Cn913xDbA/Dsdt.asl + Cn913xDbA/Mcfg.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + +[BuildOptions] + *_*_*_ASLCC_FLAGS =3D -DCN9131 diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf new file mode 100644 index 0000000..8108197 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn9131DbADeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + cn9131-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index 2533c35..6618737 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -15,5 +15,7 @@ #define CN9130_DB_VBUS1_LIMIT_PIN 5 #define CN9130_DB_SDMMC_VCC_PIN 14 #define CN9130_DB_SDMMC_VCCQ_PIN 15 +#define CN9131_DB_VBUS0_PIN 3 +#define CN9131_DB_VBUS0_LIMIT_PIN 2 =20 #endif diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index b5fd397..2838676 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -18,6 +18,8 @@ =20 #if defined(CN9130) #define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',= ' ') +#elif defined (CN9131) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ',= ' ') #endif =20 /** diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index 598c649..dded150 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -91,6 +91,33 @@ Cp0XhciInit ( MV_GPIO_DRIVER_TYPE_PCA95XX); } =20 +STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP1_CONTROLLER0, + CN9131_DB_VBUS0_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp1XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp1XhciVbusPins, + ARRAY_SIZE (mCp1XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet ( case 0: case 1: return Cp0XhciInit; + case 2: + return Cp1XhciInit; } } =20 diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.fdf.inc new file mode 100644 index 0000000..8ae449d --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc @@ -0,0 +1,18 @@ +# +# Copyright (C) 2019 Marvell International Ltd. and its affiliates +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-board additional content of the DXE phase firmware volume + + INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131D= bA.inf + +!if $(ARCH) =3D=3D AARCH64 + # ACPI support + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/C= n9131DbA.inf +!endif diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl new file mode 100644 index 0000000..59145b5 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -0,0 +1,98 @@ +/** @file + + Secondary System Description Table Fields (SSDT) + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "IcuInterrupts.h" + +DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131DBA", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "LNRO001E") // _HID: Hardware ID + Name (_UID, 0x00) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4540000, // Address Base (MMIO) + 0x00030000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_SATA_H0 + } + }) + } + + Device (XHC2) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + Memory32Fixed (ReadWrite, + 0xF4510000, // Address Base (MMIO) + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP1_USB_H1 + } + }) + } + Device (PP21) + { + Name (_HID, "MRVL0110") // _HID: H= ardware ID + Name (_CCA, 0x01) // Cache-c= oherent controller + Name (_UID, 0x00) // _UID: U= nique ID + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 333333333 }, + } + }) + Device (ETH0) + { + Name (_ADR, 0x0) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, ) + { + CP_GIC_SPI_PP2_CP1_PORT0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port-id", 0 }, + Package () { "gop-port-id", 0 }, + Package () { "phy-mode", "10gbase-kr"}, + } + }) + } + } + } +} diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi index c8e425a..9c9dfb6 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi @@ -6,15 +6,23 @@ */ =20 #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE =20 /* CP110-1 Settings */ +#define CP110_NAME cp1 #define CP110_NUM 1 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1= 000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(i= face)) +#define CP110_BASE f4000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) =20 #include "armada-cp110.dtsi" =20 @@ -93,12 +101,6 @@ =20 &cp1_sata0 { status =3D "okay"; - /* CON32 */ - sata-port@1 { - status =3D "okay"; - /* Generic PHY, providing serdes lanes */ - phys =3D <&cp1_comphy5 1>; - }; }; =20 /* U24 */ @@ -138,7 +140,7 @@ =20 &cp1_syscon0 { cp1_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; + compatible =3D "marvell,armada-7k-pinctrl"; =20 cp1_i2c0_pins: cp1-i2c-pins-0 { marvell,pins =3D "mpp37", "mpp38"; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45048): https://edk2.groups.io/g/devel/message/45048 Mute This Topic: https://groups.io/mt/32793675/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-