From nobody Mon May 6 13:53:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45035+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45035+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1565207199; cv=none; d=zoho.com; s=zohoarc; b=DpsvIu2uNmu54ApbTbljceTD96aUcm2CnOKWZPoZFOuaNKCsQpkHScXLAXckoh9cSvxg1F784MwphCtV3F7eznyNa8WWneJ6zMONzIx5BliNDFm8bOJ9vWyOZQl4g653UGC/rFLFQQuQgH+XV2WMm5WqMLgUooPYuEmGLHmt2mQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565207199; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=HWKd7jBwp2jsO+g6YIdohQQt17so9WTBHEomkdtowIM=; b=D1sG+omvN4ujJ247h3GAioyvPZY4ck0vH6wxqouVLDgtmrkwQc/XnXgQEQHQyK6U86s3N2nJ4K38Eh7H71V7IpYQgtNuAd5DP+Q16f0gJlroThdskWlRetY/iwHIhEZPuX+eHSW/PT+lFMkwL7kU8RKpPT/eSY/NrGLxqFLiRrA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45035+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565207199692766.3567114865468; Wed, 7 Aug 2019 12:46:39 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by groups.io with SMTP; Wed, 07 Aug 2019 12:46:38 -0700 X-Received: by mail-lj1-f193.google.com with SMTP id r9so86599577ljg.5 for ; Wed, 07 Aug 2019 12:46:37 -0700 (PDT) X-Gm-Message-State: APjAAAVXNtw8Ib3OrDdsQQbxx+mDe277VHYgZ93ZkA9IJtccAcAnNwMb HP2XqoMW0yLNnnA4FFiBH61x9VmF8man7w== X-Google-Smtp-Source: APXvYqzJGu+nc+wZTCIYdRALf2w4bQLXjnuwLYdwA+seTcpKMuZY1KkVMm9Ya17THbZwIxVDP2vMtQ== X-Received: by 2002:a2e:9657:: with SMTP id z23mr5622176ljh.116.1565207196004; Wed, 07 Aug 2019 12:46:36 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h11sm16691071lfm.14.2019.08.07.12.46.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Aug 2019 12:46:35 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH v2] Marvell/Drivers: XenonDxe: Explicitly disable HS400 Date: Wed, 7 Aug 2019 21:46:12 +0200 Message-Id: <1565207172-8921-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565207199; bh=fPpmk+lL4IlpWkf6GmpuD+BVwCrSuMe1KNcGmtHYg3E=; h=Cc:Date:From:Reply-To:Subject:To; b=H8wSqBgwcJN4l/t24r8X7O78kfjeWyu9nOXsTf3VYbWXrDCIIsgSxmz4bhGLx+5SXHp pMCvqCYIBnOnQwi8VnOs7cXaAHB4wu73ZrgT6uhbJJDTIGfAOxJm4y7X0VnnmzDAY2gq8 AImGQK+Dc5RQLItuSUpzlsG0XIM8eQYwMVU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On another SoC revision, the capability register marks HS400 support as enabled. However in case the interface itself is powered with 3.3V this flag must be unset by the SdMmcOverride protocol callback - otherwise the generic EmmcSwitchToHS400 () would be executed with a failure. Ensure that in case of SlowMode or 3.3V operation, the HS400 capability will be disabled in the SdMmc driver, along with other highest-speed modes. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/= Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h index afc2b2f..2ad23e2 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -55,6 +55,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SDHC_CAP_SDR50 BIT32 #define SDHC_CAP_SDR104 BIT33 #define SDHC_CAP_DDR50 BIT34 +#define SDHC_CAP_HS400 BIT63 #define SDHC_MAX_CURRENT_CAP 0x0048 #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 #define SDHC_FORCE_EVT_ERR_INT 0x0052 diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/= Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c index 3b54459..afd650b 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c @@ -330,7 +330,8 @@ XenonSdMmcCapability ( Capability &=3D ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30); } else { Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | + SDHC_CAP_VOLTAGE_18); } =20 if (!SdMmcDesc.Xenon8BitBusEnabled) { @@ -338,7 +339,7 @@ XenonSdMmcCapability ( } =20 if (SdMmcDesc.XenonSlowModeEnabled) { - Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); + Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_= HS400); } =20 Capability &=3D ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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