From nobody Mon Apr 29 07:17:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+42871+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42871+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1561532675; cv=none; d=zoho.com; s=zohoarc; b=M29qXPP8JznG1r30RlPoltfPp+DolafrkaFQGpNXi4U3IFT83yzZ3CPLi5rh0lQO7qiRc19hOhF3wbV3U6QyyUVdZLXmWh5zMazg7Mtwkt6sI72k5vKbgMJ9ezOgVyFfQLFtZ5GBERVSpcbH931FZi4QxqWbjCn5INCATXOwpww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561532675; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=pItGVxfNlNPo6uqnCHM1cbzTdh+coXk63M7ZUS0ht68=; b=DbNOYbaMvvKQXAwksHRc/jXVjsn6lmVbUGwqInr8Lffh2ZovQiJNe6WAV5D4YFtE5fjJ3YWU7CtLhH796cAwioZ6Ms6os49md2Yt+LrYs6nsaTCs/z///O15qo7qWHDorc+vTJ9gOE+U2WeN4bcRSqdk///7rPU/QMo6ZNBRiwA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42871+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1561532675663587.4680554851549; Wed, 26 Jun 2019 00:04:35 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by groups.io with SMTP; Wed, 26 Jun 2019 00:04:34 -0700 X-Received: by mail-lj1-f196.google.com with SMTP id t28so1012800lje.9 for ; Wed, 26 Jun 2019 00:04:33 -0700 (PDT) X-Gm-Message-State: APjAAAW2A9V3fZiYukxxW57ZxD4c+ypxDaBvtVVVHwCG1wa4tnUnXRrA sEvU1QMhOjWXVYBObf+wyvkBPPNyFgBE5Q== X-Google-Smtp-Source: APXvYqy7pKKBBQT3XfatFpYkaXwF7MPu4IvO++leFrPraa187M2W2N5uD933HCioOhGqBg53BsjWbw== X-Received: by 2002:a2e:94cb:: with SMTP id r11mr1711500ljh.212.1561532671802; Wed, 26 Jun 2019 00:04:31 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p29sm2657101ljp.87.2019.06.26.00.04.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Jun 2019 00:04:31 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-devel] [edk2-platforms: PATCH] Marvell/Drivers: XenonDxe: Explicitly disable HS400 Date: Wed, 26 Jun 2019 09:04:14 +0200 Message-Id: <1561532654-6277-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1561532675; bh=XhlVSoaqAlTc71WjcpdnDhJ+1Mab7eJJXrxh1D8odcc=; h=Cc:Date:From:Reply-To:Subject:To; b=LDzmWDlBPoUOjQ72l5ksL/ghQApM3LXKbbMxzPUeyODc98eqs2AsxtEbJG0qzvzyDGI 6iAISavAc6GqhyhBOT6ej5aUmB8M5oAqpx9tWBrB4BHkWjT+Iuf4WVVDr6R89FqHefjZC +yVLYmorhfhEuwHJnRsSxeTNIKV6yLdPBjk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Ensure that in case of SlowMode or 3.3V operation, also the HS400 capability will be disabled in the SdMmc driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/= Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h index 8bf1835..2d7c7f0 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -82,6 +82,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define SDHC_CAP_SDR50 BIT32 #define SDHC_CAP_SDR104 BIT33 #define SDHC_CAP_DDR50 BIT34 +#define SDHC_CAP_HS400 BIT63 #define SDHC_MAX_CURRENT_CAP 0x0048 #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 #define SDHC_FORCE_EVT_ERR_INT 0x0052 diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/= Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c index 7a9266e..55ebcf8 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c @@ -357,7 +357,8 @@ XenonSdMmcCapability ( Capability &=3D ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30); } else { Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | + SDHC_CAP_VOLTAGE_18); } =20 if (!SdMmcDesc.Xenon8BitBusEnabled) { @@ -365,7 +366,7 @@ XenonSdMmcCapability ( } =20 if (SdMmcDesc.XenonSlowModeEnabled) { - Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); + Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_= HS400); } =20 Capability &=3D ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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