From nobody Sun Feb 8 21:33:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41351+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41351+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1558713573; cv=none; d=zoho.com; s=zohoarc; b=i0yX0hQP4/vGuGCyavUlPQEyaTS0XOu09rFnwg5F1Qq4+SX8bLbn+qtwBN5Gflx6SskAucbDZIx1UPXs952oho6tGjwyG8yC1mh94HwtcpR0fubUEnwpWKCerTgp/6p6OprgrhSVellSvobh7XJzzJbNLo0vaIePprdI7c1Bkyw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558713573; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=S8bQTjEgndOSLgR7x2usxvhfwEisr4hWO/cJy1/1BEc=; b=IyVrU/JQZ2ceF0yT1l10hpqcc8KF9qTYdzzwMhzaNQsQR07RDKNPBYMZ2ILOYCyWu0bSGroA8da2MdZwNKYEgonYXZnxRv/p4H7D5LeGRHzSqgZrogaDcyWhZon3uHY2m4ta5nZoso6DhKjotq1V/0fSZW5Igrqb/1lYQ3pJ5sc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41351+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1558713573750222.33006558804834; Fri, 24 May 2019 08:59:33 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by groups.io with SMTP; Fri, 24 May 2019 08:59:32 -0700 X-Received: by mail-lj1-f196.google.com with SMTP id z1so3635853ljb.3 for ; Fri, 24 May 2019 08:59:32 -0700 (PDT) X-Gm-Message-State: APjAAAX4Bh+I9Ccpi9yP5AKYn3rfQuyVcNik122m6WtvsT1LWGgrhwyv 7f/GHF7gSMvUyHKZaow3DDGXbSipazjZ9A== X-Google-Smtp-Source: APXvYqxRBpyntRqaNV/dABFELpCtuqqNMltcKTf6f/RIu6y7G+6+zvrm2D+SWM6zBAeulXyscEBOrA== X-Received: by 2002:a2e:994:: with SMTP id 142mr45939886ljj.192.1558713570303; Fri, 24 May 2019 08:59:30 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id d18sm685280lfl.95.2019.05.24.08.59.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 May 2019 08:59:29 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH v3 02/14] Marvell/Library: ArmadaSoCDescLib: Add PCIE information Date: Fri, 24 May 2019 17:58:59 +0200 Message-Id: <1558713551-25363-3-git-send-email-mw@semihalf.com> In-Reply-To: <1558713551-25363-1-git-send-email-mw@semihalf.com> References: <1558713551-25363-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558713573; bh=mTYO0hyUBpPpunHHfGYyvp6EYUmq9sX0hdH6pxCX3WA=; h=Cc:Date:From:Reply-To:Subject:To; b=lYjFAaGpZ5pgBdWPf6+T284sblLZhrg6oE7PKI0YHvlENmETIi2kKxVohqfZtv5eOFO 4MJpO46NRCoXojcPdlUXCK4len+hLdZupuq9HuwrAoPY20380XZ6JpYSbK6ddEj57hpQz bk7d+R1E8BX/48n7ZTGnTbCC+Gdlxf6mpto= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCPcieGet ()), which dynamically allocates and fills array with all available PCIE controllers' base addresses. It is needed for the configuration of PCIE, whose support will be added in the upcoming patches. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 +++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 +++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 44 ++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 74883fd..0296d43 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -76,6 +76,12 @@ #define MV_SOC_MDIO_ID(Cp) (Cp) =20 // +// Platform description of PCIE +// +#define MV_SOC_PCIE_PER_CP_COUNT 3 +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000)) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index cd9c9f2..6432916 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -185,6 +185,26 @@ ArmadaSoCDescXhciGet ( IN OUT UINTN *DescCount ); =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieDbiAddresses Array containing PCIE controllers' ba= se + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieDbiAddresses, + IN OUT UINTN *Count + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index b637966..5947601 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -272,6 +272,50 @@ ArmadaSoCDescAhciGet ( return EFI_SUCCESS; } =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' ba= se + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, + IN OUT UINTN *Count + ) +{ + UINTN CpCount, CpIndex, Index; + EFI_PHYSICAL_ADDRESS *BaseAddress; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_PCIE_PER_CP_COUNT; + BaseAddress =3D AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS)= ); + if (BaseAddress =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *PcieBaseAddresses =3D BaseAddress; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) { + *BaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index); + BaseAddress++; + } + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescPp2Get ( --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41351): https://edk2.groups.io/g/devel/message/41351 Mute This Topic: https://groups.io/mt/31746168/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-