From nobody Sun Feb 8 22:43:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41359+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41359+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1558713587; cv=none; d=zoho.com; s=zohoarc; b=GH8NQ5NSIyv6UzEwFWqPCROU9HGWQtA/mVExT2Y4ZlusAUWZIQC0LytvWNYrSHRy7XDjkJzFNkNyv6sfvrqw8voPnXqv7M+tHTjNg6NQG1BLoZ3mXXEWeUMWQdM6FsKHvbtLYBkAvBMt3jbm2hxV5MlQsJzkvUqWxBcvXvxcPRg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558713587; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=0yUT3koWUh2RMtRAt0CP40NWF4yl6ZNyUz31gL2/h7k=; b=bVZHMu5ofzcWXs9sUA5pu88Yh2xjt6W21VD7jKNikMd68+VY++WnTW8C1MkLnztk3Ve6ufzIJevDbbOE4CL49mwvSauoU0hNPTBBsOzw19/j2zxPbTD0OISbT6KFsMNVfRDbjcvwegz3YkX1MlK5Dh6WzDGVYxrY9xvpn9zsu7Q= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41359+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1558713587957256.5987768573955; Fri, 24 May 2019 08:59:47 -0700 (PDT) Return-Path: X-Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by groups.io with SMTP; Fri, 24 May 2019 08:59:43 -0700 X-Received: by mail-lj1-f195.google.com with SMTP id j24so9129227ljg.1 for ; Fri, 24 May 2019 08:59:43 -0700 (PDT) X-Gm-Message-State: APjAAAUNg7rJcAiyU2Z2WNYnUe/h2i7+jmLJuj3ShWWF7wdBa1ctBAna SgDN4QAsXr7RFu+Nr0yuwS9bqOLrmI/TZg== X-Google-Smtp-Source: APXvYqzx6Lf6QMuuyN0MmMZIcTgWHL4u95lPNpD/U3tc1ev22qcoBrGu6Zu91cGGBViDVHpKl3E8Mg== X-Received: by 2002:a2e:880d:: with SMTP id x13mr12369566ljh.72.1558713581356; Fri, 24 May 2019 08:59:41 -0700 (PDT) X-Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id d18sm685280lfl.95.2019.05.24.08.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 May 2019 08:59:40 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH v3 10/14] Marvell/Armada80x0Db: Enable ACPI PCIE support Date: Fri, 24 May 2019 17:59:07 +0200 Message-Id: <1558713551-25363-11-git-send-email-mw@semihalf.com> In-Reply-To: <1558713551-25363-1-git-send-email-mw@semihalf.com> References: <1558713551-25363-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558713587; bh=WJ+wZKguMmdwrvnkISfwOcVBC/suwKnwg72hTQwZedo=; h=Cc:Date:From:Reply-To:Subject:To; b=jir3L61HtFqQdy8wfeNp0igp3hXsg4Rh6cE0TktprRcMzjyqP57eMB90iTY/sszXGOq Byx6fkEMQ6gNndnttdtV2vr6AlGFHdvO0vY3OEcZ5RPxqkkb4lEJlLr7etA5OyiojLVJi 4T4yi8lBLL+Em+NaFZJLKlMjiZ25yCPqDi8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds description of the PCIE controller in ACPI tables of Armada 8040 DB board. Due to the quirky nature of the Synopsys Designware PCIe IP, the type 0 configuration is broadcast and whatever device is plugged into slot, will appear at each 32 device positions of bus0. In order to prevent above, shift the config space base address to the second half of the smallest ATU window (64kB), and limit bus number to 1. Thanks to this, the pci-host-generic driver could be used in OS with ACPI, however with the limitation to support only single device in the slot. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 +++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 +++++++= +++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 +++++++= ++ 4 files changed, 182 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie= .h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg= .aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf index 8367f07..7750817 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf @@ -19,6 +19,7 @@ =20 [Sources] Armada80x0Db/Dsdt.asl + Armada80x0Db/Mcfg.aslc Fadt.aslc Gtdt.aslc Madt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h new file mode 100644 index 0000000..d7b6124 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h @@ -0,0 +1,26 @@ +/** + + Copyright (C) 2019, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#define PCI_BUS_MIN 0x0 +#define PCI_BUS_MAX 0x0 +#define PCI_BUS_COUNT 0x1 +#define PCI_MMIO32_BASE 0xC0000000 +#define PCI_MMIO32_SIZE 0x20000000 +#define PCI_MMIO64_BASE 0x800000000 +#define PCI_MMIO64_SIZE 0x100000000 +#define PCI_IO_BASE 0x0 +#define PCI_IO_SIZE 0x10000 +#define PCI_IO_TRANSLATION 0xEFF00000 +#define PCI_ECAM_BASE 0xE0008000 +#define PCI_ECAM_SIZE 0x10000000 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 822a8e4..5c060a3 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -9,6 +9,7 @@ =20 **/ =20 +#include "Armada80x0Db/Pcie.h" #include "IcuInterrupts.h" =20 DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) @@ -320,5 +321,112 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "AR= MADA8K", 3) } }) } + + // + // PCIe Root Bus + // + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 0x00) // _SEG: PCI Segment + Name (_BBN, 0x00) // _BBN: BIOS Bus Number + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () { 0xFFFF, 0x0, 0x0, 0x40 }, + Package () { 0xFFFF, 0x1, 0x0, 0x40 }, + Package () { 0xFFFF, 0x2, 0x0, 0x40 }, + Package () { 0xFFFF, 0x3, 0x0, 0x40 } + }) + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + PCI_BUS_MIN, // Range Minim= um + PCI_BUS_MAX, // Range Maxim= um + 0x0000, // Translation= Offset + PCI_BUS_COUNT // Length + ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + PCI_MMIO32_BASE, // Range Minim= um + 0xDFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO32_SIZE // Length + ) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + PCI_MMIO64_BASE, // Range Minim= um + 0x8FFFFFFFF, // Range Maxim= um + 0x00000000, // Translation= Offset + PCI_MMIO64_SIZE // Length + ) + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + PCI_IO_BASE, // Range Minim= um + 0x0000FFFF, // Range Maxim= um + PCI_IO_TRANSLATION, // Translation= Address + PCI_IO_SIZE, // Length + , + , + , + TypeTranslation + ) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + PCI_ECAM_BASE, + PCI_ECAM_SIZE + ) + }) + } + Name (SUPP, 0x00) + Name (CTRL, 0x00) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, 0x00, CDW1) + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ + } + + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ + If (LNotEqual (Arg1, One)) + { + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + If (LNotEqual (CDW3, CTRL)) + { + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + } + + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ + Return (Arg3) + } + Else + { + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ + Return (Arg3) + } + } // Method(_OSC) + } } } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc new file mode 100644 index 0000000..da152b7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc @@ -0,0 +1,47 @@ +/** @file + + Memory mapped config space base address table (MCFG) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" +#include "Armada80x0Db/Pcie.h" + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure; +} ACPI_6_0_MCFG_STRUCTURE; +#pragma pack() + +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MCFG_STRUCTURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION), + EFI_ACPI_RESERVED_QWORD + }, { + PCI_ECAM_BASE, // BaseAddress + 0, // PciSegmentGroupNumber + PCI_BUS_MIN, // StartBusNumber + PCI_BUS_MAX, // EndBusNumber + EFI_ACPI_RESERVED_DWORD // Reserved + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41359): https://edk2.groups.io/g/devel/message/41359 Mute This Topic: https://groups.io/mt/31746178/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-